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| REJ09B0300-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2140B Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series H8S/2161B H8S/2160B H8S/2141B H8S/2140B H8S/2145B HD64F2161BV HD64F2160BV HD64F2141BV HD64F2140BV HD64F2145BV HD64F2145B H8S/2148B HD64F2148BV HD64F2148B Rev. 3.00 Revision Date: Mar 21, 2006 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 3.00 Mar 21, 2006 page ii of liv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 3.00 Mar 21, 2006 page iii of liv Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6. Overview 7. Description of Functional Modules * * CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 8. List of Registers 9. Electrical Characteristics 10. Appendix 11. Index Rev. 3.00 Mar 21, 2006 page iv of liv Preface The H8S/2140B Group are microcomputers (MCUs) made up of the H8S/2000 CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. This LSI is equipped with a data transfer controller (DTC) as a bus master, ROM, RAM, an 8-bit PWM timer (PWM), a 14-bit PWM timer (PWMX), a 16-bit free-running timer (FRT), an 8-bit timer (TMR), timer connection, a watchdog timer (WDT), a serial communication interface (SCI), a keyboard buffer controller, a host interface X-bus interface (XBS), a host interface LPC interface (LPC), an 8-bit D/A converter, a 10-bit A/D converter, and I/O ports as on-chip peripheral 2 modules required for system configuration. An I C bus interface (IIC) can also be included as an optional interface. A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM and other kinds of memory. TM A flash memory (F-ZTAT *) version is available for this LSI's ROM. This provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2140B Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2140B Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. Rev. 3.00 Mar 21, 2006 page v of liv * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 27, List of Registers. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx Bit order: Number notation: Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8S/2140B Group manuals: Document Title H8S/2140B Group Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual Document No. This manual REJ09B0139 User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop, High-performance Debugging Interface Tutorial High-performance Embedded Workshop User's Manual Document No. REJ10B0058 ADE-702-282 ADE-702-231 ADE-702-201 Rev. 3.00 Mar 21, 2006 page vi of liv Main Revisions for This Edition Item All Page -- Revision (See Manual for Details) * Notification of change in company name amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. * Product naming convention amended (Before) H8S/2140B Series (After) H8S/2140B Group 1.1 Features 1 * Various peripheral functions Note * added Host Interface LPC interface* Note: * The LPC function is not supported by H8S/2148B and H8S/2145B (5-V version). 2 * On-chip memory Table amended ROM F-ZTAT Version Model HD64F2161BV* HD64F2160BV* HD64F2141BV* HD64F2140BV* HD64F2145BV* HD64F2145B HD64F2148BV* HD64F2148B ROM 128 kbytes 64 kbytes 128 kbytes 64 kbytes 256 kbytes 256 kbytes 128 kbytes 128 kbytes RAM 4 kbytes 4 kbytes 4 kbytes 4 kbytes 8 kbytes 8 kbytes 4 kbytes 4 kbytes Under development Remarks * Compact package Table amended (Before) 18.0 x 18.0 mm (After) 16.0 x 16.0 mm (Before) 16.0 x 16.0 mm (After) 14.0 x 14.0 mm 1.2 Block Diagram Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B Figure 1.2 Internal Block Diagram of H8S/2160B and H8S/2161B 4 3 Note amended Note: * The LPC function and the WUE pin function are not supported by the H8S/2148B and H8S/2145B (5-V version). Figure 1.2 amended (Before) ROM (Flash memory, Masked ROM) (After) ROM (Flash memory) Rev. 3.00 Mar 21, 2006 page vii of liv Item 1.3.1 Pin Arrangement Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B Page 5 Revision (See Manual for Details) Note amended Note: * The LPC function and the WUE pin function are not supported by the H8S/2148B and H8S/2145B (5-V version). 1.3.2 Pin Functions in 11 Each Operating Mode Table 1.1 Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode 2.4.4 Condition-Code Register (CCR) 36 Note * amended Note: * The LPC function and the WUE pin function are not supported by the H8S/2148B and H8S/2145B (5-V version). Table amended Interrupt Mask Bit Masks interrupts when set to 1. NMI is accepted ... 2.6.1 Table of Instructions Classified by Function Table 2.7 Bit Manipulation Instructions (1) 46 Table amended Instruction BIAND Size* B Function C [~( 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 53 Description amended ... absolute address, the upper 24 bits are all assumed ... Rev. 3.00 Mar 21, 2006 page viii of liv Item 2.7.9 Effective Address Calculation Table 2.13 Effective Address Calculation (2) Page 56 Revision (See Manual for Details) Table amended 8 Memory indirect @@aa:8 * Normal mode op abs * Advanced mode op abs 3.4 Address Map in Each Operating Mode Figure 3.7 Address Map for H8S/2145B (1) Figure 3.8 Address Map for H8S/2145B (2) Figure 3.9 Address Map for H8S/2148B(1) 77, 78 Figure 3.7 and Figure 3.8 added 79 Figure 3.9 amended H'01FFFF H'020000 H'FFE080 4.7 Usage Note Figure 4.3 Operation when SP Value Is Old 5.2 Input/Output Pins Table 5.1 Pin Configuration 87 Figure 4.3 amended H'FFEFFF 91 Note * amended Note: * Not supported by the H8S/2148B and H8S/2145B (5-V version). * WUEMRB* Note * amended Note: * Not supported by the H8S/2148B and H8S/2145B (5-V version). 5.3.7 Keyboard Matrix 98 Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Mask Register (WUEMRB) Rev. 3.00 Mar 21, 2006 page ix of liv Item 5.6 Interrupt Control Modes and Interrupt Operation Table 5.4 Interrupt Control Modes Page 105 Revision (See Manual for Details) Table amended Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I and UI bits. Priority levels can be set with ICR. 5.6.5 DTC Activation by Interrupt 7.2.8 DTC Vector Register (DTVECR) 114 151 Description amended ... the DTCE bit of DTC's DTCER, and the DISEL bit of ... Description amended ... software activation interrupt. DTVECR is initialized to H'00 at a reset and in hardware standby mode. 7.4 Location of Register Information and DTC Vector Table Table 7.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs 8.1 Overview Table 8.1 Port Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B 8.4.4 Pin Functions 154 Note 2 amended Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 167 171 Description amended ... in addition to DDR, to control the on/off ... Note * amended Note: * Not supported by the H8S/2148B and H8S/2145B (5-V version). 181 * P37/D15/HDB7/SERIRQ*, ... , P30/D8/HDB0/LAD0* Note amended Note: * Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page x of liv Item 8.9.3 Pin Functions Page 197 Revision (See Manual for Details) 2 * P83/LPCPD* Note 2 amended Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 198 2 * P82/HIFSD/CLKRUN* Note 2 amended Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 199 3 * P80/HA0/PME* Note 3 amended Note: 3. Not supported by the H8S/2148B and H8S/2145B (5-V version). 8.12.4 Pin Functions 213 to 215 * PB7/D7/WUE7* , PB6/D6/WUE6* , PB5/D5/WUE5* , 2 PB4/D4/WUE4* to * PB0/D0/WUE0/HIRQ3/LSMI* Notes amended Note: Not supported by the H8S/2148B and H8S/2145B (5-V version). 11.3.6 Timer Interrupt 265 Enable Register (TIER) Table amended Initial Value (Before) 0 (After) 1 12.7 Input Capture Operation Figure 12.11 Timing of Input Capture Operation 307 Figure 12.11 amended 4 2 2 2 TMRIX Input capture signal Figure 12.12 Timing 307 of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) Figure 12.12 amended TICRR, TICRF read cycle T1 T2 TMRIX Input capture signal Rev. 3.00 Mar 21, 2006 page xi of liv Item 14.4.2 Interval Timer Mode Figure 14.4 OVF Flag Set Timing Page 354 Revision (See Manual for Details) Figure 14.4 amended TCNT H'FF H'00 Overflow signal (internal signal) OVF 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment Figure 14.7 Conflict between TCNT Write and Increment 357 Figure 14.7 amended TCNT write cycle T1 T2 Address Internal write signal 15.1 Features Figure 15.1 Block Diagram of SCI 16.3.5 I C Bus Control Register (ICCR) 2 360 Figure legend amended (Before) SCMR: Smart card mode register (After) SCMR: Serial interface mode register 424 Table amended Bit 5 4 Bit Name MST TRS Initial Value R/W 0 0 R/W R/W Description Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they 2 lose in a bus contention in master mode with the I C bus 2 format. In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition sets these bits in receive mode or transmit mode automatically by hardware. Modification of the TRS bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer. Rev. 3.00 Mar 21, 2006 page xii of liv Item 16.3.5 I C Bus Register (ICCR) 2 Page Revision (See Manual for Details) 2 427, 428 Table amended Bit 1 R/W of I C Bus Interface Interrupt Request Flag (Before) R/W (After) R/(W)* 430 Table 16.5 amended MST 0 0 0 0 0 TRS 1 1 1 1 1 BBSY ESTP STOP IRTR 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 AASX AL -- 0 -- 0 0 AAS -- 0 -- 0 0 ADZ 0 0 0 0 0 ACKB ICDRF ICDRE State 0 0 0 0 0 -- -- -- -- -- 1 0 1 0 1 Transmission end with ICDRE = 0 ICDR write with the above state Transmission end with ICDRE = 1 ICDR write with the above state Automatic data transfer from ICDRT to ICDRS with the above state 2 1/0* -- Table 16.5 Flash and Transfer States (Slave Mode) -- -- -- -- -- -- 2 1/0* -- 16.4.4 Master Receive Operation Figure 16.12 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) 451 Figure 16.12 amended Master transmit mode Master receive mode SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR Undefined va [2] ICDR read (Dummy read) 9 A 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 Data 1 User processing [1] TRS = 0 clear [1] IRIC clear Figure 16.13 Example 451 of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) Figure 16.13 amended SCL is fixed low until stop condition is issued 7 Bit 1 8 Bit 0 [8] A 9 Stop condition generation Data 3 [10] ICDR read (Data 3) [9] IRIC clear [11] Set BBSY = 0 and SCP = 0 (Stop condition instruction issuance) Rev. 3.00 Mar 21, 2006 page xiii of liv Item 16.4.4 Master Receive Operation Figure 16.15 Sample Flowchart for Operations in Master Receive (Receiving a Single Byte) (WAIT = 1) Page 453 Revision (See Manual for Details) Figure 16.15 amended Read ICDR [2] Start receiving. The first read is a dummy read. Read IRIC flag in ICCR No IRIC = 1? [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) Yes Set ACKB = 1 in ICSR [7] Set acknowledge data for the last reception. Figure 16.16 Example 456 of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) Figure 16.16 amended Master tansmit mode Master receive mode SCL (master output) 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 SDA (slave output) SDA (master output) A Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 [3] A [3] Bit 7 Bit 6 Bit 5 Data 2 Bit 4 Bit 3 IRIC 16.4.5 Slave Receive Operation Figure 16.22 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0) 464 Figure title amended Figure 16.23 Example 464 of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0) 16.6 Usage Notes Figure 16.35 ICDR Read and ICCR Access Riming in Slave Transmit Mode 483 485 Figure title amended 10. Notes on WAIT Function Description added Figure 16.35 amended R/W 487, 488 14. Notes on Arbitration Lost in Master Mode Description added Rev. 3.00 Mar 21, 2006 page xiv of liv Item 17.3.1 Keyboard Control Register H (KBCRH) Page 492 Revision (See Manual for Details) Table amended Bit 6 Bit Name KCLKI Initial Value 1 R/W R Description Keyboard Clock In Monitors the KCLK I/O pin. This bit cannot be modified. 0: KCLK I/O pin is low 1: KCLK I/O pin is high 5 KDI 1 R Keyboard Data In Monitors the KDI I/O pin. This bit cannot be modified. 0: KD I/O pin is low 1: KD I/O pin is high 19.4.4 Host Interface Shutdown Function (LPCPD) Table 19.5 Scope of Host Interface Pin Shutdown Section 22 RAM 569 Table 19.5 amended Abbreviation CLKRUN LPCPD Port P82 P83 Scope of Shutdown O x I/O Input Input Notes Hi-Z Needed to clear shutdown state 601 Masked ROM version deleted Product Classification Flash memory version H8S/2161B H8S/2160B H8S/2141B H8S/2140B H8S/2145B H8S/2148B RAM Capacitance 4 kbytes 4 kbytes 4 kbytes 4 kbytes 8 kbytes 4 kbytes RAM Address H'E080-H'EFFF, H'FF00-H'FF7F H'E080-H'EFFF, H'FF00-H'FF7F H'E080-H'EFFF, H'FF00-H'FF7F H'E080-H'EFFF, H'FF00-H'FF7F H'D080-H'EFFF, H'FF00-H'FF7F H'E080-H'EFFF, H'FF00-H'FF7F Section 23 ROM 603 Description amended (Before) This LSI has an on-chip ROM (flash memory or masked ROM). ... (After) This LSI has an on-chip flash memory. ... Rev. 3.00 Mar 21, 2006 page xv of liv Item 23.8.1 Program/ Program-Verify Figure 23.11 Program/ProgramVerify Flowchart Page 625 Revision (See Manual for Details) Figure 23.11 amended Write pulse application subroutine Start of programming START Set SWE bit in FLMCR1 Wait (x) s Store 128-byte program data in program data area and reprogram data area Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR2 Wait () s Set P bit in FLMCR1 Wait (z1) s, (z2) s or (z3) s Clear P bit in FLMCR1 Wait () s Clear PSU bit in FLMCR2 Wait () s Disable WDT Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *6 *4 *6 *5 *6 n=1 m=0 Write 128-byte data in RAM reprogram data area consecutively to flash memory *1 Sub-Routine-Call *6 Apply write pulse z1 s or z2 s Set PV bit in FLMCR1 Wait () s See note 7 for pulse width *6 *6 *6 H'FF dummy write to verify address nn+1 Wait () s Read verify data Increment address *6 *2 NG m=1 NG End Sub Note: 7. Write Pulse Width Number of Writes n Write Time (z) s*6 Write data = verify data? 1 2 3 4 5 6 7 8 9 10 11 12 13 z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 OK 6n? OK Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 Transfer reprogram data to reprogram data area *4 128-byte data verification completed? 998 999 1000 z2 z2 z2 NG OK Clear PV bit in FLMCR1 Wait () s 6 n? NG Note: Use a z3 s write pulse for additional programming. *6 RAM Program data storage area (128 bytes) OK Successively write 128-byte data from additionalprogramming data area in RAM to flash memory *1 Apply write pulse (Additional programming) z3 s *3 *6 NG NG Reprogram data storage area (128 bytes) Additional-programming data storage area (128 bytes) m=0? OK Clear SWE bit in FLMCR1 n (N)? OK Clear SWE bit in FLMCR1 Wait () s Wait () s *6 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing End of programming Programming failure fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of z1 s or z2 s is applied according to the progress of the programming operation. See note 7 for details of the pulse widths. When writing of additional-programming data is executed, a z3 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 6. The values of x, y, z1, z2, z3, , , , , , , and N are shown in sections 28.1.6 and 28.2.6, Flash Memory Characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Comments (D) (V) (X) 0 0 1 Programming completed 0 1 1 1 0 1 0 1 1 Still in erased state; no action Programming incomplete; reprogram *6 Additional-Programming Data Computation Table Reprogram Verify Data AdditionalComments Data (X') (V) Programming Data (Y) 0 0 0 Additional programming to be executed 0 1 1 1 0 1 1 1 1 Additional programming not to be executed Additional programming not to be executed Section of "Masked ROM" deleted Section 24 Clock Pulse Generator Figure 24.1 Block Diagram of Clock Pulse Generator 24.5 Subclock Input Circuit 25.1.1 Standby Control Register (SBYCR) 639 643 Description of "When Subclock Is Not Needed" and "Note on Subclock Usage" added Table amended ... SCK2 to SCK0 must be cleared to B'000. 633 Figure 24.1 amended (Before) 2 to f32 (After) 2 to 32 Rev. 3.00 Mar 21, 2006 page xvi of liv Item 25.1.1 Standby Control Register (SBYCR) Table 25.1 Operating Frequency and Wait Time 26.1 Register Addresses (Address Order) 26.2 Register Bits Page 643 Revision (See Manual for Details) Table amended STS2 STS1 STS0 Wait Time 0 0 0 8192 states 20 MHz 10 MHz 8 MHz 0.4 0.8 1.0 6 MHz 1.3 4 MHz 2.0 2 MHz 4.1 Unit ms 670 Note 2 amended Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 679 Note 5 amended Note: 5. Not supported by the H8S/2148B and H8S/2145B (5-V version). 26.3 Register States in Each Operating Mode 688 Note 2 amended Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 26.4 Register Select Conditions 690 Table amended H8S/2160B, H8S/2161B Register Select Condition (Before) -- (After) No condition 27.1.1 Absolute Maximum Ratings Table 27.1 Absolute Maximum Ratings 27.1.2 DC Characteristics Table 27.2 DC Characteristics (1) 701 Table 27.1 amended item (Ports C to G are added in the H8S/2160B and H8S/2161B.) input voltage (P97, P86, P52, P42) 703 Table 27.2 amended Item P97, P86, P52, P42 (Ports C to G are added in the H8S/2160B and H8S/2161B.) Rev. 3.00 Mar 21, 2006 page xvii of liv Item 27.1.6 Flash Memory Characteristics Table 27.15 Flash Memory Characteristics Page 722 Revision (See Manual for Details) Table 28.15 amended Item Programming time* * * 1 2 4 Symbol Min tP tE NWEC tDRP -- -- Typ 10 100 Max 200 Unit ms/ 128 bytes Test Condition Erase time* * * 1 3 6 1200 ms/block times Years Reprogramming count Data retention time*10 100*8 10,000*9 -- 10 -- -- 723 Notes 8 to 10 added Notes: 8. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 9. Reference value for 25C (as a guideline, rewriting should normally function up to this value). 10. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. 27.2.2 DC Characteristics Table 27.17 DC Characteristics (5) 736 Table 27.17 (5) amended Item Symbol - Min VCC x 0.2 VCCB x 0.2 -- VCC x 0.05 VCCB x 0.05 Typ Max -- -- -- -- VCC x 0.7 VCCB x 0.7 -- Unit V Test Conditions Schmitt P67 to P60 (KWUL (1) VT 26 trigger input = 00)* * , 78 voltage + KIN15 to KIN8* * , VT 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 + - VT - VT 27.2.3 AC Characteristics Table 27.23 Timing of On-Chip Peripheral Modules (1) 27.2.7 Usage Notes Figure 27.5 Connection of VCL Capacitor 752 Table 27.23 (1) amended (Before) tcscyc (After) tScyc 761 Figure 27.5 amended < Product with internal step-down function > HD64F2145B HD64F2148B Rev. 3.00 Mar 21, 2006 page xviii of liv Item 27.3.1 Clock Timing Figure 27.7 Oscillation Settling Timing Page 762 Revision (See Manual for Details) Figure 27.7 amended EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 Appendix B Product Codes 779 Table amended Product Type H8S/2145B Flash memory version (3-V version) Flash memory version (5-V version) Product Code HD64F2145BV HD64F2145B Mark Code F2145BVFA10 F2145BVTE10 F2145BFA20 F2145BTE20 Package (Package Code) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) Appendix C Package Dimensions Figure C.1 Package Dimensions (FP-100B) Figure C.2 Package Dimensions (TFP-100B) Figure C.3 Package Dimensions (TFP-144) 780 Figure replaced 781 Figure replaced 782 Figure replaced Rev. 3.00 Mar 21, 2006 page xix of liv Rev. 3.00 Mar 21, 2006 page xx of liv Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 Features ............................................................................................................................. Block Diagram .................................................................................................................. Pin Arrangement and Functions........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... 1 1 3 5 5 7 18 Section 2 CPU ...................................................................................................................... 25 2.1 Features ............................................................................................................................. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.2 Differences from H8/300 CPU ............................................................................ 2.1.3 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... 2.2.1 Normal Mode....................................................................................................... 2.2.2 Advanced Mode................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 2.4.1 General Registers ................................................................................................. 2.4.2 Program Counter (PC) ......................................................................................... 2.4.3 Extended Control Register (EXR) ....................................................................... 2.4.4 Condition-Code Register (CCR) .......................................................................... 2.4.5 Initial Register Values.......................................................................................... Data Formats..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Table of Instructions Classified by Function ....................................................... 2.6.2 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Register Direct--Rn............................................................................................. 2.7.2 Register Indirect--@ERn .................................................................................... 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn).............. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32.................................... 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 ................................................................. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC).................................... 25 26 27 27 28 28 29 32 33 34 35 35 35 37 37 37 39 40 41 50 51 52 52 52 52 53 53 54 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 3.00 Mar 21, 2006 page xxi of liv 2.8 2.9 2.7.8 Memory Indirect--@@aa:8 ................................................................................ 2.7.9 Effective Address Calculation ............................................................................. Processing States............................................................................................................... Usage Notes ...................................................................................................................... 2.9.1 Note on TAS Instruction Usage ........................................................................... 2.9.2 Note on STM/LDM Instruction Usage ................................................................ 2.9.3 Note on Bit Manipulation Instructions................................................................. 2.9.4 EEPMOV Instruction........................................................................................... 54 55 57 59 59 59 59 61 Section 3 MCU Operating Modes .................................................................................. 63 3.1 3.2 MCU Operating Mode Selection ...................................................................................... Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... 3.2.3 Serial Timer Control Register (STCR) ................................................................ Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 1 ................................................................................................................. 3.3.2 Mode 2 ................................................................................................................. 3.3.3 Mode 3 ................................................................................................................. 3.3.4 Pin Functions in Each Operating Mode ............................................................... Address Map in Each Operating Mode ............................................................................. 63 63 64 65 66 69 69 69 69 70 71 3.3 3.4 Section 4 Exception Handling ......................................................................................... 81 4.1 4.2 4.3 Exception Handling Types and Priority ............................................................................ Exception Sources and Exception Vector Table ............................................................... Reset.................................................................................................................................. 4.3.1 Reset Exception Handling.................................................................................... 4.3.2 Interrupts after Reset............................................................................................ 4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled ........................................ Interrupt Exception Handling............................................................................................ Trap Instruction Exception Handling................................................................................ Stack Status after Exception Handling.............................................................................. Usage Note........................................................................................................................ 81 82 83 83 84 84 85 85 86 87 4.4 4.5 4.6 4.7 Section 5 Interrupt Controller .......................................................................................... 89 5.1 5.2 5.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 5.3.2 Address Break Control Register (ABRKCR)....................................................... 5.3.3 Break Address Registers A to C (BARA to BARC) ............................................ 89 91 91 92 93 94 Rev. 3.00 Mar 21, 2006 page xxii of liv 5.4 5.5 5.6 5.7 5.8 IRQ Sense Control Registers (ISCRH, ISCRL)................................................... IRQ Enable Register (IER) .................................................................................. IRQ Status Register (ISR).................................................................................... Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... Interrupt Sources............................................................................................................... 5.4.1 External Interrupts ............................................................................................... 5.4.2 Internal Interrupts................................................................................................. Interrupt Exception Handling Vector Table...................................................................... Interrupt Control Modes and Interrupt Operation ............................................................. 5.6.1 Interrupt Control Mode 0 ..................................................................................... 5.6.2 Interrupt Control Mode 1 ..................................................................................... 5.6.3 Interrupt Exception Handling Sequence .............................................................. 5.6.4 Interrupt Response Times .................................................................................... 5.6.5 DTC Activation by Interrupt................................................................................ Address Break ................................................................................................................... 5.7.1 Features................................................................................................................ 5.7.2 Block Diagram ..................................................................................................... 5.7.3 Operation ............................................................................................................. 5.7.4 Usage Notes ......................................................................................................... Usage Notes ...................................................................................................................... 5.8.1 Conflict between Interrupt Generation and Disabling ......................................... 5.8.2 Instructions that Disable Interrupts ...................................................................... 5.8.3 Interrupts during Execution of EEPMOV Instruction.......................................... 5.8.4 Setting on Product Incorporating DTC ................................................................ 5.8.5 IRQ Status Register (ISR).................................................................................... 5.3.4 5.3.5 5.3.6 5.3.7 95 96 96 97 100 100 102 102 105 105 107 110 112 113 115 115 115 116 116 118 118 119 119 119 120 Section 6 Bus Controller (BSC) ...................................................................................... 121 6.1 6.2 6.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 6.3.1 Bus Control Register (BCR) ................................................................................ 6.3.2 Wait State Control Register (WSCR) .................................................................. Bus Control ....................................................................................................................... 6.4.1 Bus Specifications................................................................................................ 6.4.2 Advanced Mode................................................................................................... 6.4.3 Normal Mode....................................................................................................... 6.4.4 I/O Select Signals................................................................................................. Basic Bus Interface ........................................................................................................... 6.5.1 Data Size and Data Alignment............................................................................. 6.5.2 Valid Strobes........................................................................................................ 121 123 123 124 125 126 126 127 127 128 129 129 130 6.4 6.5 Rev. 3.00 Mar 21, 2006 page xxiii of liv 6.6 6.7 6.8 6.5.3 Basic Operation Timing ....................................................................................... 6.5.4 Wait Control ........................................................................................................ Burst ROM Interface......................................................................................................... 6.6.1 Basic Operation Timing ....................................................................................... 6.6.2 Wait Control ........................................................................................................ Idle Cycle .......................................................................................................................... Bus Arbitration.................................................................................................................. 6.8.1 Priority of Bus Masters ........................................................................................ 6.8.2 Bus Transfer Timing ............................................................................................ 131 139 141 141 142 142 144 144 144 Section 7 Data Transfer Controller (DTC)................................................................... 145 7.1 7.2 Features ............................................................................................................................. Register Descriptions ........................................................................................................ 7.2.1 DTC Mode Register A (MRA) ............................................................................ 7.2.2 DTC Mode Register B (MRB)............................................................................. 7.2.3 DTC Source Address Register (SAR).................................................................. 7.2.4 DTC Destination Address Register (DAR).......................................................... 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 7.2.6 DTC Transfer Count Register B (CRB)............................................................... 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 7.2.8 DTC Vector Register (DTVECR)........................................................................ Activation Sources ............................................................................................................ Location of Register Information and DTC Vector Table ................................................ Operation .......................................................................................................................... 7.5.1 Normal Mode....................................................................................................... 7.5.2 Repeat Mode ........................................................................................................ 7.5.3 Block Transfer Mode ........................................................................................... 7.5.4 Chain Transfer ..................................................................................................... 7.5.5 Interrupts.............................................................................................................. 7.5.6 Operation Timing................................................................................................. 7.5.7 Number of DTC Execution States........................................................................ Procedures for Using DTC................................................................................................ 7.6.1 Activation by Interrupt......................................................................................... 7.6.2 Activation by Software ........................................................................................ Examples of Use of DTC .................................................................................................. 7.7.1 Normal Mode....................................................................................................... 7.7.2 Software Activation ............................................................................................. Usage Notes ...................................................................................................................... 7.8.1 Module Stop Mode Setting .................................................................................. 7.8.2 On-Chip RAM ..................................................................................................... 7.8.3 DTCE Bit Setting................................................................................................. 145 147 147 149 149 149 150 150 150 151 152 153 155 156 157 158 159 160 160 161 163 163 163 164 164 165 166 166 166 166 7.3 7.4 7.5 7.6 7.7 7.8 Rev. 3.00 Mar 21, 2006 page xxiv of liv 7.8.4 7.8.5 Setting Required on Entering Subactive Mode or Watch Mode .......................... 166 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter ........ 166 Section 8 I/O Ports .............................................................................................................. 167 8.1 8.2 Overview........................................................................................................................... Port 1................................................................................................................................. 8.2.1 Port 1 Data Direction Register (P1DDR)............................................................. 8.2.2 Port 1 Data Register (P1DR)................................................................................ 8.2.3 Port 1 Pull-Up MOS Control Register (P1PCR) .................................................. 8.2.4 Pin Functions ....................................................................................................... 8.2.5 Port 1 Input Pull-Up MOS ................................................................................... Port 2................................................................................................................................. 8.3.1 Port 2 Data Direction Register (P2DDR)............................................................. 8.3.2 Port 2 Data Register (P2DR)................................................................................ 8.3.3 Port 2 Pull-Up MOS Control Register (P2PCR) .................................................. 8.3.4 Pin Functions ....................................................................................................... 8.3.5 Port 2 Input Pull-Up MOS ................................................................................... Port 3................................................................................................................................. 8.4.1 Port 3 Data Direction Register (P3DDR)............................................................. 8.4.2 Port 3 Data Register (P3DR)................................................................................ 8.4.3 Port 3 Pull-Up MOS Control Register (P3PCR) .................................................. 8.4.4 Pin Functions ....................................................................................................... 8.4.5 Port 3 Input Pull-Up MOS ................................................................................... Port 4................................................................................................................................. 8.5.1 Port 4 Data Direction Register (P4DDR)............................................................. 8.5.2 Port 4 Data Register (P4DR)................................................................................ 8.5.3 Pin Functions ....................................................................................................... Port 5................................................................................................................................. 8.6.1 Port 5 Data Direction Register (P5DDR)............................................................. 8.6.2 Port 5 Data Register (P5DR)................................................................................ 8.6.3 Pin Functions ....................................................................................................... Port 6................................................................................................................................. 8.7.1 Port 6 Data Direction Register (P6DDR)............................................................. 8.7.2 Port 6 Data Register (P6DR)................................................................................ 8.7.3 Port 6 Pull-Up MOS Control Register (KMPCR)................................................ 8.7.4 Pin Functions ....................................................................................................... 8.7.5 Port 6 Input Pull-Up MOS ................................................................................... Port 7................................................................................................................................. 8.8.1 Port 7 Input Data Register (P7PIN) ..................................................................... 8.8.2 Pin Functions ....................................................................................................... 167 172 172 173 173 174 174 175 175 176 176 177 178 179 179 180 180 181 181 182 182 183 183 186 186 187 187 188 189 189 190 190 193 193 194 194 8.3 8.4 8.5 8.6 8.7 8.8 Rev. 3.00 Mar 21, 2006 page xxv of liv 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 Port 8................................................................................................................................. 8.9.1 Port 8 Data Direction Register (P8DDR)............................................................. 8.9.2 Port 8 Data Register (P8DR)................................................................................ 8.9.3 Pin Functions ....................................................................................................... Port 9................................................................................................................................. 8.10.1 Port 9 Data Direction Register (P9DDR)............................................................. 8.10.2 Port 9 Data Register (P9DR)................................................................................ 8.10.3 Pin Functions ....................................................................................................... Port A................................................................................................................................ 8.11.1 Port A Data Direction Register (PADDR) ........................................................... 8.11.2 Port A Output Data Register (PAODR) ............................................................... 8.11.3 Port A Input Data Register (PAPIN).................................................................... 8.11.4 Pin Functions ....................................................................................................... 8.11.5 Port A Input Pull-Up MOS .................................................................................. Port B ................................................................................................................................ 8.12.1 Port B Data Direction Register (PBDDR)............................................................ 8.12.2 Port B Output Data Register (PBODR) ............................................................... 8.12.3 Port B Input Data Register (PBPIN) .................................................................... 8.12.4 Pin Functions ....................................................................................................... 8.12.5 Port B Input Pull-Up MOS .................................................................................. Additional Overview for H8S/2160B and H8S/2161B ..................................................... Ports C, D.......................................................................................................................... 8.14.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR) ........................ 8.14.2 Port C and Port D Output Data Registers (PCODR, PDODR) ............................ 8.14.3 Port C and Port D Input Data Registers (PCPIN, PDPIN) ................................... 8.14.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR) ................. 8.14.5 Pin Functions ....................................................................................................... 8.14.6 Input Pull-Up MOS in Ports C and D .................................................................. Ports E, F........................................................................................................................... 8.15.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) .......................... 8.15.2 Port E and Port F Output Data Registers (PEODR, PFODR) .............................. 8.15.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)..................................... 8.15.4 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR) ................... 8.15.5 Pin Functions ....................................................................................................... 8.15.6 Input Pull-Up MOS in Ports E and F ................................................................... Port G................................................................................................................................ 8.16.1 Port G Data Direction Register (PGDDR) ........................................................... 8.16.2 Port G Output Data Register (PGODR) ............................................................... 8.16.3 Port G Input Data Register (PGPIN).................................................................... 8.16.4 Port G Nch-OD Control Register (PGNOCR) ..................................................... 8.16.5 Pin Functions ....................................................................................................... 195 195 196 196 199 200 201 201 204 205 205 206 206 210 211 211 212 212 213 216 216 217 218 219 220 221 221 222 222 223 224 225 226 226 227 227 228 228 229 229 230 Rev. 3.00 Mar 21, 2006 page xxvi of liv Section 9 8-Bit PWM Timer (PWM)............................................................................. 231 9.1 9.2 9.3 Features ............................................................................................................................. Input/Output Pin................................................................................................................ Register Descriptions ........................................................................................................ 9.3.1 PWM Register Select (PWSL)............................................................................. 9.3.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 9.3.3 PWM Data Polarity Registers A and B (PWDPRA, PWDPRB) ......................... 9.3.4 PWM Output Enable Registers A and B (PWOERA, PWOERB) ....................... 9.3.5 Peripheral Clock Select Register (PCSR) ............................................................ Operation .......................................................................................................................... Usage Note........................................................................................................................ 9.5.1 Module Stop Mode Setting .................................................................................. 231 233 233 234 236 236 237 238 239 241 241 9.4 9.5 Section 10 14-Bit PWM Timer (PWMX)..................................................................... 243 10.1 Features ............................................................................................................................. 10.2 Input/Output Pins .............................................................................................................. 10.3 Register Descriptions ........................................................................................................ 10.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL)...................................... 10.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB) ................................. 10.3.3 PWM (D/A) Control Register (DACR) ............................................................... 10.4 Bus Master Interface ......................................................................................................... 10.5 Operation .......................................................................................................................... 10.6 Usage Note........................................................................................................................ 10.6.1 Module Stop Mode Setting .................................................................................. 243 244 244 245 246 248 250 251 257 257 Section 11 16-Bit Free-Running Timer (FRT)............................................................ 259 11.1 Features ............................................................................................................................. 11.2 Input/Output Pins .............................................................................................................. 11.3 Register Descriptions ........................................................................................................ 11.3.1 Free-Running Counter (FRC) .............................................................................. 11.3.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 11.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 11.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 11.3.5 Output Compare Register DM (OCRDM) ........................................................... 11.3.6 Timer Interrupt Enable Register (TIER) .............................................................. 11.3.7 Timer Control/Status Register (TCSR) ................................................................ 11.3.8 Timer Control Register (TCR) ............................................................................. 11.3.9 Timer Output Compare Control Register (TOCR) .............................................. 11.4 Operation .......................................................................................................................... 11.4.1 Pulse Output......................................................................................................... 11.5 Operation Timing.............................................................................................................. 259 261 261 262 262 262 263 263 264 265 268 269 271 271 272 Rev. 3.00 Mar 21, 2006 page xxvii of liv 11.5.1 FRC Increment Timing ........................................................................................ 11.5.2 Output Compare Output Timing .......................................................................... 11.5.3 FRC Clear Timing................................................................................................ 11.5.4 Input Capture Input Timing ................................................................................. 11.5.5 Buffered Input Capture Input Timing .................................................................. 11.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 11.5.7 Timing of Output Compare Flag (OCF) setting................................................... 11.5.8 Timing of FRC Overflow Flag Setting ................................................................ 11.5.9 Automatic Addition Timing................................................................................. 11.5.10 Mask Signal Generation Timing .......................................................................... 11.6 Interrupt Sources............................................................................................................... 11.7 Usage Notes ...................................................................................................................... 11.7.1 Conflict between FRC Write and Clear ............................................................... 11.7.2 Conflict between FRC Write and Increment........................................................ 11.7.3 Conflict between OCR Write and Compare-Match ............................................. 11.7.4 Switching of Internal Clock and FRC Operation ................................................. 11.7.5 Module Stop Mode Setting .................................................................................. 272 273 273 274 274 276 276 277 278 278 279 280 280 281 282 284 285 Section 12 8-Bit Timer (TMR)........................................................................................ 287 12.1 Features ............................................................................................................................. 12.2 Input/Output Pins .............................................................................................................. 12.3 Register Descriptions ........................................................................................................ 12.3.1 Timer Counter (TCNT)........................................................................................ 12.3.2 Time Constant Register A (TCORA)................................................................... 12.3.3 Time Constant Register B (TCORB) ................................................................... 12.3.4 Timer Control Register (TCR) ............................................................................. 12.3.5 Timer Control/Status Register (TCSR) ................................................................ 12.3.6 Input Capture Register (TICR) ............................................................................ 12.3.7 Time Constant Register (TCORC)....................................................................... 12.3.8 Input Capture Registers R and F (TICRR, TICRF).............................................. 12.3.9 Timer Input Select Register (TISR) ..................................................................... 12.4 Operation .......................................................................................................................... 12.4.1 Pulse Output......................................................................................................... 12.5 Operation Timing.............................................................................................................. 12.5.1 TCNT Count Timing............................................................................................ 12.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 12.5.3 Timing of Timer Output at Compare-Match........................................................ 12.5.4 Timing of Counter Clear at Compare-Match ....................................................... 12.5.5 TCNT External Reset Timing .............................................................................. 12.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 12.6 Operation with Cascaded Connection ............................................................................... Rev. 3.00 Mar 21, 2006 page xxviii of liv 287 290 290 291 291 291 291 294 300 300 300 300 301 301 302 302 303 303 304 304 305 305 12.6.1 16-Bit Count Mode .............................................................................................. 12.6.2 Compare-Match Count Mode .............................................................................. 12.7 Input Capture Operation.................................................................................................... 12.8 Interrupt Sources............................................................................................................... 12.9 Usage Notes ...................................................................................................................... 12.9.1 Conflict between TCNT Write and Clear ............................................................ 12.9.2 Conflict between TCNT Write and Increment..................................................... 12.9.3 Conflict between TCOR Write and Compare-Match........................................... 12.9.4 Conflict between Compare-Matches A and B...................................................... 12.9.5 Switching of Internal Clocks and TCNT Operation............................................. 12.9.6 Mode Setting with Cascaded Connection ............................................................ 12.9.7 Module Stop Mode Setting .................................................................................. 305 306 306 309 310 310 311 312 313 313 315 315 Section 13 Timer Connection........................................................................................... 317 13.1 Features ............................................................................................................................. 13.2 Input/Output Pins .............................................................................................................. 13.3 Register Descriptions ........................................................................................................ 13.3.1 Timer Connection Register I (TCONRI) ............................................................. 13.3.2 Timer Connection Register O (TCONRO) .......................................................... 13.3.3 Timer Connection Register S (TCONRS)............................................................ 13.3.4 Edge Sense Register (SEDGR) ............................................................................ 13.4 Operation .......................................................................................................................... 13.4.1 PWM Decoding (PDC Signal Generation) .......................................................... 13.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 13.4.3 Measurement of 8-Bit Timer Divided Waveform Period .................................... 13.4.4 2fH Modification of IHI Signal ........................................................................... 13.4.5 IVI Signal Fall Modification and IHI Synchronization ....................................... 13.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) .......................................................................................................... 13.4.7 HSYNCO Output ................................................................................................. 13.4.8 VSYNCO Output ................................................................................................. 13.4.9 CBLANK Output ................................................................................................. 13.5 Usage Note........................................................................................................................ 13.5.1 Module Stop Mode Setting .................................................................................. 317 319 319 320 323 325 327 329 329 330 332 334 336 338 341 342 343 344 344 Section 14 Watchdog Timer (WDT).............................................................................. 345 14.1 Features ............................................................................................................................. 14.2 Input/Output Pins .............................................................................................................. 14.3 Register Descriptions ........................................................................................................ 14.3.1 Timer Counter (TCNT)........................................................................................ 14.3.2 Timer Control/Status Register (TCSR) ................................................................ 345 347 347 347 348 Rev. 3.00 Mar 21, 2006 page xxix of liv 14.4 Operation .......................................................................................................................... 14.4.1 Watchdog Timer Mode ........................................................................................ 14.4.2 Interval Timer Mode ............................................................................................ 14.4.3 RESO Signal Output Timing ............................................................................... 14.5 Interrupt Sources............................................................................................................... 14.6 Usage Notes ...................................................................................................................... 14.6.1 Notes on Register Access..................................................................................... 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 14.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 14.6.5 System Reset by RESO Signal............................................................................. 14.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ................................................................................................ 352 352 354 355 355 356 356 357 357 357 358 358 359 359 361 361 362 362 362 362 363 364 366 368 369 375 376 377 378 379 380 381 383 387 388 390 393 393 Section 15 Serial Communication Interface (SCI and IrDA) ................................. 15.1 Features ............................................................................................................................. 15.2 Input/Output Pins .............................................................................................................. 15.3 Register Descriptions ........................................................................................................ 15.3.1 Receive Shift Register (RSR) .............................................................................. 15.3.2 Receive Data Register (RDR) .............................................................................. 15.3.3 Transmit Data Register (TDR)............................................................................. 15.3.4 Transmit Shift Register (TSR) ............................................................................. 15.3.5 Serial Mode Register (SMR)................................................................................ 15.3.6 Serial Control Register (SCR).............................................................................. 15.3.7 Serial Status Register (SSR) ................................................................................ 15.3.8 Serial Interface Mode Register (SCMR).............................................................. 15.3.9 Bit Rate Register (BRR) ...................................................................................... 15.3.10 Keyboard Comparator Control Register (KBCOMP) .......................................... 15.4 Operation in Asynchronous Mode .................................................................................... 15.4.1 Data Transfer Format........................................................................................... 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode .................................................................................................................... 15.4.3 Clock.................................................................................................................... 15.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 15.4.5 Data Transmission (Asynchronous Mode)........................................................... 15.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 15.5 Multiprocessor Communication Function......................................................................... 15.5.1 Multiprocessor Serial Data Transmission ............................................................ 15.5.2 Multiprocessor Serial Data Reception ................................................................. 15.6 Operation in Clocked Synchronous Mode ........................................................................ 15.6.1 Clock.................................................................................................................... Rev. 3.00 Mar 21, 2006 page xxx of liv SCI Initialization (Clocked Synchronous Mode) ................................................. Serial Data Transmission (Clocked Synchronous Mode) .................................... Serial Data Reception (Clocked Synchronous Mode).......................................... Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 15.7 IrDA Operation ................................................................................................................. 15.8 Interrupt Sources............................................................................................................... 15.9 Usage Notes ...................................................................................................................... 15.9.1 Module Stop Mode Setting .................................................................................. 15.9.2 Break Detection and Processing .......................................................................... 15.9.3 Mark State and Break Detection .......................................................................... 15.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) .................................................................... 15.9.5 Relation between Writing to TDR and TDRE Flag ............................................. 15.9.6 Restrictions on Using DTC .................................................................................. 15.9.7 SCI Operations during Mode Transitions ............................................................ 15.9.8 Notes on Switching from SCK Pins to Port Pins ................................................. 15.6.2 15.6.3 15.6.4 15.6.5 394 395 398 400 402 405 406 406 406 406 406 406 407 407 411 Section 16 I2C Bus Interface (IIC) (Optional)............................................................. 413 16.1 Features ............................................................................................................................. 16.2 Input/Output Pins .............................................................................................................. 16.3 Register Descriptions ........................................................................................................ 2 16.3.1 I C Bus Data Register (ICDR) ............................................................................. 16.3.2 Slave Address Register (SAR) ............................................................................. 16.3.3 Second Slave Address Register (SARX) ............................................................. 2 16.3.4 I C Bus Mode Register (ICMR) ........................................................................... 2 16.3.5 I C Bus Control Register (ICCR) ......................................................................... 2 16.3.6 I C Bus Status Register (ICSR)............................................................................ 16.3.7 DDC Switch Register (DDCSWR) ...................................................................... 2 16.3.8 I C Bus Extended Control Register (ICXR)......................................................... 16.4 Operation .......................................................................................................................... 2 16.4.1 I C Bus Data Format ............................................................................................ 16.4.2 Initialization ......................................................................................................... 16.4.3 Master Transmit Operation .................................................................................. 16.4.4 Master Receive Operation.................................................................................... 16.4.5 Slave Receive Operation...................................................................................... 16.4.6 Slave Transmit Operation .................................................................................... 16.4.7 IRIC Setting Timing and SCL Control ................................................................ 2 16.4.8 Automatic Switching from Formatless Mode to I C Bus Format ........................ 16.4.9 Operation Using DTC .......................................................................................... 16.4.10 Noise Canceler ..................................................................................................... 413 416 417 417 418 419 421 424 431 436 438 442 442 444 444 448 457 465 468 470 471 472 Rev. 3.00 Mar 21, 2006 page xxxi of liv 16.4.11 Initialization of Internal State .............................................................................. 16.5 Interrupt Sources............................................................................................................... 16.6 Usage Notes ...................................................................................................................... 16.6.1 Module Stop Mode Setting .................................................................................. 473 475 475 488 Section 17 Keyboard Buffer Controller ........................................................................ 489 17.1 Features ............................................................................................................................. 17.2 Input/Output Pins .............................................................................................................. 17.3 Register Descriptions ........................................................................................................ 17.3.1 Keyboard Control Register H (KBCRH) ............................................................. 17.3.2 Keyboard Control Register L (KBCRL) .............................................................. 17.3.3 Keyboard Data Buffer Register (KBBR) ............................................................. 17.4 Operation .......................................................................................................................... 17.4.1 Receive Operation................................................................................................ 17.4.2 Transmit Operation .............................................................................................. 17.4.3 Receive Abort ...................................................................................................... 17.4.4 KCLKI and KDI Read Timing............................................................................. 17.4.5 KCLKO and KDO Write Timing......................................................................... 17.4.6 KBF Setting Timing and KCLK Control ............................................................. 17.4.7 Receive Timing.................................................................................................... 17.4.8 KCLK Fall Interrupt Operation............................................................................ 17.5 Usage Notes ...................................................................................................................... 17.5.1 KBIOE Setting and KCLK Falling Edge Detection............................................. 17.5.2 Module Stop Mode Setting .................................................................................. 489 491 492 492 494 495 496 496 497 500 503 504 505 506 507 508 508 508 Section 18 Host Interface X-Bus Interface (XBS)..................................................... 509 18.1 Features ............................................................................................................................. 18.2 Input/Output Pins .............................................................................................................. 18.3 Register Descriptions ........................................................................................................ 18.3.1 System Control Register 2 (SYSCR2) ................................................................. 18.3.2 Host Interface Control Register (HICR) Host Interface Control Register 2 (HICR2) ............................................................................................................... 18.3.3 Input Data Register (IDR).................................................................................... 18.3.4 Output Data Register 1 (ODR)............................................................................. 18.3.5 Status Register (STR) .......................................................................................... 18.4 Operation .......................................................................................................................... 18.4.1 Host Interface Activation ..................................................................................... 18.4.2 Control States....................................................................................................... 18.4.3 A20 Gate .............................................................................................................. 18.4.4 Host Interface Pin Shutdown Function ................................................................ 18.5 Interrupt Sources............................................................................................................... Rev. 3.00 Mar 21, 2006 page xxxii of liv 509 511 512 512 514 517 517 518 519 519 521 521 523 525 18.5.1 IBF1, IBF2, IBF3, and IBF4 ................................................................................ 18.5.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 18.6 Usage Notes ...................................................................................................................... 18.6.1 Note on Host Interface ......................................................................................... 18.6.2 Module Stop Mode Setting .................................................................................. 525 525 527 527 527 529 529 531 532 533 540 543 544 545 545 545 552 561 562 562 562 565 568 572 574 575 575 575 577 577 577 Section 19 Host Interface LPC Interface (LPC) ......................................................... 19.1 Features ............................................................................................................................. 19.2 Input/Output Pins .............................................................................................................. 19.3 Register Descriptions ........................................................................................................ 19.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)................................. 19.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)................................. 19.3.3 LPC Channel 3 Address Register (LADR3) ........................................................ 19.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 19.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)................................................... 19.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) .................................... 19.3.7 Status Registers 1 to 3 (STR1 to STR3)............................................................... 19.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) ............................... 19.3.9 Host Interface Select Register (HISEL) ............................................................... 19.4 Operation .......................................................................................................................... 19.4.1 Host Interface Activation ..................................................................................... 19.4.2 LPC I/O Cycles .................................................................................................... 19.4.3 A20 Gate .............................................................................................................. 19.4.4 Host Interface Shutdown Function (LPCPD)....................................................... 19.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) .................................... 19.4.6 Host Interface Clock Start Request (CLKRUN) .................................................. 19.5 Interrupt Sources............................................................................................................... 19.5.1 IBFI1 to IBFI3, and ERRI.................................................................................... 19.5.2 SMI, HIRQ1, HIRQ6, HIRQ9 to HIRQ12 .......................................................... 19.6 Usage Notes ...................................................................................................................... 19.6.1 Module Stop Mode Setting .................................................................................. 19.6.2 Notes on Using Host Interface ............................................................................. Section 20 D/A Converter................................................................................................. 579 20.1 Features ............................................................................................................................. 20.2 Input/Output Pins .............................................................................................................. 20.3 Register Descriptions ........................................................................................................ 20.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 20.3.2 D/A Control Register (DACR) ............................................................................ 20.4 Operation .......................................................................................................................... 20.5 Usage Note........................................................................................................................ 579 580 580 580 581 582 583 Rev. 3.00 Mar 21, 2006 page xxxiii of liv 20.5.1 Module Stop Mode Setting .................................................................................. 583 Section 21 A/D Converter................................................................................................. 585 21.1 Features ............................................................................................................................. 21.2 Input/Output Pins .............................................................................................................. 21.3 Register Descriptions ........................................................................................................ 21.3.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 21.3.2 A/D Control/Status Register (ADCSR) ............................................................... 21.3.3 A/D Control Register (ADCR) ............................................................................ 21.3.4 Keyboard Comparator Control Register (KBCOMP) .......................................... 21.4 Operation .......................................................................................................................... 21.4.1 Single Mode......................................................................................................... 21.4.2 Scan Mode ........................................................................................................... 21.4.3 Input Sampling and A/D Conversion Time ......................................................... 21.4.4 External Trigger Input Timing............................................................................. 21.5 Interrupt Sources............................................................................................................... 21.6 A/D Conversion Accuracy Definitions ............................................................................. 21.7 Usage Notes ...................................................................................................................... 21.7.1 Permissible Signal Source Impedance ................................................................. 21.7.2 Influences on Absolute Accuracy ........................................................................ 21.7.3 Setting Range of Analog Power Supply and Other Pins ...................................... 21.7.4 Notes on Board Design ........................................................................................ 21.7.5 Notes on Noise Countermeasures ........................................................................ 21.7.6 Module Stop Mode Setting .................................................................................. 585 587 588 588 589 590 591 592 592 592 594 595 596 596 598 598 598 599 599 599 600 Section 22 RAM .................................................................................................................. 601 Section 23 ROM .................................................................................................................. 603 23.1 Features ............................................................................................................................. 23.2 Mode Transitions .............................................................................................................. 23.3 Block Configuration.......................................................................................................... 23.3.1 Block Configuration of 64-Kbyte Flash Memory ................................................ 23.3.2 Block Configuration of 128-Kbyte Flash Memory .............................................. 23.3.3 Block Configuration of 256-Kbyte Flash Memory .............................................. 23.4 Input/Output Pins .............................................................................................................. 23.5 Register Descriptions ........................................................................................................ 23.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 23.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 23.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 23.6 Operating Modes............................................................................................................... 23.7 On-Board Programming Modes........................................................................................ Rev. 3.00 Mar 21, 2006 page xxxiv of liv 603 605 608 608 609 610 611 611 611 613 614 617 617 23.8 23.9 23.10 23.11 23.12 23.7.1 Boot Mode ........................................................................................................... 23.7.2 User Program Mode............................................................................................. Flash Memory Programming/Erasing ............................................................................... 23.8.1 Program/Program-Verify ..................................................................................... 23.8.2 Erase/Erase-Verify............................................................................................... Program/Erase Protection ................................................................................................. 23.9.1 Hardware Protection ............................................................................................ 23.9.2 Software Protection.............................................................................................. 23.9.3 Error Protection.................................................................................................... Interrupts during Flash Memory Programming/Erasing ................................................... Programmer Mode ............................................................................................................ Usage Notes ...................................................................................................................... 618 622 623 624 626 628 628 628 628 629 630 631 633 634 634 635 637 637 638 638 639 639 640 640 640 640 Section 24 Clock Pulse Generator .................................................................................. 24.1 Oscillator........................................................................................................................... 24.1.1 Connecting Crystal Resonator ............................................................................. 24.1.2 External Clock Input Method............................................................................... 24.2 Duty Correction Circuit .................................................................................................... 24.3 Medium-Speed Clock Divider .......................................................................................... 24.4 Bus Master Clock Select Circuit ....................................................................................... 24.5 Subclock Input Circuit ...................................................................................................... 24.6 Subclock Waveform Forming Circuit ............................................................................... 24.7 Clock Select Circuit .......................................................................................................... 24.8 Processing for X1 and X2 Pins ......................................................................................... 24.9 Usage Notes ...................................................................................................................... 24.9.1 Note on Resonator ............................................................................................... 24.9.2 Notes on Board Design ........................................................................................ Section 25 Power-Down Modes...................................................................................... 641 25.1 Register Descriptions ........................................................................................................ 25.1.1 Standby Control Register (SBYCR) .................................................................... 25.1.2 Low-Power Control Register (LPWRCR) ........................................................... 25.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 25.2 Mode Transitions and LSI States ...................................................................................... 25.3 Medium-Speed Mode........................................................................................................ 25.4 Sleep Mode ....................................................................................................................... 25.5 Software Standby Mode.................................................................................................... 25.6 Hardware Standby Mode .................................................................................................. 25.7 Watch Mode...................................................................................................................... 25.8 Subsleep Mode.................................................................................................................. 25.9 Subactive Mode ................................................................................................................ 641 642 644 645 646 649 650 651 652 653 654 655 Rev. 3.00 Mar 21, 2006 page xxxv of liv 25.10 Module Stop Mode ........................................................................................................... 25.11 Direct Transitions.............................................................................................................. 25.12 Usage Notes ...................................................................................................................... 25.12.1 I/O Port Status...................................................................................................... 25.12.2 Current Consumption when Waiting for Oscillation Stabilization ...................... 25.12.3 DTC Module Stop Mode ..................................................................................... 656 656 657 657 657 657 Section 26 List of Registers.............................................................................................. 659 26.1 26.2 26.3 26.4 Register Addresses (Address Order) ................................................................................. Register Bits...................................................................................................................... Register States in Each Operating Mode........................................................................... Register Select Conditions ................................................................................................ 660 671 680 689 Section 27 Electrical Characteristics.............................................................................. 701 27.1 Electrical Characteristics of H8S/2140B, H8S/2141B, H8S/2160B, and H8S/2161B...... 27.1.1 Absolute Maximum Ratings ................................................................................ 27.1.2 DC Characteristics ............................................................................................... 27.1.3 AC Characteristics ............................................................................................... 27.1.4 A/D Conversion Characteristics........................................................................... 27.1.5 D/A Conversion Characteristics........................................................................... 27.1.6 Flash Memory Characteristics ............................................................................. 27.1.7 Usage Note........................................................................................................... 27.2 Electrical Characteristics of H8S/2145B and H8S/2148B ................................................ 27.2.1 Absolute Maximum Ratings ................................................................................ 27.2.2 DC Characteristics ............................................................................................... 27.2.3 AC Characteristics ............................................................................................... 27.2.4 A/D Conversion Characteristics........................................................................... 27.2.5 D/A Conversion Characteristics........................................................................... 27.2.6 Flash Memory Characteristics ............................................................................. 27.2.7 Usage Notes ......................................................................................................... 27.3 Timing Chart..................................................................................................................... 27.3.1 Clock Timing ....................................................................................................... 27.3.2 Control Signal Timing ......................................................................................... 27.3.3 Bus Timing .......................................................................................................... 27.3.4 On-Chip Peripheral Module Timing .................................................................... 701 701 702 710 719 721 722 724 725 725 727 745 756 758 759 760 762 762 764 765 770 Appendix A I/O Port States in Each Processing State.............................................. 777 Appendix B Product Codes .............................................................................................. 779 Appendix C Package Dimensions................................................................................... 780 Rev. 3.00 Mar 21, 2006 page xxxvi of liv Index .......................................................................................................................................... 783 Rev. 3.00 Mar 21, 2006 page xxxvii of liv Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B.................................................................................................... Figure 1.2 Internal Block Diagram of H8S/2160B and H8S/2161B ..................................... Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B ..... Figure 1.4 Pin Arrangement of H8S/2160B and H8S/2161B................................................ Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ............................................................. Figure 2.2 Stack Structure in Normal Mode ......................................................................... Figure 2.3 Exception Vector Table (Advanced Mode) ......................................................... Figure 2.4 Stack Structure in Advanced Mode ..................................................................... Figure 2.5 Memory Map ....................................................................................................... Figure 2.6 CPU Internal Registers......................................................................................... Figure 2.7 Usage of General Registers.................................................................................. Figure 2.8 Stack .................................................................................................................... Figure 2.9 General Register Data Formats (1) ...................................................................... Figure 2.9 General Register Data Formats (2) ...................................................................... Figure 2.10 Memory Data Formats ......................................................................................... Figure 2.11 Instruction Formats (Examples)........................................................................... Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ................ Figure 2.13 State Transitions................................................................................................... Section 3 MCU Operating Modes Figure 3.1 Address Map for H8S/2140B and H8S/2160B (1)............................................... Figure 3.2 Address Map for H8S/2140B and H8S/2160B (2)............................................... Figure 3.3 Address Map for H8S/2141B and H8S/2161B (1)............................................... Figure 3.4 Address Map for H8S/2141B and H8S/2161B (2)............................................... Figure 3.5 Address Map for H8S/2145BV (1) ...................................................................... Figure 3.6 Address Map for H8S/2145BV (2) ...................................................................... Figure 3.7 Address Map for H8S/2145B (1) ......................................................................... Figure 3.8 Address Map for H8S/2145B (2) ......................................................................... Figure 3.9 Address Map for H8S/2148B (1) ......................................................................... Figure 3.10 Address Map for H8S/2148B (2) ......................................................................... 3 4 5 6 29 29 30 31 32 33 34 35 37 38 39 51 54 58 71 72 73 74 75 76 77 78 79 80 Section 4 Exception Handling Figure 4.1 Reset Sequence (Mode 3) .................................................................................... 84 Figure 4.2 Stack Status after Exception Handling................................................................. 86 Rev. 3.00 Mar 21, 2006 page xxxviii of liv Figure 4.3 Operation when SP Value Is Odd ........................................................................ 87 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ................................................................ Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB..................................................................................................... Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 ........................................................ Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 ................................................................................................................. Figure 5.5 State Transition in Interrupt Control Mode 1....................................................... Figure 5.6 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 ................................................................................................................. Figure 5.7 Interrupt Exception Handling............................................................................... Figure 5.8 DTC and Interrupt Controller .............................................................................. Figure 5.9 Address Break Block Diagram ............................................................................ Figure 5.10 Address Break Timing Example .......................................................................... Figure 5.11 Conflict between Interrupt Generation and Disabling ......................................... Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller ........................................................................ Figure 6.2 IOS Signal Output Timing ................................................................................... Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) ........................ Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)....................... Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space........................................................ Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space........................................................ Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) ..................... Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)....................... Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) ..................... Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)....................... Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode).................................. Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) ................ Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) ................ Figure 6.16 Examples of Idle Cycle Operation ....................................................................... 90 99 101 106 107 109 111 113 115 117 118 122 128 129 130 131 132 133 134 135 136 137 138 140 141 142 143 Section 7 Data Transfer Controller (DTC) Figure 7.1 Block Diagram of DTC........................................................................................ 146 Figure 7.2 Block Diagram of DTC Activation Source Control............................................. 152 Figure 7.3 DTC Register Information Location in Address Space........................................ 153 Rev. 3.00 Mar 21, 2006 page xxxix of liv Figure 7.4 Figure 7.5 Figure 7.6 Figure 7.7 Figure 7.8 Figure 7.9 Figure 7.10 Figure 7.11 DTC Operation Flowchart ................................................................................... Memory Mapping in Normal Mode..................................................................... Memory Mapping in Repeat Mode...................................................................... Memory Mapping in Block Transfer Mode ......................................................... Chain Transfer Operation .................................................................................... DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................ DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ........................................................................................... DTC Operation Timing (Example of Chain Transfer)......................................... 155 156 157 158 159 160 161 161 Section 9 8-Bit PWM Timer (PWM) Figure 9.1 Block Diagram of PWM Timer ........................................................................... 232 Figure 9.2 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000) .... 240 Section 10 14-Bit PWM Timer (PWMX) Figure 10.1 PWM (D/A) Block Diagram ................................................................................ Figure 10.2 PWM D/A Operation ........................................................................................... Figure 10.3 Output Waveform (OS = 0, DADR Corresponds to TL) ...................................... Figure 10.4 Output Waveform (OS = 1, DADR Corresponds to TH) ...................................... Figure 10.5 D/A Data Register Configuration when CFS = 1................................................. Figure 10.6 Output Waveform when DADR = H'0207 (OS = 1)............................................ Section 11 16-Bit Free-Running Timer (FRT) Figure 11.1 Block Diagram of 16-Bit Free-Running Timer.................................................... Figure 11.2 Example of Pulse Output ..................................................................................... Figure 11.3 Increment Timing with Internal Clock Source..................................................... Figure 11.4 Increment Timing with External Clock Source ................................................... Figure 11.5 Timing of Output Compare A Output.................................................................. Figure 11.6 Clearing of FRC by Compare-Match A Signal.................................................... Figure 11.7 Input Capture Input Signal Timing (Usual Case)................................................. Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) ................. Figure 11.9 Buffered Input Capture Timing............................................................................ Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)..................................................... Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ................ Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting................................ Figure 11.13 Timing of Overflow Flag (OVF) Setting ............................................................. Figure 11.14 OCRA Automatic Addition Timing..................................................................... Figure 11.15 Timing of Input Capture Mask Signal Setting ..................................................... Figure 11.16 Timing of Input Capture Mask Signal Clearing................................................... Figure 11.17 FRC Write-Clear Conflict.................................................................................... Figure 11.18 FRC Write-Increment Conflict ............................................................................ Rev. 3.00 Mar 21, 2006 page xl of liv 243 251 253 254 254 255 260 271 272 272 273 273 274 274 275 275 276 277 277 278 278 279 280 281 Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) ............................................. 282 Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used) .................................................... 283 Section 12 8-Bit Timer (TMR) Figure 12.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1)....................................... Figure 12.2 Block Diagram of 8-Bit Timers (TMR_Y and TMR_X) ..................................... Figure 12.3 Pulse Output Example.......................................................................................... Figure 12.4 Count Timing for Internal Clock Input ................................................................ Figure 12.5 Count Timing for External Clock Input (Both Edges) ......................................... Figure 12.6 Timing of CMF Setting at Compare-Match......................................................... Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal ......................... Figure 12.8 Timing of Counter Clear by Compare-Match ...................................................... Figure 12.9 Timing of Counter Clear by External Reset Input ............................................... Figure 12.10 Timing of OVF Flag Setting ................................................................................ Figure 12.11 Timing of Input Capture Operation ..................................................................... Figure 12.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR and TICRF Read)................................................................................................. Figure 12.13 Input Capture Signal Selection ............................................................................ Figure 12.14 Conflict between TCNT Write and Clear ............................................................ Figure 12.15 Conflict between TCNT Write and Increment..................................................... Figure 12.16 Conflict between TCOR Write and Compare-Match........................................... Section 13 Timer Connection Figure 13.1 Block Diagram of Timer Connection................................................................... Figure 13.2 Timing Chart for PWM Decoding ....................................................................... Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)............ Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) ............................ Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods ............................................................................................... Figure 13.6 2fH Modification Timing Chart........................................................................... Figure 13.7 Fall Modification and IHI Synchronization Timing Chart................................... Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart .............................................. Figure 13.9 CBLANK Output Waveform Generation ............................................................ Section 14 Watchdog Timer (WDT) Figure 14.1 Block Diagram of WDT....................................................................................... Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation ............................................. Figure 14.3 Interval Timer Mode Operation ........................................................................... Figure 14.4 OVF Flag Set Timing........................................................................................... 288 289 301 302 302 303 303 304 304 305 307 307 308 310 311 312 318 330 331 331 334 335 337 340 343 346 353 354 354 Rev. 3.00 Mar 21, 2006 page xli of liv Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Output Timing of RESO signal............................................................................ Writing to TCNT and TCSR (WDT_0) ............................................................... Conflict between TCNT Write and Increment..................................................... Sample Circuit for Resetting System by RESO Signal........................................ 355 356 357 358 Section 15 Serial Communication Interface (SCI and IrDA) Figure 15.1 Block Diagram of SCI ......................................................................................... Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .............................................. Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode..................................... Figure 15.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) ......................................................................................... Figure 15.5 Sample SCI Initialization Flowchart.................................................................... Figure 15.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)................................................. Figure 15.7 Sample Serial Transmission Flowchart................................................................ Figure 15.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)................................................. Figure 15.9 Sample Serial Reception Flowchart (1) ............................................................... Figure 15.9 Sample Serial Reception Flowchart (2) ............................................................... Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)......................................... Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart....................................... Figure 15.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ....................................................................... Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ...................................... Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ...................................... Figure 15.14 Data Format in Clocked Synchronous Communication (LSB-First) ................... Figure 15.15 Sample SCI Initialization Flowchart.................................................................... Figure 15.16 Example of SCI Transmit Operation in Clocked Synchronous Mode ................. Figure 15.17 Sample Serial Transmission Flowchart................................................................ Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode................... Figure 15.19 Sample Serial Reception Flowchart ..................................................................... Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ............. Figure 15.21 IrDA Block Diagram............................................................................................ Figure 15.22 IrDA Transmission and Reception....................................................................... Figure 15.23 Example of Transmission Using DTC in Clocked Synchronous Mode............... Figure 15.24 Sample Flowchart for Mode Transition during Transmission ............................. Figure 15.25 Pin States during Transmission in Asynchronous Mode (Internal Clock) ........... Figure 15.26 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock).................................................................................................... Rev. 3.00 Mar 21, 2006 page xlii of liv 360 376 378 379 380 381 382 383 385 386 388 389 390 391 392 393 394 396 397 398 399 401 402 403 407 408 409 409 Figure 15.27 Sample Flowchart for Mode Transition during Reception................................... 410 Figure 15.28 Switching from SCK Pins to Port Pins ................................................................ 411 Figure 15.29 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ........ 411 Section 16 I C Bus Interface (IIC) (Optional) 2 Figure 16.1 Block Diagram of I C Bus Interface .................................................................... 2 Figure 16.2 I C Bus Interface Connections (Example: This LSI as Master) ........................... 2 2 Figure 16.3 I C Bus Data Format (I C Bus Format) ................................................................ 2 Figure 16.4 I C Bus Data Format (Formatless) (IIC_0 Only) ................................................. 2 Figure 16.5 I C Bus Data Format (Serial Format)................................................................... 2 Figure 16.6 I C Bus Timing .................................................................................................... Figure 16.7 Sample Flowchart for IIC Initialization ............................................................... Figure 16.8 Sample Flowchart for Operations in Master Transmit Mode............................... Figure 16.9 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ... Figure 16.10 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ................................................................................... Figure 16.11 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ........... Figure 16.12 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)........................................................................... Figure 16.13 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ................................................................ Figure 16.14 Sample Flowchart for Operations in Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1).............................................................. Figure 16.15 Sample Flowchart for Operations in Master Receive Mode (Receiving a Single Byte) (WAIT = 1) ................................................................ Figure 16.16 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) .......................................................................... Figure 16.17 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1) .......................................................................... Figure 16.18 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1).............. Figure 16.19 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1).. Figure 16.20 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1).. Figure 16.21 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0).............. Figure 16.22 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0) .......................................................................... Figure 16.23 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0) .......................................................................... Figure 16.24 Sample Flowchart for Slave Transmit Mode ....................................................... Figure 16.25 Example of Slave Transmit Mode Operation Timing (MLS = 0) ........................ Figure 16.26 IRIC Setting Timing and SCL Control (1)........................................................... Figure 16.27 IRIC Setting Timing and SCL Control (2)........................................................... 2 415 416 442 442 443 443 444 445 447 448 449 451 451 452 453 456 456 458 460 461 462 464 464 465 467 468 469 Rev. 3.00 Mar 21, 2006 page xliii of liv Figure 16.28 Figure 16.29 Figure 16.30 Figure 16.31 Figure 16.32 Figure 16.33 Figure 16.34 Figure 16.35 Figure 16.36 Figure 16.37 IRIC Setting Timing and SCL Control (3)........................................................... Block Diagram of Noise Canceler ....................................................................... Notes on Reading Master Receive Data............................................................... Flowchart for Start Condition Issuance Instruction for Retransmission and Timing........................................................................................................... Stop Condition Issuance Timing.......................................................................... IRIC Flag Clear Timing on WAIT Operation...................................................... IRIC Flag Clearing Timing When WAIT = 1 ...................................................... ICDR Read and ICCR Access Timing in Slave Transmit Mode ......................... TRS Bit Set Timing in Slave Mode ..................................................................... Diagram of Erroneous Operation when Arbitration is Lost ................................. 470 473 479 481 482 483 484 485 486 487 Section 17 Keyboard Buffer Controller Figure 17.1 Block Diagram of Keyboard Buffer Controller ................................................... Figure 17.2 Keyboard Buffer Controller Connection.............................................................. Figure 17.3 Sample Receive Processing Flowchart ................................................................ Figure 17.4 Receive Timing.................................................................................................... Figure 17.5 (1) Sample Transmit Processing Flowchart.............................................................. Figure 17.5 (2) Sample Transmit Processing Flowchart.............................................................. Figure 17.6 Transmit Timing ................................................................................................. Figure 17.7 (1) Sample Receive Abort Processing Flowchart ..................................................... Figure 17.7 (2) Sample Receive Abort Processing Flowchart ..................................................... Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing.................................................................................................................. Figure 17.9 KCLKI and KDI Read Timing............................................................................. Figure 17.10 KCLKO and KDO Write Timing......................................................................... Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing.................... Figure 17.12 Receive Counter and KBBR Data Load Timing.................................................. Figure 17.13 Example of KCLK Input Fall Interrupt Operation............................................... Figure 17.14 KBIOE Setting and KCLK Falling Edge Detection Timing................................ 490 491 496 497 498 499 500 501 502 502 503 504 505 506 507 508 Section 18 Host Interface X-Bus Interface (XBS) Figure 18.1 Block Diagram of XBS........................................................................................ 510 Figure 18.2 GA20 Output........................................................................................................ 522 Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2) .................................... 526 Section 19 Host Interface LPC Interface (LPC) Figure 19.1 Block Diagram of LPC ........................................................................................ Figure 19.2 Typical LFRAME Timing ................................................................................... Figure 19.3 Abort Mechanism ................................................................................................ Figure 19.4 GA20 Output........................................................................................................ Rev. 3.00 Mar 21, 2006 page xliv of liv 530 564 564 566 Figure 19.5 Figure 19.6 Figure 19.7 Figure 19.8 Power-Down State Termination Timing.............................................................. SERIRQ Timing................................................................................................... Clock Start Request Timing................................................................................. HIRQ Flowchart (Example of Channel 1) ........................................................... 571 572 574 577 Section 20 D/A Converter Figure 20.1 Block Diagram of D/A Converter ........................................................................ 579 Figure 20.2 D/A Converter Operation Example...................................................................... 583 Section 21 A/D Converter Figure 21.1 Block Diagram of A/D Converter ........................................................................ Figure 21.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)............................................................................................................... Figure 21.3 A/D Conversion Timing ...................................................................................... Figure 21.4 External Trigger Input Timing............................................................................. Figure 21.5 A/D Conversion Accuracy Definitions ................................................................ Figure 21.6 A/D Conversion Accuracy Definitions ................................................................ Figure 21.7 Example of Analog Input Circuit......................................................................... Figure 21.8 Example of Analog Input Protection Circuit ....................................................... Figure 21.9 Equivalent Circuit of Analog Input Pin ............................................................... Section 23 ROM Figure 23.1 Block Diagram of Flash Memory ........................................................................ Figure 23.2 Flash Memory State Transitions .......................................................................... Figure 23.3 Boot Mode ........................................................................................................... Figure 23.4 User Program Mode (Example) ........................................................................... Figure 23.5 64-Kbyte Flash Memory Block Configuration .................................................... Figure 23.6 128-Kbyte Flash Memory Block Configuration .................................................. Figure 23.7 256-Kbyte Flash Memory Block Configuration .................................................. Figure 23.8 On-Chip RAM Area in Boot Mode...................................................................... Figure 23.9 ID Code Area ....................................................................................................... Figure 23.10 Programming/Erasing Flowchart Example in User Program Mode..................... Figure 23.11 Program/Program-Verify Flowchart .................................................................... Figure 23.12 Erase/Erase-Verify Flowchart.............................................................................. Figure 23.13 Memory Map in Programmer Mode .................................................................... Section 24 Clock Pulse Generator Figure 24.1 Block Diagram of Clock Pulse Generator............................................................ Figure 24.2 Typical Connection to Crystal Resonator ............................................................ Figure 24.3 Equivalent Circuit of Crystal Resonator .............................................................. Figure 24.4 Example of External Clock Input......................................................................... 586 593 594 595 597 597 598 600 600 604 605 606 607 608 609 610 621 622 623 625 627 630 633 634 634 635 Rev. 3.00 Mar 21, 2006 page xlv of liv Figure 24.5 Figure 24.6 Figure 24.7 Figure 24.8 Figure 24.9 External Clock Input Timing ............................................................................... Timing of External Clock Output Stabilization Delay Time ............................... Subclock Input Timing ........................................................................................ Processing for X1 and X2 Pins ............................................................................ Note on Board Design of Oscillator Circuit Section............................................ 636 637 638 640 640 Section 25 Power-Down Modes Figure 25.1 Mode Transition Diagram.................................................................................... Figure 25.2 Medium-Speed Mode Timing.............................................................................. Figure 25.3 Application Example in Software Standby Mode................................................ Figure 25.4 Hardware Standby Mode Timing......................................................................... Section 27 Electrical Characteristics Figure 27.1 Darlington Pair Drive Circuit (Example)............................................................. Figure 27.2 LED Drive Circuit (Example).............................................................................. Figure 27.3 Output Load Circuit ............................................................................................. Figure 27.4 Connection of VCL Capacitor ............................................................................. Figure 27.5 Connection of VCL Capacitor ............................................................................. Figure 27.6 System Clock Timing .......................................................................................... Figure 27.7 Oscillation Settling Timing.................................................................................. Figure 27.8 Oscillation Setting Timing (Exiting Software Standby Mode) ............................ Figure 27.9 Reset Input Timing .............................................................................................. Figure 27.10 Interrupt Input Timing ......................................................................................... Figure 27.11 Basic Bus Timing (Two-State Access) ................................................................ Figure 27.12 Basic Bus Timing (Three-State Access) .............................................................. Figure 27.13 Basic Bus Timing (Three-State Access with One Wait State) ............................. Figure 27.14 Burst ROM Access Timing (Two-State Access) ................................................. Figure 27.15 Burst ROM Access Timing (One-State Access) .................................................. Figure 27.16 I/O Port Input/Output Timing .............................................................................. Figure 27.17 FRT Input/Output Timing.................................................................................... Figure 27.18 FRT Clock Input Timing ..................................................................................... Figure 27.19 8-Bit Timer Output Timing.................................................................................. Figure 27.20 8-Bit Timer Clock Input Timing.......................................................................... Figure 27.21 8-Bit Timer Reset Input Timing........................................................................... Figure 27.22 PWM, PWMX Output Timing............................................................................. Figure 27.23 SCK Clock Input Timing ..................................................................................... Figure 27.24 SCI Input/Output Timing (Synchronous Mode) .................................................. Figure 27.25 A/D Converter External Trigger Input Timing .................................................... Figure 27.26 WDT Output Timing (RESO).............................................................................. Figure 27.27 Host Interface (XBS) Timing............................................................................... Figure 27.28 Keyboard Buffer Controller Timing .................................................................... Rev. 3.00 Mar 21, 2006 page xlvi of liv 647 650 652 653 708 709 710 724 761 762 762 763 764 764 765 766 767 768 769 770 770 771 771 771 771 772 772 772 772 773 773 774 Figure 27.29 I C Bus Interface Input/Output Timing................................................................ 775 Figure 27.30 Host Interface (LPC) Timing ............................................................................... 775 Figure 27.31 Tester Measurement Condition............................................................................ 776 Appendix C Figure C.1 Figure C.2 Figure C.3 Package Dimensions Package Dimensions (FP-100B) .......................................................................... 780 Package Dimensions (TFP-100B)........................................................................ 781 Package Dimensions (TFP-144) .......................................................................... 782 2 Rev. 3.00 Mar 21, 2006 page xlvii of liv Tables Section 1 Overview Table 1.1 Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode ........................................................................................ 7 Table 1.2 Pin Functions of H8S/2160B and H8S/2161B in Each Operating Mode ............... 12 Table 1.3 Pin Functions.......................................................................................................... 18 Section 2 CPU Table 2.1 Instruction Classification........................................................................................ Table 2.2 Operation Notation................................................................................................. Table 2.3 Data Transfer Instructions ...................................................................................... Table 2.4 Arithmetic Operations Instructions (1)................................................................... Table 2.4 Arithmetic Operations Instructions (2)................................................................... Table 2.5 Logic Operations Instructions ................................................................................ Table 2.6 Shift Instructions .................................................................................................... Table 2.7 Bit Manipulation Instructions (1) ........................................................................... Table 2.7 Bit Manipulation Instructions (2) ........................................................................... Table 2.8 Branch Instructions ................................................................................................ Table 2.9 System Control Instructions ................................................................................... Table 2.10 Block Data Transfer Instructions ........................................................................... Table 2.11 Addressing Modes.................................................................................................. Table 2.12 Absolute Address Access Ranges .......................................................................... Table 2.13 Effective Address Calculation (1) .......................................................................... Table 2.13 Effective Address Calculation (2) .......................................................................... 40 41 42 43 44 45 45 46 47 48 49 50 52 53 55 56 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection............................................................................ 63 Table 3.2 Pin Functions in Each Mode .................................................................................. 70 Section 4 Exception Handling Table 4.1 Exception Types and Priority ................................................................................. 81 Table 4.2 Exception Handling Vector Table .......................................................................... 82 Table 4.3 Status of CCR after Trap Instruction Exception Handling ..................................... 85 Section 5 Interrupt Controller Table 5.1 Pin Configuration ................................................................................................... Table 5.2 Correspondence between Interrupt Source and ICR .............................................. Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ Table 5.4 Interrupt Control Modes......................................................................................... Rev. 3.00 Mar 21, 2006 page xlviii of liv 91 92 103 105 Table 5.5 Table 5.6 Interrupt Response Times....................................................................................... 112 Number of States in Interrupt Handling Routine Execution Status........................ 112 Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration ................................................................................................... Table 6.2 Bus Specifications for Basic Bus Interface ............................................................ Table 6.3 Address Range for IOS Signal Output ................................................................... Table 6.4 Data Buses Used and Valid Strobes ....................................................................... Table 6.5 Pin States in Idle Cycle .......................................................................................... Section 7 Data Transfer Controller (DTC) Table 7.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................ Table 7.2 Register Functions in Normal Mode ...................................................................... Table 7.3 Register Functions in Repeat Mode ....................................................................... Table 7.4 Register Functions in Block Transfer Mode........................................................... Table 7.5 DTC Execution Status ............................................................................................ Table 7.6 Number of States Required for Each Execution Status .......................................... Section 8 I/O Ports Table 8.1 Port Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B ........... Table 8.2 Input Pull-Up MOS States (Port 1) ........................................................................ Table 8.3 Input Pull-Up MOS States (Port 2) ........................................................................ Table 8.4 Input Pull-Up MOS States (Port 3) ........................................................................ Table 8.5 Input Pull-Up MOS States (Port 6) ........................................................................ Table 8.6 Input Pull-Up MOS States (Port A)........................................................................ Table 8.7 Input Pull-Up MOS States (Port B)........................................................................ Table 8.8 H8S/2160B, H8S/2161B Additional Port Functions .............................................. Table 8.9 Input Pull-Up MOS States (Port C and port D)...................................................... Table 8.10 Input Pull-Up MOS States (Port E and port F)....................................................... Section 9 8-Bit PWM Timer (PWM) Table 9.1 Pin Configuration ................................................................................................... Table 9.2 Internal Clock Selection ......................................................................................... Table 9.3 Resolution, PWM Conversion Period and Carrier Frequency when = 10 MHz . Table 9.4 Duty Cycle of Basic Pulse...................................................................................... Table 9.5 Position of Pulses Added to Basic Pulses............................................................... 123 127 128 130 143 154 156 157 158 162 162 168 174 178 181 193 210 216 217 222 227 233 235 236 239 240 Section 10 14-Bit PWM Timer (PWMX) Table 10.1 Pin Configuration ................................................................................................... 244 Table 10.2 Read and Write Access Methods for 16-Bit Registers ........................................... 250 Table 10.3 Settings and Operation (Examples when = 10 MHz) .......................................... 252 Rev. 3.00 Mar 21, 2006 page xlix of liv Table 10.4 Position of Pulse to Be Added to Basic Pulse (CFS = 1) ....................................... 256 Section 11 16-Bit Free-Running Timer (FRT) Table 11.1 Pin Configuration ................................................................................................... 261 Table 11.2 FRT Interrupt Sources............................................................................................ 279 Table 11.3 Switching of Internal Clock and FRC Operation ................................................... 284 Section 12 8-Bit Timer (TMR) Table 12.1 Pin Configuration ................................................................................................... Table 12.2 Clock Input to TCNT and Count Condition ........................................................... Table 12.3 Input Capture Signal Selection............................................................................... Table 12.4 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X......... Table 12.5 Timer Output Priorities .......................................................................................... Table 12.6 Switching of Internal Clocks and TCNT Operation ............................................... Section 13 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 13.7 Table 13.8 Table 13.9 Table 13.10 Table 13.11 Timer Connection Pin Configuration ................................................................................................... Synchronization Signal Connection Enable ........................................................... Registers Accessible by TMR_X/TMR_Y............................................................. Examples of TCR Settings ..................................................................................... Examples of TCORB (Pulse Width Threshold) Settings ....................................... Examples of TCR and TCSR Settings.................................................................... Examples of TCR, TCSR, TOCR, and OCRDM Settings...................................... Examples of TCR, TCSR, and TCORB Settings ................................................... Examples of OCRAR, OCRAF, TCORA, TCORB, TCR, and TCSR Settings ..... HSYNCO Output Modes........................................................................................ VSYNCO Output Modes........................................................................................ 290 293 308 309 313 314 319 322 326 329 329 333 335 337 339 341 342 Section 14 Watchdog Timer (WDT) Table 14.1 Pin Configuration ................................................................................................... 347 Table 14.2 WDT Interrupt Source............................................................................................ 355 Section 15 Serial Communication Interface (SCI and IrDA) Table 15.1 Pin Configuration ................................................................................................... Table 15.2 Relationships between N Setting in BRR and Bit Rate B ...................................... Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... Table 15.8 Serial Transfer Formats (Asynchronous Mode) ..................................................... Rev. 3.00 Mar 21, 2006 page l of liv 361 369 370 373 373 374 374 377 Table 15.9 SSR Status Flags and Receive Data Handling........................................................ 384 Table 15.10 IrCKS2 to IrCKS0 Bit Settings .............................................................................. 404 Table 15.11 SCI Interrupt Sources ............................................................................................. 405 Section 16 Table 16.1 Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Table 16.7 Table 16.8 Table 16.9 Table 16.10 Table 16.11 I C Bus Interface (IIC) (Optional) Pin Configuration ................................................................................................... Communication Format.......................................................................................... 2 I C Transfer Rate .................................................................................................... Flags and Transfer States (Master Mode) .............................................................. Flags and Transfer States (Slave Mode)................................................................. 2 I C Bus Data Format Symbols................................................................................ Examples of Operation Using DTC ....................................................................... IIC Interrupt Sources.............................................................................................. 2 I C Bus Timing (SCL and SDA Outputs)............................................................... Permissible SCL Rise Time (tsr) Values ................................................................. 2 I C Bus Timing (with Maximum Influence of tSr/tSf)............................................... 2 416 420 423 429 430 443 472 475 476 477 478 Section 17 Keyboard Buffer Controller Table 17.1 Pin Configuration ................................................................................................... 491 Section 18 Host Interface X-Bus Interface (XBS) Table 18.1 Pin Configuration ................................................................................................... 511 Table 18.2 Set/Clear Timing for STR Flags............................................................................. 519 Table 18.3 Host Interface Channel Selection and Pin Operation ............................................. 520 Table 18.4 Host Interface Operations from HIF Host, and Slave Operation............................ 521 Table 18.5 GA20 (P81) Set/Clear Timing................................................................................ 522 Table 18.6 Fast A20 Gate Output Signal.................................................................................. 523 Table 18.7 Scope of HIF Pin Shutdown................................................................................... 524 Table 18.8 Input Buffer Full Interrupts .................................................................................... 525 Table 18.9 HIRQ Setting/Clearing Conditions......................................................................... 526 Section 19 Host Interface LPC Interface (LPC) Table 19.1 Pin Configuration ................................................................................................... Table 19.2 Register Selection................................................................................................... Table 19.3 GA20 (P81) Set/Clear Timing................................................................................ Table 19.4 Fast A20 Gate Output Signals ............................................................................... Table 19.5 Scope of Host Interface Pin Shutdown................................................................... Table 19.6 Scope of Initialization in Each Host Interface Mode.............................................. Table 19.7 Receive Complete Interrupts and Error Interrupt ................................................... Table 19.8 HIRQ Setting and Clearing Conditions.................................................................. 531 544 565 567 569 570 575 576 Rev. 3.00 Mar 21, 2006 page li of liv Section 20 D/A Converter Table 20.1 Pin Configuration ................................................................................................... 580 Table 20.2 D/A Channel Enable............................................................................................... 582 Section 21 A/D Converter Table 21.1 Pin Configuration ................................................................................................... 587 Table 21.2 Analog Input Channels and Corresponding ADDR Registers................................ 588 Table 21.3 A/D Conversion Time (Single Mode) .................................................................... 595 Section 23 ROM Table 23.1 Differences between Boot Mode and User Program Mode.................................... Table 23.2 Pin Configuration ................................................................................................... Table 23.3 Operating Modes and ROM ................................................................................... Table 23.4 On-Board Programming Mode Settings................................................................. Table 23.5 Boot Mode Operation............................................................................................. Table 23.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible............................................................................................................... Section 24 Clock Pulse Generator Table 24.1 Damping Resistance Values ................................................................................... Table 24.2 Crystal Resonator Parameters ................................................................................ Table 24.3 External Clock Input Conditions ............................................................................ Table 24.4 External Clock Output Stabilization Delay Time................................................... Table 24.5 Subclock Input Conditions ..................................................................................... 605 611 617 618 620 621 634 635 636 637 638 Section 25 Power-Down Modes Table 25.1 Operating Frequency and Wait Time ..................................................................... 643 Table 25.2 LSI Internal States in Each Mode........................................................................... 648 Section 27 Electrical Characteristics Table 27.1 Absolute Maximum Ratings................................................................................... Table 27.2 DC Characteristics (1) ............................................................................................ Table 27.2 DC Characteristics (2) ............................................................................................ Table 27.2 DC Characteristics (3) When LPC Function Is Used ............................................. Table 27.3 Permissible Output Currents .................................................................................. Table 27.4 Bus Drive Characteristics ....................................................................................... Table 27.5 Clock Timing ......................................................................................................... Table 27.6 Control Signal Timing............................................................................................ Table 27.7 Bus Timing (1) (Normal Mode) ............................................................................. Table 27.7 Bus Timing (2) (Advanced Mode) ......................................................................... Table 27.8 Timing of On-Chip Peripheral Modules (1) ........................................................... Rev. 3.00 Mar 21, 2006 page lii of liv 701 702 705 707 708 709 711 712 713 714 715 Table 27.8 Table 27.9 Table 27.10 Table 27.11 Table 27.12 Table 27.13 Table 27.14 Table 27.15 Table 27.16 Table 27.17 Table 27.17 Table 27.17 Table 27.17 Table 27.17 Table 27.17 Table 27.17 Table 27.18 Table 27.19 Table 27.20 Table 27.21 Table 27.22 Table 27.22 Table 27.23 Table 27.23 Table 27.24 Table 27.25 Table 27.26 Table 27.27 Table 27.28 Table 27.29 Table 27.30 Timing of On-Chip Peripheral Modules (2) ........................................................... Keyboard Buffer Controller Timing....................................................................... 2 I C Bus Timing....................................................................................................... LPC Module Timing .............................................................................................. A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) ................................................... A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) ............................................... D/A Conversion Characteristics ............................................................................. Flash Memory Characteristics................................................................................ Absolute Maximum Ratings................................................................................... DC Characteristics (1) ............................................................................................ DC Characteristics (2) ............................................................................................ DC Characteristics (3) ............................................................................................ DC Characteristics (4) ............................................................................................ DC Characteristics (5) ............................................................................................ DC Characteristics (6) ............................................................................................ DC Characteristics (7) (3-V Version of H8S/2145BV) When LPC Function Is Used.................................................................................. Permissible Output Currents .................................................................................. Bus Drive Characteristics ....................................................................................... Clock Timing ......................................................................................................... Control Signal Timing............................................................................................ Bus Timing (1) (Normal Mode) ............................................................................. Bus Timing (2) (Advanced Mode) ......................................................................... Timing of On-Chip Peripheral Modules (1) ........................................................... Timing of On-Chip Peripheral Modules (2) ........................................................... Keyboard Buffer Controller Timing....................................................................... 2 I C Bus Timing....................................................................................................... LPC Module Timing (For H8S/2145B Only)......................................................... A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) ................................................... A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) ............................................... D/A Conversion Characteristics ............................................................................. Flash Memory Characteristics (Operation Range at Programming/Erasing) ......... 716 717 717 718 719 720 721 722 725 727 729 731 734 736 739 741 742 744 745 746 747 749 751 753 754 754 755 756 757 758 759 Appendix A I/O Port States in Each Processing State Table A.1 I/O Port States in Each Processing State ................................................................ 777 Rev. 3.00 Mar 21, 2006 page liii of liv Rev. 3.00 Mar 21, 2006 page liv of liv Section 1 Overview Section 1 Overview 1.1 Features * High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions * Various peripheral functions Data transfer controller (DTC) 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Timer connection Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI, IrDA) I C bus interface (IIC) Keyboard buffer controller Host interface X-BUS interface (XBS) Host interface LPC interface (LPC)* 8-bit D/A converter 10-bit A/D converter Clock pulse generator Note: * The LPC function is not supported by H8S/2148B and H8S/2145B (5-V version). 2 Rev. 3.00 Mar 21, 2006 page 1 of 788 REJ09B0300-0300 Section 1 Overview * On-chip memory ROM F-ZTAT Version Model HD64F2161BV* HD64F2160BV* HD64F2141BV* HD64F2140BV* HD64F2145BV* HD64F2145B HD64F2148BV* HD64F2148B Note: * 3-V version product ROM 128 kbytes 64 kbytes 128 kbytes 64 kbytes 256 kbytes 256 kbytes 128 kbytes 128 kbytes RAM 4 kbytes 4 kbytes 4 kbytes 4 kbytes 8 kbytes 8 kbytes 4 kbytes 4 kbytes Under development Remarks * General I/O ports I/O pins: 74 (H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B) I/O pins: 114 (H8S/2160B and H8S/2161B) Input-only pins: 8 * Supports various power-down states * Compact package Product H8S/2161B, H8S/2160B H8S/2141B, H8S/2140B H8S/2145B, H8S/2148B Package TQFP-144 QFP-100B TQFP-100B Code TFP-144 FP-100B TFP-100B Body Size 16.0 x 16.0 mm 14.0 x 14.0 mm Pin Pitch 0.4 mm 0.5 mm Rev. 3.00 Mar 21, 2006 page 2 of 788 REJ09B0300-0300 Section 1 Overview 1.2 Block Diagram VCC VCL VSS VSS VSS VSS Port A EXTAL VCCB MD1 MD0 NMI STBY RESO P97/WAIT/SDA0 P96//EXCL Clock pulse generator RES XTAL PA7/A23/KIN15/CIN15/PS2CD PA6/A22/KIN14/CIN14/PS2CC PA5/A21/KIN13/CIN13/PS2BD PA4/A20/KIN12/CIN12/PS2BC PA3/A19/KIN11/CIN11/PS2AD PA2/A18/KIN10/CIN10/PS2AC PA1/A17/KIN9/CIN9 PA0/A16/KIN8/CIN8 P27/A15/PW15/CBLANK P26/A14/PW14 Internal data bus Bus controller H8S/2000 CPU Internal address bus Interrup controller DTC Port 2 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 P93/RD/IOR P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG/ECS2 P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD Port 9 P95/AS/IOS/CS1 P94/HWR/IOW ROM (Flash memory) WDTx 2 channels P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 P37/D15/HDB7/SERIRQ* P36/D14/HDB6/LCLK* P35/D13/HDB5/LRESET* P34/D12/HDB4/LFRAME* P33/D11/HDB3/LAD3* P32/D10/HDB2/LAD2* P31/D9/HDB1/LAD1* P30/D8/HDB0/LAD0* PB7/D7/WUE7* PB6/D6/WUE6* PB5/D5/WUE5* PB4/D4/WUE4* PB3/D3/WUE3*/CS4 PB2/D2/WUE2*/CS3 PB1/D1/WUE1*/HIRQ4/LSCI* PB0/D0/WUE0*/HIRQ3/LSMI* RAM Keyboard buffer controller x 3 channels Port 6 16-bit FRT 8-bit PWM 14-bit PWM 8-bit timer x 4 channels Port 4 Timer connection Host interfaces (LPC*, XBS) 10-bit A/D converter 8-bit D/A converter P52/SCK0/SCL0 P51/RxD0 P50/TxD0 Port 5 IIC x 2 channels Port 8 Port 7 AVCC AVSS P86/IRQ5/SCK1/SCL1 P83/LPCPD* P82/HIFSD/CLKRUN* P85/IRQ4/RxD1 P84/IRQ3/TxD1 Note: * The LPC function and the WUE pin function are not supported by the H8S/2148B and H8S/2145B (5-version). Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B P80/HA0/PME* P81/CS2/GA20 P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVref Rev. 3.00 Mar 21, 2006 page 3 of 788 REJ09B0300-0300 Port B SCI x 3 channels (IrDA x 1 channel) Port 3 Port 1 Section 1 Overview VCC VCC VCL VSS VSS VSS VSS VSS Clock pulse generator X1 X2 RES XTAL EXTAL VCCB MD1 MD0 NMI STBY RESO P97/WAIT/SDA0 P96//EXCL P95/AS/IOS/CS1 P94/HWR/IOW P93/RD/IOR P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG/ECS2 P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD Port A PA7/A23/KIN15/CIN15/PS2CD PA6/A22/KIN14/CIN14/PS2CC PA5/A21/KIN13/CIN13/PS2BD PA4/A20/KIN12/CIN12/PS2BC PA3/A19/KIN11/CIN11/PS2AD PA2/A18/KIN10/CIN10/PS2AC PA1/A17/KIN9/CIN9 PA0/A16/KIN8/CIN8 P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 P37/D15/HDB7/SERIRQ P36/D14/HDB6/LCLK P35/D13/HDB5/LRESET Internal data bus Bus controller H8S/2000 CPU Internal address bus Interrupt controller DTC Port 9 ROM (Flash memory) WDTx 2 channels RAM Keyboard buffer controller x 3 channels Port 6 Port 3 Port 1 Port 2 16-bit FRT 8-bit PWM P34/D12/HDB4/LFRAME P33/D11/HDB3/LAD3 P32/D10/HDB2/LAD2 P31/D9/HDB1/LAD1 P30/D8/HDB0/LAD0 PB7/D7/WUE7 PB6/D6/WUE6 PB5/D5/WUE5 14-bit PWM Port 4 Port B 8-bit timer x 4 channels Timer connection Host interfaces (LPC, XBS) 10-bit A/D converter PB4/D4/WUE4 PB3/D3/WUE3/CS4 PB2/D2/WUE2/CS3 PB1/D1/WUE1/HIRQ4/LSCI PB0/D0/WUE0/HIRQ3/LSMI SCI x 3 channels (IrDA x 1 channel) 8-bit D/A converter Port C P52/SCK0/SCL0 P51/RxD0 P50/TxD0 Port 5 IIC x 2 channels PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 Port D Port 8 Port 7 Port G Port F Port E AVref AVCC P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P82/HIFSD/CLKRUN P81/CS2/GA20 P80/HA0/PME P77/AN7/DA1 P76/AN6/DA0 AVSS PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PD4 PD3 PD2 PD1 PD0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 Rev. 3.00 Mar 21, 2006 page 4 of 788 REJ09B0300-0300 P84/IRQ3/TxD1 P83/LPCPD Figure 1.2 Internal Block Diagram of H8S/2160B and H8S/2161B P70/AN0 Section 1 Overview 1.3 1.3.1 Pin Arrangement and Functions Pin Arrangement P45/TMRI1/HIRQ12/CSYNCI P43/TMCI1/HIRQ11/HSYNCI P44/TMO1/HIRQ1/HSYNCO P27/A15/PW15/CBLANK PB4/D4/WUE4* PB5/D5/WUE5* P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 PB6/D6/WUE6* PB7/D7/WUE7* P22/A10/PW10 P23/A11/PW11 P24/A12/PW12 P25/A13/PW13 P26/A14/PW14 P20/A8/PW8 P21/A9/PW9 VSS P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 PB3/D3/WUE3*/CS4 PB2/D2/WUE2*/CS3 P30/D8 /HDB0/LAD0* P31/D9 /HDB1/LAD1* P32/D10/HDB2/LAD2* P33/D11/HDB3/LAD3* P34/D12/HDB4/LFRAME* P35/D13/HDB5/LRESET* P36/D14/HDB6/LCLK* P37/D15/HDB7/SERIRQ* PB1/D1/WUE1*/HIRQ4/LSCI* PB0/D0/WUE0*/HIRQ3/LSMI* VSS P80/HA0/PME* P81/CS2/GA20 P82/HIFSD/CLKRUN* P83/LPCPD* P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/SCL1 RESO 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 FP-100B TFP-100B (Top view) 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VSS VCC P42/TMRI0/SCK2/SDA1 P47/PWX1 P46/PWX0 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD PA0/A16/KIN8/CIN8 PA1/A17/KIN9/CIN9 AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC AVref P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO PA2/A18/CIN10/KIN10/PS2AC PA3/A19/KIN11/CIN11/PS2AD P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX PA5/A21/KIN13/CIN13/PS2BD PA7/A23/KIN15/CIN15/PS2CD PA6/A22/KIN14/CIN14/PS2CC PA4/A20/KIN12/CIN12/PS2BC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 Note: * The LPC function and the WUE pin function are not supported by the H8S/2148B and H8S/2145B (5-version). Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B Rev. 3.00 Mar 21, 2006 page 5 of 788 REJ09B0300-0300 P90/LWR/IRQ2/ADTRG/ECS2 P92/IRQ0 P97/WAIT/SDA0 P95/AS/IOS/CS1 P94/HWR/IOW P93/RD/IOR P96//EXCL P91/IRQ1 EXTAL STBY VCCB MD1 XTAL MD0 RES VCL NMI VSS Section 1 Overview P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P27/A15/PW15/CBLANK P22/A10/PW10 P23/A11/PW11 P24/A12/PW12 P25/A13/PW13 P26/A14/PW14 P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P63/FTIB/CIN3/KIN3/VFBACKI P64/FTIC/CIN4/KIN4/CLAMPO P65/FTID/CIN5/KIN5 P77/AN7/DA1 P13/A3/PW3 P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 P20/A8/PW8 P21/A9/PW9 P76/AN6/DA0 P12/A2/PW2 P11/A1/PW1 VSS P10/A0/PW0 PB7/D7/WUE7 PB6/D6/WUE6 PB5/D5/WUE5 PB4/D4/WUE4 PB3/D3/WUE3/CS4 PB2/D2/WUE2/CS3 PB1/D1/HIRQ4/WUE1/LSCI PB0/D0/HIRQ3/WUE0/LSMI P30/D8/HDB0/LAD0 P31/D9/HDB1/LAD1 P32/D10/HDB2/LAD2 P33/D11/HDB3/LAD3 P34/D12/HDB4/LFRAME P35/D13/HDB5/LRESET P36/D14/HDB6/LCLK P37/D15/HDB7/SERIRQ P80/HA0/PME P81/CS2/GA20 P82/HIFSD/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/SCL1 P40/TMCI0/TxD2/IrTxD P41/TMO0/RxD2/IrRxD P42/TMRI0/SCK2/SDA1 VSS X1 X2 RESO XTAL EXTAL 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 109 71 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 70 69 68 67 66 65 64 63 62 61 60 59 58 57 VCC VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 P75/AN5 AVCC AVref P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVSS PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 VSS PA0/A16/KIN8/CIN8 PA1/A17/KIN9/CIN9 PA2/A18/KIN10/CIN10/PS2AC PA3/A19/KIN11/CIN11/PS2AD PA4/A20/KIN12/CIN12/PS2BC TFP-144 (Top view) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 P43/TMCI1/HIRQ11/HSYNCI P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P52/SCK0/SCL0 P46/PWX0 P47/PWX1 P51/ RxD0 P50/TxD0 P97/WAIT/SDA0 STBY VCL P95/AS/IOS/CS1 VCC MD1 MD0 VSS RES NMI P94/HWR/IOW P93/RD/IOR PA7/A23/KIN15/CIN15/PS2CD PA6/A22/KIN14/CIN14/PS2CC P96// EXCL P92/IRQ0 P91/IRQ1 P90/LWR/ECS2/IRQ2/ADTRG PA5/A21/KIN13/CIN13/PS2BD PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Figure 1.4 Pin Arrangement of H8S/2160B and H8S/2161B Rev. 3.00 Mar 21, 2006 page 6 of 788 REJ09B0300-0300 VCCB Section 1 Overview 1.3.2 Table 1.1 Pin Functions in Each Operating Mode Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode Pin Name Pin No. FP-100B TFP-100B 1 2 3 4 5 6 7 8 9 10 (B) 11 (B) 12 (N) 13 14 15 16 (N) 17 18 19 20 (B) 21 (B) Mode 1 RES XTAL EXTAL VCCB MD1 MD0 NMI STBY VCL Extended Modes Mode 2, Mode 3 (EXPE = 1) RES XTAL EXTAL VCCB MD1 MD0 NMI STBY VCL PA7/A23/CIN15/ KIN15/PS2CD PA6/A22/CIN14/ KIN14/PS2CC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 VSS P97/WAIT/SDA0 P96//EXCL AS/IOS HWR PA5/A21/CIN13/ KIN13/PS2BD PA4/A20/CIN12/ KIN12/PS2BC Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) RES XTAL EXTAL VCCB MD1 MD0 NMI STBY VCL PA7/CIN15/KIN15/ PS2CD PA6/CIN14/KIN14/ PS2CC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 VSS P97/SDA0 P96//EXCL P95/CS1 P94/IOW PA5/CIN13/KIN13/ PS2BD PA4/CIN12/KIN12/ PS2BC Flash Memory Programmer Mode RES XTAL EXTAL VCC VSS VSS FA9 VCC VCC NC NC NC FA17 NC VSS VCC NC FA16 FA15 NC NC PA7/CIN15/KIN15/ PS2CD PA6/CIN14/KIN14/ PS2CC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 VSS P97/WAIT/SDA0 P96//EXCL AS/IOS HWR PA5/CIN13/KIN13/ PS2BD PA4/CIN12/KIN12/ PS2BC Rev. 3.00 Mar 21, 2006 page 7 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. FP-100B TFP-100B 22 23 24 25 26 Mode 1 RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ ADTRG P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P61/FTOA/CIN1/ KIN1/VSYNCO Extended Modes Mode 2, Mode 3 (EXPE = 1) RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ ADTRG P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P61/FTOA/CIN1/ KIN1/VSYNCO Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) P93/IOR P92/IRQ0 P91/IRQ1 P90/ECS2/IRQ2/ ADTRG P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P61/FTOA/CIN1/ KIN1/VSYNCO P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY P63/FTIB/CIN3/ KIN3/VFBACKI PA3/CIN11/KIN11/ PS2AD PA2/CIN10/KIN10/ PS2AC P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 P66/FTOB/CIN6/ KIN6/IRQ6 P67/TMOX/CIN7/ KIN7/IRQ7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 Flash Memory Programmer Mode WE VSS VCC VCC NC 27 28 29 30 (B) 31 (B) 32 33 34 35 36 37 38 39 40 41 NC NC NC NC NC NC NC NC VSS VCC VCC NC NC NC NC P62/FTIA/CIN2/ P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY KIN2/VSYNCI/TMIY P63/FTIB/CIN3/ KIN3/VFBACKI PA3/CIN11/KIN11/ PS2AD PA2/CIN10/KIN10/ PS2AC P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 P66/FTOB/CIN6/ KIN6/IRQ6 P67/TMOX/CIN7/ KIN7/IRQ7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P63/FTIB/CIN3/ KIN3/VFBACKI PA3/A19/CIN11/ KIN11/PS2AD PA2/A18/CIN10/ KIN10/PS2AC P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 P66/FTOB/CIN6/ KIN6/IRQ6 P67/TMOX/CIN7/ KIN7/IRQ7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 Rev. 3.00 Mar 21, 2006 page 8 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. FP-100B TFP-100B 42 43 44 45 46 47 (B) 48 (B) 49 50 51 (N) 52 53 54 55 56 57 58 59 60 61 62 63 64 Mode 1 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS PA1/CIN9/KIN9 PA0/CIN8/KIN8 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 PB7/D7/WUE7* PB6/D6/WUE6* VCC A15 A14 A13 A12 A11 Extended Modes Mode 2, Mode 3 (EXPE = 1) P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS PA1/A17/CIN9/KIN9 PA0/A16/CIN8/KIN8 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 PB7/D7/WUE7* PB6/D6/WUE6* VCC P27/A15/PW15/ CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS PA1/CIN9/KIN9 PA0/CIN8/KIN8 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 P43/TMCI1/HIRQ11/ HSYNCI P44/TMO1/HIRQ1/ HSYNCO P45/TMRI1/HIRQ12/ CSYNCI P46/PWX0 P47/PWX1 PB7/WUE7* PB6/WUE6* VCC P27/PW15/ CBLANK P26/PW14 P25/PW13 P24/PW12 P23/PW11 Flash Memory Programmer Mode NC NC NC NC VSS NC NC NC NC NC NC NC NC NC NC NC NC VCC CE FA14 FA13 FA12 FA11 Rev. 3.00 Mar 21, 2006 page 9 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. FP-100B TFP-100B 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Mode 1 A10 A9 A8 PB5/D5/WUE5* PB4/D4/WUE4* VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 PB3/D3/WUE3* PB2/D2/WUE2* D8 D9 D10 D11 D12 D13 D14 D15 PB1/D1/WUE1* Extended Modes Mode 2, Mode 3 (EXPE = 1) P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 PB5/D5/WUE5* PB4/D4/WUE4* VSS VSS P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 PB3/D3/WUE3* PB2/D2/WUE2* D8 D9 D10 D11 D12 D13 D14 D15 PB1/D1/WUE1* Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) P22/PW10 P21/PW9 P20/PW8 PB5/WUE5* PB4/WUE4* VSS VSS P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 PB3/WUE3*/CS4 PB2/WUE2*/CS3 P30/HDB0/LAD0* P31/HDB1/LAD1* P32/HDB2/LAD2* P33/HDB3/LAD3* P34/HDB4/ LFRAME* P35/HDB5/ LRESET* P36/HDB6/LCLK* Flash Memory Programmer Mode FA10 OE FA8 NC NC VSS VSS FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 NC NC FO0 FO1 FO2 FO3 FO4 FO5 FO6 P37/HDB7/SERIRQ* FO7 PB1/HIRQ4/WUE1*/ NC LSCI* Rev. 3.00 Mar 21, 2006 page 10 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. FP-100B TFP-100B 91 92 93 94 95 96 97 98 99 (N) 100 Mode 1 PB0/D0/WUE0* VSS P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/ SCL1 RESO Extended Modes Mode 2, Mode 3 (EXPE = 1) PB0/D0/WUE0* VSS P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/ SCL1 RESO Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) PB0/HIRQ3/WUE0*/ LSMI* VSS P80/HA0/PME* P81/CS2/GA20 P82/HIFSD/ CLKRUN* P83/LPCPD* P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/ SCL1 RESO Flash Memory Programmer Mode NC VSS NC NC NC NC NC NC NC NC Notes: The (B) in Pin No. means the VCCB drive and the (N) in Pin No. means the NMOS pushpull/open-drain drive. * The LPC function and the WUE pin function are not supported by the H8S/2148B and H8S/2145B (5-version). Rev. 3.00 Mar 21, 2006 page 11 of 788 REJ09B0300-0300 Section 1 Overview Table 1.2 Pin Functions of H8S/2160B and H8S/2161B in Each Operating Mode Pin Name Pin No. TFP-144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (N) 15 16 17 (N) 18 19 20 21 22 23 24 Mode 1 VCC P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 VSS RES MD1 MD0 NMI STBY VCL Extended modes Mode 2, Mode 3 (EXPE = 1) VCC P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 VSS RES MD1 MD0 NMI STBY VCL P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/WAIT/SDA0 P96//EXCL AS/IOS HWR RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ ADTRG Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) VCC P43/TMCI1/HIRQ11/ HSYNCI P44/TMO1/HIRQ1/ HSYNCO P45/TMRI1/HIRQ12/ CSYNCI P46/PWX0 P47/PWX1 VSS RES MD1 MD0 NMI STBY VCL P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/SDA0 P96//EXCL P95/CS1 P94/IOW P93/IOR P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG/ ECS2 Flash Memory Programmer Mode VCC NC NC NC NC NC VSS RES VSS VSS FA9 VCC VCC FA18 FA17 NC VCC NC FA16 FA15 WE VSS VCC VCC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/WAIT/SDA0 P96//EXCL AS/IOS HWR RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ ADTRG Rev. 3.00 Mar 21, 2006 page 12 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. TFP-144 25 26 27 28 29 30 31 32 33 (B) 34 (B) 35 (B) 36 37 (B) 38 (B) 39 (B) 40 (B) 41 (B) 42 43 44 45 46 47 48 Mode 1 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PA7/CIN15/KIN15/ PS2CD PA6/CIN14/KIN14/ PS2CC PA5/CIN13/KIN13/ PS2BD VCCB PA4/CIN12/KIN12/ PS2BC PA3/CIN11/KIN11/ PS2AD PA2/CIN10/KIN10/ PS2AC PA1/CIN9/KIN9 PA0/CIN8/KIN8 VSS PF7 PF6 PF5 PF4 PF3 PF2 Extended modes Mode 2, Mode 3 (EXPE = 1) PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PA7/A23/CIN15/ KIN15/PS2CD PA6/A22/CIN14/ KIN14/PS2CC PA5/A21/CIN13/ KIN13/PS2BD VCCB PA4/A20/CIN12/ KIN12/PS2BC PA3/A19/CIN11/ KIN11/PS2AD PA2/A18/CIN10/ KIN10/PS2AC PA1/A17/CIN9/KIN9 PA0/A16/CIN8/KIN8 VSS PF7 PF6 PF5 PF4 PF3 PF2 Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PA7/CIN15/KIN15/ PS2CD PA6/CIN14/KIN14/ PS2CC PA5/CIN13/KIN13/ PS2BD VCCB PA4/CIN12/KIN12/ PS2BC PA3/CIN11/KIN11/ PS2AD PA2/CIN10/KIN10/ PS2AC PA1/CIN9/KIN9 PA0/CIN8/KIN8 VSS PF7 PF6 PF5 PF4 PF3 PF2 Flash Memory Programmer Mode NC NC NC NC NC NC NC NC NC NC NC VCC NC NC NC NC NC VSS NC NC NC NC NC NC Rev. 3.00 Mar 21, 2006 page 13 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. TFP-144 49 50 51 (N) 52 (N) 53 (N) 54 (N) 55 (N) 56 (N) 57 (N) 58 (N) 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Mode 1 PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVCC Extended modes Mode 2, Mode 3 (EXPE = 1) PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVCC Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVCC Flash Memory Programmer Mode NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC VCC Rev. 3.00 Mar 21, 2006 page 14 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. TFP-144 77 78 Mode 1 AVref P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P61/FTOA/CIN1/ KIN1/VSYNCO Extended modes Mode 2, Mode 3 (EXPE = 1) AVref P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P61/FTOA/CIN1/ KIN1/VSYNCO Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) AVref P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P61/FTOA/CIN1/ KIN1/VSYNCO P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY P63/FTIB/CIN3/ KIN3/VFBACKI P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 P66/FTOB/CIN6/ KIN6/IRQ6 P67/TMOX/CIN7/ KIN7/IRQ7 VCC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 VSS P27/PW15/ CBLANK P26/PW14 Flash Memory Programmer Mode VCC NC 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 NC NC NC NC NC NC VSS VCC NC NC NC NC NC NC NC NC VSS CE FA14 P62/FTIA/CIN2/ P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY KIN2/VSYNCI/TMIY P63/FTIB/CIN3/ KIN3/VFBACKI P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 P66/FTOB/CIN6/ KIN6/IRQ6 P67/TMOX/CIN7/ KIN7/IRQ7 VCC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 VSS A15 A14 P63/FTIB/CIN3/ KIN3/VFBACKI P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 P66/FTOB/CIN6/ KIN6/IRQ6 P67/TMOX/CIN7/ KIN7/IRQ7 VCC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 VSS P27/A15/PW15/ CBLANK P26/A14/PW14 Rev. 3.00 Mar 21, 2006 page 15 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. TFP-144 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 Mode 1 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 VSS A0 PB7/D7/WUE7 PB6/D6/WUE6 PB5/D5/WUE5 PB4/D4/WUE4 PB3/D3/WUE3 PB2/D2/WUE2 PB1/D1/WUE1 PB0/D0/WUE0 D8 D9 D10 D11 Extended modes Mode 2, Mode 3 (EXPE = 1) P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 VSS P10/A0/PW0 PB7/D7/WUE7 PB6/D6/WUE6 PB5/D5/WUE5 PB4/D4/WUE4 PB3/D3/WUE3 PB2/D2/WUE2 PB1/D1/WUE1 PB0/D0/WUE0 D8 D9 D10 D11 Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 VSS P10/PW0 PB7/WUE7 PB6/WUE6 PB5/WUE5 PB4/WUE4 PB3/WUE3/CS4 PB2/WUE2/CS3 PB1/HIRQ4/WUE1/ LSCI PB0/HIRQ3/WUE0/ LSMI P30/HDB0/LAD0 P31/HDB1/LAD1 P32/HDB2/LAD2 P33/HDB3/LAD3 Flash Memory Programmer Mode FA13 FA12 FA11 FA10 OE FA8 FA7 FA6 FA5 FA4 FA3 FA2 FA1 VSS FA0 NC NC NC NC NC NC NC NC FO0 FO1 FO2 FO3 Rev. 3.00 Mar 21, 2006 page 16 of 788 REJ09B0300-0300 Section 1 Overview Pin Name Pin No. TFP-144 125 126 127 128 129 130 131 132 133 134 135 (N) 136 137 138 (N) 139 140 141 142 143 144 Mode 1 D12 D13 D14 D15 P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/ SCL1 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 VSS X1 X2 RESO XTAL EXTAL Extended modes Mode 2, Mode 3 (EXPE = 1) D12 D13 D14 D15 P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/ SCL1 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 VSS X1 X2 RESO XTAL EXTAL Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) P34/HDB4/LFRAME P35/HDB5/LRESET P36/HDB6/LCLK P37/HDB7/SERIRQ P80/HA0/PME P81/CS2/GA20 P82/HIFSD/ CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/ SCL1 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 VSS X1 X2 RESO XTAL EXTAL Flash Memory Programmer Mode FO4 FO5 FO6 FO7 NC NC NC NC NC NC NC NC NC NC VSS NC NC NC XTAL EXTAL Note: The (B) in Pin No. means the VCCB drive and the (N) in Pin No. means the NMOS pushpull/open-drain drive. Rev. 3.00 Mar 21, 2006 page 17 of 788 REJ09B0300-0300 Section 1 Overview 1.3.3 Table 1.3 Pin Functions Pin Functions Pin No. Type Power Symbol VCC VCL VCCB VSS FP-100B, TFP-100B TFP-144 I/O 59 9 4 1, 86 13 36 Input Input Input Name and Function Power supply pin. Connect the pin to the system power supply. Power supply pin. Connect the pin to VCC. The power supply for the port A input/output buffer. Ground pin. Connect to the system power supply (0 V). Pins for connection to crystal resonators. The EXTAL pin can also input an external clock. See section 25, Clock Pulse Generator, for typical connection diagrams. 15, 70, 71, 7, 42, 95, Input 92 111, 139 2 3 143 144 Input Input Clock XTAL EXTAL EXCL X1 X2 Operating mode control System control MD1 MD0 RES 17 17 -- -- 5 6 1 18 18 140 141 9 10 8 Output Input Input Input Input Supplies the system clock to external devices. Input a 32.768 kHz external subclock. Leave open. Leave open. These pins set the operating mode. These pins should not be changed while the MCU is operating. Reset pin. When this pin becomes low, the chip is reset. Input RESO STBY 100 8 142 12 Output Outputs reset signal to external device. Input When this pin is driven low, a transition is made to hardware standby mode. Rev. 3.00 Mar 21, 2006 page 18 of 788 REJ09B0300-0300 Section 1 Overview Pin No. Type Address bus Symbol A23 to A16 FP-100B, TFP-100B TFP-144 I/O 10, 11, 20, 33, 34, 21, 30, 31, 35, 37, 47, 48 38, 39, 40, 41 60 to 67, 72 to 79 Name and Function Output Address output pins when 16-Mbyte space is used. A15 to A0 Data bus 96 to Output Address output pins 110, 112 128 to 121 Input/ output Input/ output Input Bidirectional data bus for upper byte of 16-bit data. Bidirectional data bus for lower byte of 16-bit data. Requests insertion of a wait state in the bus cycle when accessing external 3state address space. D15 to D8 89 to 82 D7 to D0 57, 58, 68, 113 to 69, 80, 81, 120 90, 91 16 17 Bus control WAIT RD HWR 22 19 21 20 Output When this pin is low, it indicates that the external address space is being read. Output When this pin is low, it indicates that the external address space is being written to. The upper half of the data bus is valid. Output When this pin is low, it indicates that the external address space is being written to. The lower half of the data bus is valid. Output When this pin is low, it indicates that address output on the address bus is valid. Input Input pin for a nonmaskable interrupt request. These pins request a maskable interrupt. LWR 25 24 AS/IOS 18 19 Interrupt signals NMI IRQ0 to IRQ7 7 23 to 25, 97 to 99, 34, 35 11 22 to 24, Input 133 to 135, 84, 85 Rev. 3.00 Mar 21, 2006 page 19 of 788 REJ09B0300-0300 Section 1 Overview Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O 26 27 34 28 29 32 33 50 53 35 49 52 51 54 26 28 60 to 67, 72 to 79 55 56 14 97 49 13 98 50 12 99 51 49 50 78 79 84 80 81 82 83 137 3 85 136 2 138 4 78 80 Input Name and Function The counter clock input pin. 16-bit free- FTCI running FTOA timer (FRT) FTOB FTIA FTIB FTIC FTID 8-bit timer (TMR_0, TMR_1, TMR_X) TMO0 TMO1 TMOX TMCI0 TMCI1 TMRI0 TMRI1 8-bit timer (TMR_X, TMR_Y) 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) Serial communication interface (SCI_0, SCI_1, SCI_2) TMIX TMIY PW15 to PW0 PWX0 PWX1 TxD0 TxD1 TxD2 RxD0 RxD1 RxD2 SCK0 SCK1 SCK2 SCI with IrDA (SCI_2) IrTxD IrRxD Output The output compare A output pin. Output The output compare B output pin. Input Input Input Input The input capture A input pin. The input capture B input pin. The input capture C input pin. The input capture D input pin. Output The waveform output pins for the output compare function. Input Input Input Input pins for the external clock input to counters. The counter reset input pins. The counter event input and counter reset input pins. 96 to Output PWM timer pulse output pins. 110, 112 5 6 16 133 136 15 134 137 14 135 138 136 137 Output PWM D/A pulse output pins. Output Transmit data output pins. Input Receive data input pins. Input/ Clock input/output pins. Output The output type is NMOS push-pull. Output Input and output pins for data encoded for IrDA use. Input Rev. 3.00 Mar 21, 2006 page 20 of 788 REJ09B0300-0300 Section 1 Overview Pin No. Type Keyboard buffer controller Symbol PS2AC PS2BC PS2CC PS2AD PS2BD PS2CD Host interface (XBS) HDB7 to HDB0 CS1, CS2/ ECS2, CS3, CS4 IOR IOW HA0 FP-100B, TFP-100B TFP-144 I/O 31 21 11 30 20 10 89 to 82 18, 94, 25, 81, 80 39 37 34 38 35 33 128 to 121 19, 130, 24, 118, 117 21 20 129 Name and Function Input/ Keyboard buffer controller Output synchronization clock input/output pins. Input/ Keyboard buffer controller data Output input/output pins. Input/ Bidirectional 8-bit bus for accessing Output XBS. Input Input pins for selecting XBS channels 1 to 4. The CS2 or ECS2 input pin is selected with the system control register. Input pin that enables reading from XBS. Input pin that enables writing to XBS. Input pin that indicates whether an access is a data access or command access. 22 19 93 Input Input Input GA20 HIRQ11 HIRQ1 HIRQ12 HIRQ3 HIRQ4 HIFSD 94 52 53 54 91 90 95 130 2 3 4 120 119 131 Output A20 gate control signal output pin. Output Output pins for interrupt requests to the host. Input Control input pin used to place XBS input/output pins in the high-impedance/ cutoff state. Host interface (LPC) LAD3 to LAD0 LFRAME 85 to 82 86 124 to 121 125 Input/ LPC command, address, and data Output input/output pins. Input Input pin that indicates the start of an LPC cycle or forced termination of an abnormal LPC cycle. Input pin that indicates an LPC reset. The LPC clock input pin. LRESET LCLK 87 88 126 127 Input Input Rev. 3.00 Mar 21, 2006 page 21 of 788 REJ09B0300-0300 Section 1 Overview Pin No. Type Host interface (LPC) Symbol SERIRQ FP-100B, TFP-100B TFP-144 I/O 89 128 Name and Function Input/ Input/output pin for LPC serialized host Output interrupts (HIRQ1, SMI, HIRQ6, HIRQ9 to HIRQ12). LSCI, 90, 91, 93 LSMI, PME GA20 94 119, 120, Input/ LPC auxiliary output pins. Functionally, 129 Output they are general I/O ports. 130 Input/ A20 gate control signal output pin. Output Output state monitoring input is possible. Input/ Input/output pin that requests the start Output of LCLK operation when LCLK is stopped. Input Input pin that controls LPC module shutdown. Matrix keyboard input pins. KIN0 to KIN15 are used as key-scan inputs, and P10 to P17 and P20 to P27 are used as key-scan outputs. This allows a maximum 16-output x 16-input, 256-key matrix to be configured. Wakeup event input pins. These pins allow the same kind of wakeup as keywakeup from various sources. Analog input pins. A/D conversion input pins, but since they are also used as digital input/output pins, accuracy will fall. CLKRUN 95 131 LPCPD Keyboard buffer controller KIN0 to KIN15 96 132 26 to 29, 78 to 85, Input 32 to 35, 41 to 37, 48, 47, 31, 35 to 33 30, 21, 20, 11, 10 91, 90, 81, 120 to 80, 69, 68, 113 58, 57 45 to 38 68 to 75 Input WUE0 to WUE7 A/D converter AN7 to AN0 CIN0 to CIN15 Input 26 to 29, 78 to 85, Input 32 to 35, 41 to 37, 48, 47, 31, 35 to 33 30, 21, 20, 11, 10 25 44 45 24 74 75 Input ADTRG D/A converter DA0 DA1 Pin for input of an external trigger to start A/D conversion. Output Analog output pins. Rev. 3.00 Mar 21, 2006 page 22 of 788 REJ09B0300-0300 Section 1 Overview Pin No. Type A/D converter D/A converter AVref 36 77 Input Symbol AVCC FP-100B, TFP-100B TFP-144 I/O 37 76 Input Name and Function The analog power supply pin for the A/D converter and D/A converter. When the A/D and D/A converters are not used, this pin should be connected to the system power supply (+3 V). The reference power supply pin for the A/D converter and D/A converter. When the A/D and D/A converters are not used, this pin should be connected to the system power supply (+3 V). AVSS 46 67 Input The ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). Timer connection synchronous signal input pins. Timer connection VSYNCI HSYNCI CSYNCI VFBACKI HFBACKI VSYNCO HSYNCO CLAMPO CBLANK 28 52 54 29 26 27 53 32 60 12 99 16 51 72 to 79 60 to 67 89 to 82 56 to 49 80 2 4 81 78 79 3 82 96 14 135 17 138 Input Output Timer connection synchronous signal output pins. I C bus interface (IIC) 2 SCL0 SCL1 SDA0 SDA1 P17 to P10 P27 to P20 P37 to P30 P47 to P40 Input/ I C clock I/O pins. The output type is Output NMOS open-drain output. Input/ I C data I/O pins. The output type is Output NMOS open-drain output. 2 2 I/O ports 104 to Input/ Eight input/output pins. 110, 112 Output 96 to 103 Input/ Eight input/output pins. Output 128 to 121 6 to 2, 138 to 136 Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output (The output type of P42 is NMOS pushpull.) Rev. 3.00 Mar 21, 2006 page 23 of 788 REJ09B0300-0300 Section 1 Overview Pin No. Type I/O ports Symbol P52 to P50 P67 to P60 P77 to P70 P86 to P80 P97 to P90 PA7 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 PG7 to PG0 FP-100B, TFP-100B TFP-144 I/O 12 to 14 14 to 16 Name and Function Input/ Three input/output pins. Output (The output type of P52 is NMOS pushpull.) Input/ Eight input/output pins. Output Input Eight input pins. 35 to 32 29 to 26 45 to 38 99 to 93 85 to 78 75 to 68 135 to 129 17 to 24 Input/ Seven input/output pins. Output (The output type of P86 is NMOS pushpull.) Input/ Eight input/output pins. Output (The output type of P97 is NMOS pushpull.) 16 to 19 22 to 25 10, 11, 20, 33 to 35, Input/ Eight input/output pins. 21, 30, 31, 37 to 41 Output 47, 48 57, 58, 68, 113 to 69, 80, 81, 120 90, 91 -- -- -- 87 to 94 59 to 66 25 to 32 Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output Input/ Output Input/ Output Eight input/output pins. Eight input/output pins. (The output type of PG7 to PG0 in the H8S/2160B and the H8S/2161B is NMOS push-pull.) -- -- 43 to 50 51 to 58 Rev. 3.00 Mar 21, 2006 page 24 of 788 REJ09B0300-0300 Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.1 Features * Upward-compatibility with H8/300 and H8/300H CPUs Can execute H8/300 CPU and H8/300H CPU object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) 16 / 8-bit register-register divide: 12 states (DIVXU.B) CPU210A_010020020700 Rev. 3.00 Mar 21, 2006 page 25 of 788 REJ09B0300-0300 Section 2 CPU 16 x 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 / 16-bit register-register divide: 20 states (DIVXU.W) * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * The number of execution states of the MULXU and MULXS instructions Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. Rev. 3.00 Mar 21, 2006 page 26 of 788 REJ09B0300-0300 Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. Rev. 3.00 Mar 21, 2006 page 27 of 788 REJ09B0300-0300 Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. * Address space Linear access to a maximum address space of 64 kbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. (If general register Rn is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended register (En) will be affected.) * Instruction set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception vector table and memory indirect branch addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details on the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack structure In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. Rev. 3.00 Mar 21, 2006 page 28 of 788 REJ09B0300-0300 Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch Note: * Ignored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Normal Mode 2.2.2 Advanced Mode * Address space Linear access to a maximum address space of 16 Mbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. Rev. 3.00 Mar 21, 2006 page 29 of 788 REJ09B0300-0300 Section 2 CPU * Instruction set All instructions and addressing modes can be used. * Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details on the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table. Rev. 3.00 Mar 21, 2006 page 30 of 788 REJ09B0300-0300 Section 2 CPU * Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24 bits) SP CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.4 Stack Structure in Advanced Mode Rev. 3.00 Mar 21, 2006 page 31 of 788 REJ09B0300-0300 Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 64 kbytes H'FFFF 16 Mbytes Program area H'00000000 H'00FFFFFF Data area Not available in this LSI H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.5 Memory Map Rev. 3.00 Mar 21, 2006 page 32 of 788 REJ09B0300-0300 Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers 23 PC 0 76543210 EXR* T -- -- -- -- I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: : Stack pointer SP : Program counter PC EXR : Extended control register : Trace bit T I2 to I0 : Interrupt mask bits CCR : Condition-code register : Interrupt mask bit I UI : User bit or interrupt mask bit Note: * Does not affect operation in this LSI. H U N Z V C : Half-carry flag : User bit : Negative flag : Zero flag : Overflow flag : Carry flag Figure 2.6 CPU Internal Registers Rev. 3.00 Mar 21, 2006 page 33 of 788 REJ09B0300-0300 Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.7 Usage of General Registers Rev. 3.00 Mar 21, 2006 page 34 of 788 REJ09B0300-0300 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR does not affect operation in this LSI. Bit 7 6 to 3 2 to 0 Bit Name T -- I2 I1 I0 Initial Value 0 All 1 All 1 R/W R/W R R/W Description Trace Bit Does not affect operation in this LSI. Reserved These bits are always read as 1. Interrupt Mask Bits 2 to 0 Do not affect operation in this LSI. 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Rev. 3.00 Mar 21, 2006 page 35 of 788 REJ09B0300-0300 Section 2 CPU Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev. 3.00 Mar 21, 2006 page 36 of 788 REJ09B0300-0300 Section 2 CPU 2.4.5 Initial Register Values The program counter (PC) among CPU internal registers is initialized when reset exception handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the interrupt mask (I) bits in CCR and EXR are set to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats of general registers. Data Type 1-bit data General Register RnH Data Image 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 3.00 Mar 21, 2006 page 37 of 788 REJ09B0300-0300 Section 2 CPU Data Type Word data General Register Rn Data Image 15 0 MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 3.00 Mar 21, 2006 page 38 of 788 REJ09B0300-0300 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Image 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M + 1 MSB LSB Longword data Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 MSB LSB Figure 2.10 Memory Data Formats Rev. 3.00 Mar 21, 2006 page 39 of 788 REJ09B0300-0300 Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV 1 1 POP* , PUSH* 5 5 LDM* , STM* 3 3 MOVFPE* , MOVTPE* Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B B/W/L B/W/L B -- -- -- Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS 4 TAS* Logic operations Shift Bit manipulation Branch System control Block data transfer AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 2 Bcc* , JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV 19 4 8 14 5 9 1 Total: 65 Legend: B: Byte size W: Word size L: Longword size. Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5. 5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Rev. 3.00 Mar 21, 2006 page 40 of 788 REJ09B0300-0300 Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: * Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 3.00 Mar 21, 2006 page 41 of 788 REJ09B0300-0300 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions Size* 1 Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. B/W/L MOVFPE MOVTPE POP B B W/L Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. 2 LDM* L L @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. 2 STM* Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Rev. 3.00 Mar 21, 2006 page 42 of 788 REJ09B0300-0300 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.) B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Adds or subtracts the value 1 or 2 to or from data in a general register. (Only the value 1 can be added to or subtracted from byte operands.) L B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Mar 21, 2006 page 43 of 788 REJ09B0300-0300 Section 2 CPU Table 2.4 Instruction DIVXS Arithmetic Operations Instructions (2) Size* B/W 1 Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. 2 TAS* B @ERd - 0, 1 ( Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. Rev. 3.00 Mar 21, 2006 page 44 of 788 REJ09B0300-0300 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L Rd Rd Takes the one's complement (logical complement) of data in a general register. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (shift) Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (rotate) Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. B/W/L Rd (rotate) Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Mar 21, 2006 page 45 of 788 REJ09B0300-0300 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions (1) Size* B Function 1 ( BCLR B 0 ( BNOT B ( BTST B ( BAND B C ( BIAND B C [~( BOR B C ( BIOR B C [( Note: * Size refers to the operand size. B: Byte Rev. 3.00 Mar 21, 2006 page 46 of 788 REJ09B0300-0300 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size* B Function C ( BIXOR B C ( BLD B ( BILD B ( BST B C ( BIST B C ( Note: * Size refers to the operand size. B: Byte Rev. 3.00 Mar 21, 2006 page 47 of 788 REJ09B0300-0300 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Condition Always Never CZ=0 CZ=1 C=0 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev. 3.00 Mar 21, 2006 page 48 of 788 REJ09B0300-0300 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC ORC XORC B B B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP Note: * -- PC + 2 PC Only increments the program counter. Size refers to the operand size. B: Byte W: Word Rev. 3.00 Mar 21, 2006 page 49 of 788 REJ09B0300-0300 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5 + @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W -- 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields, and some have no register field. * Effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition field Specifies the branching condition of Bcc instructions. Rev. 3.00 Mar 21, 2006 page 50 of 788 REJ09B0300-0300 Section 2 CPU (1) Operation field only op NOP, RTS (2) Operation field and register fields op rn rm ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Rev. 3.00 Mar 21, 2006 page 51 of 788 REJ09B0300-0300 Section 2 CPU Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 2.7.1 Register Direct--Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn Register Indirect with Post-Increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. Rev. 3.00 Mar 21, 2006 page 52 of 788 REJ09B0300-0300 Section 2 CPU Register Indirect with Pre-Decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address, the entire address space is accessed. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. Rev. 3.00 Mar 21, 2006 page 53 of 788 REJ09B0300-0300 Section 2 CPU 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode Rev. 3.00 Mar 21, 2006 page 54 of 788 REJ09B0300-0300 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct (Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 0 Register indirect (@ERn) 31 24 23 0 General register contents op 3 r Don't care Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 31 0 General register contents op r disp 31 Sign extension 31 0 disp 24 23 0 Don't care 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 0 31 24 23 0 General register contents Don't care op r 31 1, 2, or 4 * Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 3.00 Mar 21, 2006 page 55 of 788 REJ09B0300-0300 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care * Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Rev. 3.00 Mar 21, 2006 page 56 of 788 REJ09B0300-0300 Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. * Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state In a product which has a bus master other than the CPU, such as a data transfer controller (DTC), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. For details, see section 6, Bus Controller (BSC). * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 57 of 788 REJ09B0300-0300 Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request Bus-released state SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 SLEEP instruction with LSON = 0, SSBY = 0 End of exception handling Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt request RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details, refer to section 26, Power-Down Modes. Figure 2.13 State Transitions Rev. 3.00 Mar 21, 2006 page 58 of 788 REJ09B0300-0300 Section 2 CPU 2.9 2.9.1 Usage Notes Note on TAS Instruction Usage When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers ER0, ER1, ER4 and ER5. 2.9.2 Note on STM/LDM Instruction Usage ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored by one STM/LDM instruction. The following ranges can be specified in the register list. Two registers: ER0-ER1, ER2-ER3, or ER4-ER5 Three registers: ER0-ER2 or ER4-ER6 Four registers: ER0-ER3 The STM/LDM instruction including ER7 is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. 2.9.3 Note on Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where a register containing a write-only bit is used or a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. Example: The BCLR instruction is executed for DDR in port 4. P47 and P46 are input pins, with a low-level signal input at P47 and a high-level signal input at P46. P45 to P40 are output pins and output low-level signals. The following shows an example in which P40 is set to be an input pin with the BCLR instruction. Rev. 3.00 Mar 21, 2006 page 59 of 788 REJ09B0300-0300 Section 2 CPU Prior to executing BCLR: P47 Input/output Pin state DDR DR Input Low level 0 1 P46 Input High level 0 0 P45 Output Low level 1 0 P44 Output Low level 1 0 P43 Output Low level 1 0 P42 Output Low level 1 0 P41 Output Low level 1 0 P40 Output Low level 1 0 BCLR instruction executed: BCLR #0, @P4DDR The BCLR instruction is executed for DDR in port 4. After executing BCLR: P47 Input/output Pin state DDR DR Output Low level 1 1 P46 Output High level 1 0 P45 Output Low level 1 0 P44 Output Low level 1 0 P43 Output Low level 1 0 P42 Output Low level 1 0 P41 Output Low level 1 0 P40 Input High level 0 0 Operation: 1. When the BCLR instruction is executed, first the CPU reads P4DDR. Since P4DDR is a write-only register, so the CPU reads H'FF. In this example P4DDR has a value of H'3F, but the value read by the CPU is H'FF. 2. The CPU clears bit 0 of the read data to 0, changing data to H'FE. 3. The CPU writes H'FE to DDR, completing execution of BCLR. As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin. However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins. Rev. 3.00 Mar 21, 2006 page 60 of 788 REJ09B0300-0300 Section 2 CPU 2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. R5 R6 R5 + R4L R6 + R4L 2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). R5 R6 R5 + R4L Invalid H'FFFF R6 + R4L Rev. 3.00 Mar 21, 2006 page 61 of 788 REJ09B0300-0300 Section 2 CPU Rev. 3.00 Mar 21, 2006 page 62 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has three operating modes (modes 1 to 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode 0 1 2 3 1 MCU Operating Mode Selection CPU Operating Mode -- Normal Advanced Normal On-Chip ROM -- Disabled Enabled MD1 0 MD0 0 1 0 1 Description -- Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM enabled Single-chip mode Expanded mode with on-chip ROM enabled Single-chip mode Mode 1 is an expanded mode that allows access to external memory and peripheral devices. With modes 2 and 3, operation begins in single-chip mode after reset release, but a transition can be made to external expansion mode by setting the EXPE bit in MDCR to 1. Mode 0 cannot be used in this LSI. Thus, mode pins should be set to enable mode 1, 2 or 3 in normal program execution state. Mode pins should not be changed during operation. 3.2 Register Descriptions The following registers are related to the operating mode. For details on the bus control register (BCR), refer to section 6.3.1, Bus Control Register (BCR). * Mode control register (MDCR) * System control register (SYSCR) * Serial timer control register (STCR) Rev. 3.00 Mar 21, 2006 page 63 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit 7 Bit Name EXPE Initial Value --* R/W R/W* Description Extended Mode Enable Specifies extended mode. Fixed to 1 and cannot be modified in mode 1. Readable/writable and the initial value is 0 in mode 2 or 3. 0: Single-chip mode 1: Extended mode 6 to 2 1 0 -- All 0 R Reserved These bits are always read as 0. These bits cannot be modified. MDS1 MDS0 --* --* R R Mode Select 1 and 0 These bits indicate the input levels at mode pins (MD1 and MD0) (the current operating mode). Bits MDS1 and MDS0 correspond to MD1 and MD0, respectively. These bits are read-only bits and they cannot be written to. The mode pin (MD1 and MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. Note: * The initial values are determined by the settings of the MD1 and MD0 pins. Rev. 3.00 Mar 21, 2006 page 64 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space. Bit 7 Bit Name CS2E Initial Value 0 R/W R/W Description Chip Select 2 Enable Specifies the location of the control pin (CS2) of the host interface together with the FGA20E bit in HICR. See section 18, Host Interface X-Bus Interface (XBS), for details. 6 IOSE 0 R/W IOS Enable Enables or disables AS/IOS pin function in extended mode. 0: AS pin Outputs low when an external area is accessed. 1: IOS pin Outputs low when a specified address of addresses H'(FF)F000 to H'(FF)F7FF is accessed. 5 4 INTM1 INTM0 0 0 R R/W These bits select the control mode of the interrupt controller. For details on the interrupt control modes and interrupt control select modes 1 and 0, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Interrupt control mode 1 10: Setting prohibited 11: Setting prohibited 3 XRST 1 R External Reset This bit indicates the reset source. A reset is caused by an external reset input, or when the watchdog timer overflows. 0: A reset is caused when the watchdog timer overflows. 1: A reset is caused by an external reset. Rev. 3.00 Mar 21, 2006 page 65 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Bit 2 Bit Name NMIEG Initial Value 0 R/W R/W Description NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input 1 HIE 0 R/W Host Interface Enable Controls CPU access to the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2), the keyboard matrix interrupt and MOS input pull-up control registers (KMIMR, KMPCR, and KMIMRA), the 8-bit timer (TMR_X and TMR_Y) registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and TCORB_X), and the timer connection registers (TCONRI, TCONRO, TCONRS, and SEDGR). 0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X and TMR_Y) registers and timer connection registers is permitted 1: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to host interface registers and keyboard matrix interrupt and MOS input pull-up control registers is permitted 0 RAME 1 R/W RAM Enable Enables or disables on-chip RAM. The RAME bit is initialized when the reset state is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Rev. 3.00 Mar 21, 2006 page 66 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Bit 7 Bit Name IICS Initial Value 0 R/W R/W Description I C Extra Buffer Select Specifies bits 7 to 4 of port A as output buffers similar to SLC and SDA. These pins are used to implement 2 an I C interface only by software. 0: PA7 to PA4 are normal input/output pins. 1: PA7 to PA4 are input/output pins enabling bus driving. 6 5 IICX1 IICX0 0 0 R/W R/W I C Transfer Rate Select 1 and 0 These bits control the IIC operation. These bits select a transfer rate in master mode together with bits 2 CKS2 to CKS0 in the I C bus mode register (ICMR). For details on the transfer rate, refer to table 16.3. I C Master Enable Enables or disables CPU access for IIC registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, DADRBL/DACNTL), and SCI registers (SMR, BRR, SCMR). 0: SCI_1 registers are accessed in an area from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. SCI_2 registers are accessed in an area from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. SCI_0 registers are accessed in an area from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. 1: IIC_1 registers are accessed in an area from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. PWMX registers are accessed in an area from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. IIC_0 registers are accessed in an area from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. 2 2 2 4 IICE 0 R/W Rev. 3.00 Mar 21, 2006 page 67 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Bit 3 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2), control registers in power-down state (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of onchip peripheral modules (PCSR, SYSCR2). 0: Registers in power-down state and control registers of on-chip peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 1: Control registers of flash memory are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 2 1 0 -- ICKS1 ICKS0 0 0 0 R/(W) R/W R/W Reserved The initial value should not be changed. Internal Clock Source Select 1, 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, refer to section 12.3.4, Timer Control Register (TCR). Rev. 3.00 Mar 21, 2006 page 68 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1. When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset. Ports 1, 2 and A output an address by setting 1 to the corresponding port data direction register (DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port B functions as a data bus when the ABW bit in WSCR is cleared to 0. 3.3.3 Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. The CPU can access a 56-kbyte address space in mode 3. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1. When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. Ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction register (DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port B functions as a data bus when the ABW bit in WSCR is cleared to 0. Rev. 3.00 Mar 21, 2006 page 69 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes 3.3.4 Pin Functions in Each Operating Mode Pin functions of ports 1 to 3, 9, A, and B depend on the operating mode. Table 3.2 shows pin functions in each operating mode. Table 3.2 Port Port 1 Port 2 Port A Port 3 Port B Port 9 P97 P96 P95 to P93 P92, P91 P90 Port C to Port G Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: Immediately after reset Pin Functions in Each Mode Mode 1 A A P D P*/D P*/C C*/P C P P*/C P Mode 2 P*/A P*/A P*/A P*/D P*/D P*/C P*/C P*/C P P*/C P Mode 3 P*/A P*/A P P*/D P*/D P*/C P*/C P*/C P P*/C P Rev. 3.00 Mar 21, 2006 page 70 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes 3.4 Address Map in Each Operating Mode Figures 3.1 to 3.10 show the address map in each operating mode. Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 H'000000 Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled H'000000 Mode 2 (EXPE = 0) Advanced mode Single-chip mode On-chip ROM On-chip ROM External address space H'00FFFF H'00FFFF Reserved area Reserved area H'01FFFF H'020000 H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF H'FFE080 H'01FFFF External address space H'FFE080 On-chip RAM* H'FFEFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 On-chip RAM External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.1 Address Map for H8S/2140B and H8S/2160B (1) Rev. 3.00 Mar 21, 2006 page 71 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'DFFF H'E080 On-chip RAM H'EFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.2 Address Map for H8S/2140B and H8S/2160B (2) Rev. 3.00 Mar 21, 2006 page 72 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 H'000000 Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled H'000000 Mode 2 (EXPE = 0) Advanced mode Single-chip mode External address space On-chip ROM On-chip ROM H'01FFFF H'020000 H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF H'FFE080 H'01FFFF External address space H'FFE080 On-chip RAM H'FFEFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 On-chip RAM* External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.3 Address Map for H8S/2141B and H8S/2161B (1) Rev. 3.00 Mar 21, 2006 page 73 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'DFFF H'E080 On-chip RAM H'EFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.4 Address Map for H8S/2141B and H8S/2161B (2) Rev. 3.00 Mar 21, 2006 page 74 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 H'000000 Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled H'000000 Mode 2 (EXPE = 0) Advanced mode Single-chip mode External address space On-chip ROM On-chip ROM H'03FFFF H'040000 H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF H'FFD080 H'03FFFF External address space H'FFD080 On-chip RAM* H'FFEFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 On-chip RAM External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.5 Address Map for H8S/2145BV (1) Rev. 3.00 Mar 21, 2006 page 75 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'DFFF H'E080 On-chip RAM H'EFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.6 Address Map for H8S/2145BV (2) Rev. 3.00 Mar 21, 2006 page 76 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 H'000000 Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled H'000000 Mode 2 (EXPE = 0) Advanced mode Single-chip mode External address space On-chip ROM On-chip ROM H'03FFFF H'040000 H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF H'FFD080 H'03FFFF External address space H'FFD080 On-chip RAM* H'FFEFFF External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 On-chip RAM External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.7 Address Map for H8S/2145B (1) Rev. 3.00 Mar 21, 2006 page 77 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'DFFF H'E080 On-chip RAM H'EFFF External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.8 Address Map for H8S/2145B (2) Rev. 3.00 Mar 21, 2006 page 78 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 H'000000 Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled H'000000 Mode 2 (EXPE = 0) Advanced mode Single-chip mode External address space On-chip ROM On-chip ROM H'01FFFF H'020000 H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF H'FFE080 H'01FFFF External address space H'FFE080 On-chip RAM* H'FFEFFF External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 On-chip RAM External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.9 Address Map for H8S/2148B (1) Rev. 3.00 Mar 21, 2006 page 79 of 788 REJ09B0300-0300 Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'DFFF H'E080 On-chip RAM H'EFFF External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.10 Address Map for H8S/2148B (2) Rev. 3.00 Mar 21, 2006 page 80 of 788 REJ09B0300-0300 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Interrupt Start of Exception Handling Starts immediately after a low-to-high transition of the RES pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Starts when a direction transition occurs as the result of SLEEP instruction execution. Started by execution of a trap (TRAPA) instruction. Trap instruction exception handling requests are accepted at all times in program execution state. Direct transition Trap instruction Low Rev. 3.00 Mar 21, 2006 page 81 of 788 REJ09B0300-0300 Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Vector Address Exception Source Reset Reserved for system use Vector Number 0 1 5 6 7 9 10 11 Reserved for system use 12 15 16 17 18 19 20 21 22 23 24 107 Normal Mode H'0000 to H'0001 H'0002 to H'0003 | H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 | H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00DE to H'00DF Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F H'000060 to H'000063 H'0001BC to H'0001BF Direct transition External interrupt (NMI) Trap instruction (four sources) 8 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table. Rev. 3.00 Mar 21, 2006 page 82 of 788 REJ09B0300-0300 Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog Timer (WDT). 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit is set to 1 in CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence. Rev. 3.00 Mar 21, 2006 page 83 of 788 REJ09B0300-0300 Section 4 Exception Handling Vector fetch Internal Prefetch of first program processing instruction RES Internal address bus (1) (3) Internal read signal Internal write signal High Internal data bus (2) (4) (1) (2) (3) (4) Reset exception handling vector address ((1) = H'0000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First program instruction Figure 4.1 Reset Sequence (Mode 3) 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled After a reset is cancelled, the module stop control registers (MSTPCR) are initialized, and all modules except the DTC operate in module stop mode. Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read from and write to these registers, clear module stop mode. Rev. 3.00 Mar 21, 2006 page 84 of 788 REJ09B0300-0300 Section 4 Exception Handling 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address. 4.5 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR after execution of trap instruction exception handling. Table 4.3 Status of CCR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 1 Legend: 1: Set to 1 --: Retains value prior to execution I 1 1 UI -- 1 Rev. 3.00 Mar 21, 2006 page 85 of 788 REJ09B0300-0300 Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode Advanced mode SP CCR CCR* PC (16 bits) SP CCR PC (24 bits) Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev. 3.00 Mar 21, 2006 page 86 of 788 REJ09B0300-0300 Section 4 Exception Handling 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what happens when the SP value is odd. Address CCR SP PC SP R1L H'FFEFFA H'FFEFFB PC H'FFEFFC H'FFEFFD SP H'FFEFFF TRAPA instruction executed SP set to H'FFEFFF Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer MOV.B R1L, @-ER7 executed Contents of CCR lost Data saved above SP Note: This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode. Figure 4.3 Operation when SP Value Is Odd Rev. 3.00 Mar 21, 2006 page 87 of 788 REJ09B0300-0300 Section 4 Exception Handling Rev. 3.00 Mar 21, 2006 page 88 of 788 REJ09B0300-0300 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI and address break. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Thirty-one external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing, can be selected for IRQ7 to IRQ0. The IRQ6 interrupt is shared by the interrupt from the IRQ6 pin and eight external interrupt inputs (KIN7 to KIN0), and the IRQ7 interrupt is shared by the interrupt from the IRQ7 pin and sixteen external interrupt inputs (KIN15 to KIN8 and WUE7 to WUE0). KIN15 to KIN0 and WUE7 to WUE0 can be masked individually by the user program. * DTC control The DTC can be activated by an interrupt request. Rev. 3.00 Mar 21, 2006 page 89 of 788 REJ09B0300-0300 Section 5 Interrupt Controller INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input IRQ input ISR ISCR KMIMR KIN input WUE input Internal interrupt request SWDTEND to IBF13 ICR Interrupt controller Legend: ICR ISCR IER ISR KMIMR WUEMR SYSCR IER WUEMR CPU Interrupt request Vector number Priority check KIN and WUE input I, UI CCR : Interrupt control register : IRQ sense control register : IRQ enable register : IRQ status register : Keyboard matrix interrupt mask register : Wake-up event interrupt mask register : System control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 3.00 Mar 21, 2006 page 90 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Symbol NMI IRQ7 to IRQ0 Pin Configuration I/O Input Input Function Nonmaskable external interrupt Rising edge or falling edge can be selected Maskable external interrupts Rising edge, falling edge, or both edges, or level sensing, can be selected individually for each pin. KIN15 to KIN0 WUE7 to WUE0* Note: * Input Input Maskable external interrupts Falling edge or level sensing can be selected. Maskable external interrupts Falling edge or level sensing can be selected. Not supported by the H8S/2148B and H8S/2145B (5-V version). 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). * Interrupt control registers A to C (ICRA to ICRC) * Address break control register (ABRKCR) * Break address registers A to C (BARA to BARC) * IRQ sense control registers (ISCRH, ISCRL) * IRQ enable register (IER) * IRQ status register (ISR) * Keyboard matrix interrupt mask registers (KMIMRA, KMIMR) * Wake-up event interrupt mask register (WUEMRB) Rev. 3.00 Mar 21, 2006 page 91 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC) The ICR registers set interrupt control levels for interrupts other than NMI and address breaks. The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2. Bit 7 to 0 Bit Name ICRn7 to IRCn0 Initial Value All 0 R/W R/W Description Interrupt Control Level 0: Corresponding interrupt source is interrupt control level 0 (no priority) 1: Corresponding interrupt source is interrupt control level 1 (priority) n: A to C Table 5.2 Correspondence between Interrupt Source and ICR Register Bit 7 6 5 4 3 2 1 0 Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0 ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 DTC WDT_0 WDT_1 ICRB A/D converter FRT -- -- TMR_0 TMR_1 TMR_X, TMR_Y XBS, Keyboard buffer controller ICRC SCI_0 SCI_1 SCI_2 IIC_0 IIC_1 -- LPC* -- Legend: : Reserved. The write value should always be 0. Notes: n: A to C * On products not including LPC, this bit is reserved. The write value should always be 0. Rev. 3.00 Mar 21, 2006 page 92 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an address break is requested. Bit 7 Bit Name CMF Initial Value 0 R/W R Description Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE flag is set to 1. [Clearing condition] When an exception handling is executed for an address break interrupt. 6 to 1 0 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. BIE 0 R/W Break Interrupt Enable Enables or disables address break. 0: Disabled 1: Enabled Rev. 3.00 Mar 21, 2006 page 93 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. * BARA Bit 7 to 0 Bit Name A23 to A16 Initial Value All 0 R/W R/W Description Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus. * BARB Bit 7 to 0 Bit Name A15 to A8 Initial Value All 0 R/W R/W Description Addresses 15 to 8 The A15 to A8 bits are compared with A15 to A8 in the internal address bus. * BARC Bit 7 to 1 0 Bit Name A7 to A1 -- Initial Value All 0 R/W R/W Description Addresses 7 to 1 The A7 to A1 bits are compared with A7 to A1 in the internal address bus. 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 94 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0. * ISCRH Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 7 to 4) * ISCRL Bit 7 6 5 4 3 2 1 0 Bit Name IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 3 to 0) Rev. 3.00 Mar 21, 2006 page 95 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.3.5 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable (n = 7 to 0) The IRQn interrupt request is enabled when this bit is 1. 5.3.6 IRQ Status Register (ISR) The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests. Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W R/(W)*2 R/(W)*2 R/(W)* 2 Description [Setting condition] When the interrupt source selected by the ISCR registers occurs [Clearing conditions] * * When reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set 1 and IRQn input is high (n = 7 to 0)* When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or 1 both-edge detection is set* R/(W)*2 R/(W)*2 R/(W)* 2 R/(W)*2 R/(W)*2 * Notes: 1. When a product, in which a DTC is incorporated, is used, the corresponding flag bit is not automatically cleared even when exception handing is executed. For details, refer to section 5.8.4, Setting on a Product Incorporating DTC. 2. Only 0 can be written, for flag clearing. Rev. 3.00 Mar 21, 2006 page 96 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0), and wake-up event interrupt inputs (WUE7 to WUE0). * KMIMRA Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask 15 to 8 These bits enable or disable a key-sensing input interrupt request (KIN15 to KIN8). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request * KMIMR Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial Value 1 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask 7 to 0 These bits enable or disable a key-sensing input interrupt request (KIN7 to KIN0). KMIMR6 also performs interrupt request mask control for pin IRQ6. 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request Rev. 3.00 Mar 21, 2006 page 97 of 788 REJ09B0300-0300 Section 5 Interrupt Controller * WUEMRB* Bit 7 6 5 4 3 2 1 0 Note: Bit Name WUEMR7 WUEMR6 WUEMR5 WUEMR4 WUEMR3 WUEMR2 WUEMR1 WUEMR0 * Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Wake-Up Event Interrupt Mask 7 to 0 These bits enable or disable a wake-up event input interrupt request (WUE7 to WUE0). 0: Enables a wake-up event input interrupt request 1: Disables a wake-up event input interrupt request Not supported by the H8S/2148B and H8S/2145B (5-V version). Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0, interrupts WUE7 to WUE0, and registers KMIMRA, KMIMR, and WUEMRB. Rev. 3.00 Mar 21, 2006 page 98 of 788 REJ09B0300-0300 Section 5 Interrupt Controller KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 IRQ6 internal signal Edge level selection enable/disable circuit IRQ6 interrupt IRQ6E IRQ6SC KMIMR8 (initial value 1) PA0/KIN8 KMIMR9 (initial value 1) PA1/KIN9 WUEMR7 (initial value 1) PB7/WUE7 IRQ7 internal signal Edge level selection enable/disable circuit IRQ7 interrupt IRQ7E IRQ7SC Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB If any of bits KMIMR15 to KMIMR8 or WUEMRB7 to WUEMRB0 is cleared to 0, interrupt input from the IRQ7 pin will be ignored. When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt input pins or wakeup event interrupt input pins, either lowlevel sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7). Rev. 3.00 Mar 21, 2006 page 99 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: * The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an independent vector address. * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * Interrupt control levels can be specified by the ICR settings. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 to use the pin as an I/O pin for another function. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3. Rev. 3.00 Mar 21, 2006 page 100 of 788 REJ09B0300-0300 Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Note: n = 7 to 0 Clear signal S R Q IRQn interrupt request Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0. When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the IRQ7 pin will be ignored. Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied, regardless of the IER setting, refer to a needed flag only. KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts: Interrupts KIN15 to KIN0 and WUE7 to WUE0 are requested by an input signal at pins KIN15 to KIN0 and WUE7 to WUE0. When pins KIN15 to KIN0 and WUE7 to WUE0 are used for key-sense input or wakeup event, clear the corresponding KMIMR and WUEMR bits to 0 in order to enable their key-sense input and wakeup event interrupts. Remaining unused KMIMR and WUEMR bits for key-sense input should be set to 1 in order to disable interrupts. Interrupts WUE7 to WUE0 and KIN15 to KIN8 generate IRQ7 interrupts, and interrupts KIN7 to KIN0 generate IRQ6 interrupts. The pin conditions for interrupt request generation, enable of interrupt requests, settings of interrupt control levels, and status display of interrupt requests depend on each setting and display of the IRQ7 or IRQ6 interrupt. When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt input pins or wakeup event interrupt input pins, either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7). Rev. 3.00 Mar 21, 2006 page 101 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.4.2 Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: 1. For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. 2. The control level for each interrupt can be set by ICR. 3. The DTC can be activated by an interrupt request from an on-chip peripheral module. 4. An interrupt request that activates the DTC is not affected by the interrupt control mode or the status of the CPU interrupt mask bits. 5.5 Interrupt Exception Handling Vector Table Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and UI bits in CCR are given priority and processed before interrupt requests from modules that are set to control level 0 (no priority). Rev. 3.00 Mar 21, 2006 page 102 of 788 REJ09B0300-0300 Section 5 Interrupt Controller Table 5.3 Origin of Interrupt Source External pin Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8, WUE7 to WUE0 Vector Normal Number Mode 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 to 47 48 49 50 51 52 53 54 55 56 to 63 64 65 66 67 H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A to H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 to H'007E H'0080 H'0082 H'0084 H'0086 Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 to H'0000BC H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC H'0000E0 to H'0000FC H'000100 H'000104 H'000108 H'00010C ICR -- ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 Priority High DTC WDT_0 WDT_1 -- A/D converter -- SWDTEND (Software activation data transfer end) WOVI0 (Interval timer) WOVI1 (Interval timer) Address break ADI (A/D conversion end) Reserved for system use ICRA2 ICRA1 ICRA0 -- ICRB7 -- FRT ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) Reserved for system use Reserved for system use ICRB6 -- -- TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match A) OVI0 (Overflow) Reserved for system use ICRB3 Low Rev. 3.00 Mar 21, 2006 page 103 of 788 REJ09B0300-0300 Section 5 Interrupt Controller Origin of Interrupt Source TMR_1 Vector Address Name CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture X) IBF1 (IDR1 reception completion) IBF2 (IDR2 reception completion) IBF3 (IDR3 reception completion) IBF4 (IDR4 reception completion) ERI0 (Reception error 0) RXI0 (Reception completion 0) TXI0 (Transmission data empty 0) TEI0 (Transmission end 0) ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1) ERI2 (Reception error 2) RXI2 (Reception completion 2) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IICI0 (1-byte transmission/ reception completion) DDCSWI (Format switch) IICI1 (1-byte transmission/ reception completion) Reserved for system use KBIA (Reception completion A) KBIB (Reception completion B) KBIC (Reception completion C) Reserved for system use Reserved for system use Vector Normal Number Mode 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 to 107 108 109 110 111 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B2 H'00B4 H'00B6 H'00B8 H'00BA H'00BC H'00BE H'00C0 H'00C2 H'00C4 H'00C6 H'00C8 to H'00D6 H'00D8 H'00DA H'00DC H'00DE Advanced Mode H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 H'000134 H'000138 H'00013C H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C H'000160 H'000164 H'000168 H'00016C H'000170 H'000174 H'000178 H'00017C H'000180 H'000184 H'000188 H'00018C H'000190 to H'0001AC H'0001B0 H'0001B4 H'0001B8 H'0001BC ICRB0 ICRC3 ICR ICRB2 Priority High TMR_X, TMR_Y ICRB1 XBS ICRB0 SCI_0 ICRC7 SCI_1 ICRC6 SCI_2 ICRC5 IIC_0 ICRC4 IIC_1 Keyboard buffer controller -- -- LPC* ERRI (Transfer error) IBF1 (IDR1 reception completion) IBF2 (IDR2 reception completion) IBF3 (IDR3 reception completion) ICRC1 Low Note: * Reserved for system use on products not including LPC. Rev. 3.00 Mar 21, 2006 page 104 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.4 Interrupt Control Modes Priority Setting Registers ICR Interrupt Mask Bits I Interrupt SYSCR Control Mode INTM1 INTM0 0 0 0 Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I and UI bits. Priority levels can be set with ICR. 1 1 ICR I, UI 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests other than NMI and address breaks are masked by ICR and the I bit of the CCR in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. If the I bit in CCR is set to 1, only NMI and address break interrupts are accepted by the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0, any interrupt request is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. Rev. 3.00 Mar 21, 2006 page 105 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program excution state Interrupt generated? Yes Yes No NMI No An interrupt with interrupt control level 1? No Hold pending Yes No IRQ0 Yes No IRQ1 Yes IRQ0 Yes IRQ1 IBFI3 Yes Yes IBFI3 Yes No No I=0 Yes No Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.00 Mar 21, 2006 page 106 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. * An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending * An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending. For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and ICRA to ICRC are set to H'20, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are set to control level 1, and other interrupts are set to control level 0) is shown below. Figure 5.5 shows a state transition diagram. * All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...) * Only NMI, IRQ2, IRQ3 and address break interrupt requests are accepted when I = 1 and UI = 0. * Only an NMI and address break interrupt request is accepted when I = 1 and UI = 1. I All interrupt requests are accepted I 0 0 1, UI Only NMI, address break, IRQ2, and IRQ3 interrupt requests are accepted UI 0 Exception handling execution or UI 1 I Exception handling execution or I 1, UI 1 0 Only NMI and address break interrupt requests are accepted Figure 5.5 State Transition in Interrupt Control Mode 1 Rev. 3.00 Mar 21, 2006 page 107 of 788 REJ09B0300-0300 Section 5 Interrupt Controller Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or when the I bit is set to 1 while the UI bit is cleared to 0. An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0. When the I bit is set to 1, only an NMI or address break interrupt request is accepted, and other interrupts are held pending. When both the I and UI bits are set to 1, only an NMI or address break interrupt request is accepted, and other interrupts are held pending. When the I bit is cleared to 0, the UI bit is not affected. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The I and UI bits in CCR are set to 1. This masks all interrupts except for an NMI or address break interrupt. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 3.00 Mar 21, 2006 page 108 of 788 REJ09B0300-0300 Section 5 Interrupt Controller Program excution state No Interrupt generated? Yes Yes NMI No An interrupt with interrupt control level 1? No Hold pending Yes No No IRQ1 Yes IFBFI3 Yes No IRQ0 Yes IRQ1 Yes IFBFI3 Yes No IRQ0 Yes I=0 Yes No I=0 No Yes No UI = 0 Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 3.00 Mar 21, 2006 page 109 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 3.00 Mar 21, 2006 page 110 of 788 REJ09B0300-0300 Interrupt is accepted Interrupt level decision and wait for end of instruction Instruction prefetch Stack access Vector fetch Internal processing Internal processing Prefetch of instruction in interrupt-handling routine Interrupt request signal Internal address bus (1) (3) (5) (7) (9) (11) (13) Internal read signal Internal write signal Figure 5.7 Interrupt Exception Handling (2) (4) (6) (8) Internal data bus (10) (12) (14) (1) Rev. 3.00 Mar 21, 2006 page 111 of 788 REJ09B0300-0300 (6) (8) (9) (11) (10) (12) (13) (14) Section 5 Interrupt Controller (2) (4) (3) (5) (7) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) Instruction code (not executed) Instruction prefetch address (Instruction is not executed.) SP - 2 SP - 4 Saved PC and CCR Vector address Starting address of interrupt-handling routine (contents of vector address) Starting address of interrupt-handling routine ((13) = (10) (12)) First instruction in interrupt-handling routine Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.5 shows interrupt response times - the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.5 are explained in table 5.6. Table 5.5 Interrupt Response Times Normal Mode 1 No. Execution Status 1 2 3 4 5 6 Interrupt priority determination* Advanced Mode 3 1 to (19 + 2*SI) 2*SK 2*SI 2*SI 2 12 to 32 3 1 to (19 + 2*SI) 2*SK SI 2*SI Number of wait states until executing 2 instruction ends* PC, CCR stack save Vector fetch 3 Instruction fetch* Internal processing* 4 2 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and prefetch of interrupt handling routine. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5.6 Number of States in Interrupt Handling Routine Execution Status Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 2 3-State Access 3+m Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6 + 2m Legend: m: Number of wait states in external device access Rev. 3.00 Mar 21, 2006 page 112 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Selection of a number of the above For details on interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). Figure 5.8 shows a block diagram of the DTC and interrupt controller. Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, UI Figure 5.8 DTC and Interrupt Controller Selection of Interrupt Source: Interrupt factors are selected as DTC activation source or CPU interrupt source by the DTCE bit of DTCERA to DTCERE of DTC. By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after DTC data transfer, and request a CPU interrupt. If DTC carries out the designate number of data transfers and the transfer counter reads 0, after DTC data transfer, the DTCE bit is also cleared to 0, and an interrupt is requested to the CPU. Rev. 3.00 Mar 21, 2006 page 113 of 788 REJ09B0300-0300 Section 5 Interrupt Controller Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See table 7.1 for the respective priority. Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.7 shows the interrupt factor clear control and selection of interrupt factors by specification of the DTCE bit of DTC's DTCER, and the DISEL bit of DTC's MRB. Table 5.7 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 Interrupt Sources Selection/Clearing Control DTC x O o CPU O x O Legend: O: The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) o: The relevant interrupt is used. The interrupt source is not cleared. x: The relevant interrupt cannot be used. *: Don't care Note: The SCI, IIC, LPC, or A/D converter interrupt source is cleared when the DTC reads or writes to the prescribed register, and is not dependent upon the DISEL bit. Rev. 3.00 Mar 21, 2006 page 114 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.7 5.7.1 Address Break Features This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address break interrupt exception handling is performed. With this function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. 5.7.2 Block Diagram Figure 5.9 shows a block diagram of the address break. BAR ABRKCR Comparator Match signal Control logic Address break interrupt request Internal address Prefetch signal (internal signal) Figure 5.9 Address Break Block Diagram Rev. 3.00 Mar 21, 2006 page 115 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.7.3 Operation If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address break interrupt can be generated. This address break function generates an interrupt request to the interrupt controller at prefetch, and determines the priority by the interrupt controller. When an interrupt is accepted, an interrupt exception handling is activated after the current instruction has been completed. Note that the interrupt mask control according to the I and UI bits in CCR of the CPU is invalid to an address break interrupt. To use the address break function, set each register as follows: 1. Set a break address in the A23 to A1 bits in BAR. 2. Set the BIE bit in ABRKCR to 1 to enable the address break. When the BIE bit is cleared to 0, an address break is not requested. When the setting conditions are satisfied, the CMF flag in ABRKCR is set to 1 to request an interrupt. The interrupt source should be determined by the interrupt handling routine if necessary. 5.7.4 Usage Notes 1. In an address break, the break address should be an address where the first byte of the instruction exists. Otherwise, a break condition will not be satisfied. 2. In normal mode, addresses A23 to A16 are not compared. 3. When the branch instructions (Bcc, BSR), jump instructions (JMP, JSR), RST instruction, and RTE instruction are placed immediately prior to the address specified by BAR, a prefetch signal to the address may be output to request an address break by executing these instruction. It is necessary to take countermeasures: do not set a break address to an address immediately after these instructions, or determine whether interrupt handling is performed by satisfaction of a normal condition. 4. An address break interrupt is generated by combining the internal prefetch signal and an address. Therefore, the timing to enter the interrupt exception handling differs according to the instructions at the specified and at prior addresses and execution cycles. Figure 5.10 shows an example of address timing. Rev. 3.00 Mar 21, 2006 page 116 of 788 REJ09B0300-0300 Section 5 Interrupt Controller (1) When a break address specified instruction is executed for one state in the program area and on-chip memory Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Save to stack Vector fetch Instruction Internal fetch operation Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP NOP execution execution NOP execution Interrupt exception handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Break point NOP instruction is executed at break point address H'0312 and following address H'0314. Fetching is performed from address H'0316 after exception handling ends. (2) When a break address specified instruction is executed for two states in the program area and on-chip memory Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Save to stack Vector fetch Internal operation Instruction fetch Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP execution MOV.W execution Interrupt exception handling Break request signal H'0310 H'0312 H'0316 H'0318 NOP MOV.W #xx:16,Rd NOP NOP Break point MOV instruction is executed at break point address H'0312, and NOP instruction is not executed at the following address H'0314. Fetching is performed from address H'0316 after exception handling ends. (3) When a break address specified instruction is executed for one state in the program area and external memory (2-state access, 16-bit bus access) Instruction fetch Address bus H'0310 H'0312 H'0314 SP-2 SP-4 H'0036 Instruction fetch Instruction fetch Internal operation Save to stack Vector fetch Instruction fetch NOP execution Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Break point Interrupt exception handling NOP instruction is not executed at break point address H'0312. Fetching is performed from address H'0312 after exception handling ends. Figure 5.10 Address Break Timing Example Rev. 3.00 Mar 21, 2006 page 117 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.8 5.8.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.11 shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TCR write cycle by CPU CMIA exception handling Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.11 Conflict between Interrupt Generation and Disabling Rev. 3.00 Mar 21, 2006 page 118 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.8.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.8.4 Setting on Product Incorporating DTC When a product, in which a DTC is incorporated, is used in the following settings, the corresponding flag bit is not automatically cleared even when exception handing, which is a clear condition, is executed and the bit is held at 1. 1. When DTCEA3 is set to 1(ADI is set to an interrupt source), IRQ4F flag is not automatically cleared. 2. When DTCEA2 is set to 1(ICIA is set to an interrupt source), IRQ5F flag is not automatically cleared. 3. When DTCEA1 is set to 1(ICIB is set to an interrupt source), IRQ6F flag is not automatically cleared. 4. When DTCEA0 is set to 1(OCIA is set to an interrupt source), IRQ7F flag is not automatically cleared. When activation interrupt sources of DTC and IRQ interrupts are used with the above combinations, clear the interrupt flag by software in the interrupt handling routine of the corresponding IRQ. Rev. 3.00 Mar 21, 2006 page 119 of 788 REJ09B0300-0300 Section 5 Interrupt Controller 5.8.5 IRQ Status Register (ISR) According to the pin status after a reset, IRQnF may be set to 1, so ISR should be read after a reset to write 0. (n = 7 to 0) Rev. 3.00 Mar 21, 2006 page 120 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the operation of the internal bus masters - CPU, and data transfer controller (DTC). 6.1 Features * Basic bus interface 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface A burst ROM interface can be set for basic expansion areas 1-state access or 2-state access can be selected for burst access * Idle cycle insertion An idle cycle can be inserted for external write cycles immediately after external read cycles * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC BSCS20AA_000020020700 Rev. 3.00 Mar 21, 2006 page 121 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) External bus control signals Bus controller Internal control signals Bus mode signal BCR WAIT Wait controller CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller Rev. 3.00 Mar 21, 2006 page 122 of 788 REJ09B0300-0300 Internal data bus WSCR Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Symbol AS IOS RD HWR Pin Configuration I/O Output Output Output Output Function Strobe signal indicating that address output on the address bus is enabled (when the IOSE bit in SYSCR is cleared to 0). I/O select signal (when the IOSE bit in SYSCR is set to 1). Strobe signal indicating that the external address space is being read. Strobe signal indicating that the external address space is being written to, and the upper half (D15 to D8) of the data bus is enabled. Strobe signal indicating that the external address space is being written to, and the lower half (D7 to D0) of the data bus is enabled. Wait request signal when accessing the external 3-state access space. LWR Output WAIT Input 6.3 Register Descriptions The bus controller has the following registers. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). * Bus control register (BCR) * Wait state control register (WSCR) Rev. 3.00 Mar 21, 2006 page 123 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 6.3.1 Bus Control Register (BCR) BCR is used to specify the access mode for the external address space or the I/O area range when the AS/IOS pin is specified as an I/O strobe pin. Bit 7 6 Bit Name -- ICIS0 Initial Value 1 1 R/W R/W R/W Description Reserved This bit should not be written by 0. Idle Cycle Insertion Selects whether or not to insert 1-state of the idle cycle between bus cycles when the external write cycle follows the external read cycle. 0: Idle cycle not inserted when the external write cycle follows the external read cycle 1: 1-state idle cycle inserted when the external write cycle follows the external read cycle 5 BRSTRM 0 R/W Burst ROM Enable Selects the bus interface for the external address space. 0: Basic bus interface 1: Burst ROM interface 4 BRSTS1 1 R/W Burst Cycle Select 1 Selects the number of states in the burst cycle of the burst ROM interface. 0: 1 state 1: 2 states 3 BRSTS0 0 R/W Burst Cycle Select 0 Selects the number of words that can be accessed by burst access via the burst ROM interface. 0: Max, 4 words 1: Max, 8 words 2 1 0 IOS1 IOS0 0 1 1 R/W R/W R/W Reserved This bit should not be written by 0. IOS Select 1, 0 Select the address range where the IOS signal is output. For details, refer to table 6.3. Rev. 3.00 Mar 21, 2006 page 124 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 6.3.2 Wait State Control Register (WSCR) WSCR is used to specify the data bus width for external address space access, the number of access states, the wait mode, and the number of wait states for access to external address spaces. The bus width and the number of access states for internal memory and internal I/O registers are fixed regardless of the WSCR settings. Bit 7, 6 5 Bit Name -- ABW Initial Value All 0 1 R/W R/W R/W Description Reserved These bits should not be written by 1. Bus Width Control Selects 8 or 16 bits for access to the external address space. 0: 16-bit access space 1: 8-bit access space 4 AST 1 R/W Access State Control Selects 2 or 3 access states for access to the external address space. This bit also enables or disables waitstate insertion. 0: 2-state access space. Wait state insertion disabled in external address space access 1: 3-state access space. Wait state insertion enabled in external address space access 3 2 WMS1 WMS0 0 0 R/W R/W Wait Mode Select 1, 0 Select the wait mode for access to the external address space when the AST bit is set to 1. 00: Program wait mode 01: Wait disabled mode 10: Pin wait mode 11: Pin auto-wait mode Rev. 3.00 Mar 21, 2006 page 125 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Bit 1 0 Bit Name WC1 WC0 Initial Value 1 1 R/W R/W R/W Description Wait Count 1, 0 Select the number of program wait states to be inserted when the external address space is accessed while the AST bit is set to 1. 00: Program wait state is not inserted 01: 1 program wait state is inserted 10: 2 program wait states are inserted 11: 3 program wait states are inserted 6.4 6.4.1 Bus Control Bus Specifications The external address space bus specifications consist of three elements: Bus width, the number of access states, and the wait mode and the number of program wait states. The bus width and the number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller settings. Bus Width: A bus width of 8 or 16 bits can be selected via the ABW bit in WSCR. Number of Access States: Two or three access states can be selected via the AST bit in WSCR. When the 2-state access space is designated, wait-state insertion is disabled. In the burst ROM interface, the number of access states is determined regardless of the AST bit setting. Wait Mode and Number of Program Wait States: When a 3-state access space is designated by the AST bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in WSCR. From 0 to 3 program wait states can be selected. Rev. 3.00 Mar 21, 2006 page 126 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Table 6.2 shows the bus specifications for the basic bus interface of each area. Table 6.2 Bus Specifications for Basic Bus Interface Bus Specifications Number of Access States 2 3 3 Number of Program Wait States 0 0 0 1 2 3 8 8 2 3 3 0 0 0 1 2 3 ABW 0 AST 0 1 WMS1 -- 0 --* WMS0 -- 1 --* WC1 -- -- 0 WC0 -- -- 0 1 Bus Width 16 16 1 0 1 1 0 1 -- 0 --* -- 1 --* -- -- 0 -- -- 0 1 1 Note: * 0 1 Other than WMS1 = 0 and WMS0 = 1 6.4.2 Advanced Mode The external address space is initialized as the basic bus interface and a 3-state access space. In on-chip ROM enable extended mode, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The onchip RAM and its reserved area are enabled when the RAME bit in SYSCR is set to 1. The onchip RAM and its reserved area are disabled and corresponding addresses are the external address space when the RAME bit is cleared to 0. 6.4.3 Normal Mode The external address space is initialized as the basic bus interface and a 3-state access space. In on-chip ROM disable extended mode, the address space other than on-chip RAM and internal I/O registers is specified as the external address space. In on-chip ROM enable extended mode, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The on-chip RAM area is enabled when the Rev. 3.00 Mar 21, 2006 page 127 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the RAME bit is cleared to 0. 6.4.4 I/O Select Signals The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding external address space is accessed. Figure 6.2 shows an example of IOS signal output timing. Bus cycle T1 T2 T3 Address bus External addresses selected by IOS IOS Figure 6.2 IOS Signal Output Timing Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In extended mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE bit to 1. For details, refer to section 8, I/O Ports. The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR, as shown in table 6.3. Table 6.3 IOS1 0 Address Range for IOS Signal Output IOS0 0 1 IOS Signal Output Range H'(FF)F000 to H'(FF)F03F H'(FF)F000 to H'(FF)F0FF H'(FF)F000 to H'(FF)F3FF H'(FF)F000 to H'(FF)F7FF (Initial value) 1 0 1 Rev. 3.00 Mar 21, 2006 page 128 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 6.5 Basic Bus Interface The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications when using the basic bus interface, see table 6.2 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has a data alignment function, and controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used when the external address space is accessed, according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Rev. 3.00 Mar 21, 2006 page 129 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table 6.4 shows the data buses used and valid strobes for each access space. In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4 Area 8-bit access space 16-bit access space Data Buses Used and Valid Strobes Access Size Byte Read/ Write Read Write Byte Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD HWR, LWR Valid Strobe RD HWR RD Valid Invalid Valid Undefined Valid Valid Upper Data Bus Lower Data (D15 to D8) Bus (D7 to D0) Valid Ports or others Ports or others Invalid Valid Undefined Valid Valid Valid Note: Undefined: Undefined data is output. Invalid: Input state with the input value ignored. Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used as the data bus. Rev. 3.00 Mar 21, 2006 page 130 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 6.5.3 Basic Operation Timing 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space Rev. 3.00 Mar 21, 2006 page 131 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space Rev. 3.00 Mar 21, 2006 page 132 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted. Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High level Valid D7 to D0 Undefined Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) Rev. 3.00 Mar 21, 2006 page 133 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High level LWR Write D15 to D8 Undefined D7 to D0 Valid Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) Rev. 3.00 Mar 21, 2006 page 134 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 3.00 Mar 21, 2006 page 135 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR High level LWR Write D15 to D8 Valid D7 to D0 Undefined Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) Rev. 3.00 Mar 21, 2006 page 136 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High level LWR Write D15 to D8 Undefined D7 to D0 Valid Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) Rev. 3.00 Mar 21, 2006 page 137 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 3.00 Mar 21, 2006 page 138 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: Program wait insertion, pin wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin. Program Wait Mode: A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space always according to the settings of the WC1 and WC0 bits in WSCR. Pin Wait Mode: A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space always according to the settings of the WC1 and WC0 bits. If the WAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. This is useful when inserting four or more TW states, or when changing the number of TW states to be inserted for each external device. Pin Auto-Wait Mode: A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space according to the settings of the WC1 and WC0 bits if the WAIT pin is low at the falling edge of in the last T2 state. Even if the WAIT pin is held low, TW states can be inserted only up to the specified number of states. This function enables the low-speed memory interface only by inputting the chip select signal to the WAIT pin. Figure 6.13 shows an example of wait state insertion timing in pin wait mode. The settings after a reset are: 3-state access, 3 program wait insertion, and WAIT pin input disabled. Rev. 3.00 Mar 21, 2006 page 139 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) By program wait T1 T2 TW By WAIT pin TW TW T3 WAIT Address bus AS/IOS (IOSE = 0) RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: shown in clock indicates the WAIT pin sampling timing. Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode) Rev. 3.00 Mar 21, 2006 page 140 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 6.6 Burst ROM Interface In this LSI, the external address space can be designated as the burst ROM space by setting the BRSTRM bit in BCR to 1, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected for burst ROM access. 6.6.1 Basic Operation Timing The number of access states in the initial cycle (full access) of the burst ROM interface is determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1 or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR. Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight words is performed when the BRSTS0 bit in BCR is set to 1. The basic access timing for the burst ROM space is shown in figures 6.14 and 6.15. Full access T1 T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changes AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) Rev. 3.00 Mar 21, 2006 page 141 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 Address bus Only lower address changes AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle. 6.7 Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM with a long output floating time, and high-speed memory and I/O interfaces. If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.16 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.16 (a), with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In figure 6.16 (b), an idle cycle is inserted, thus preventing data collision. Rev. 3.00 Mar 21, 2006 page 142 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Address bus RD HWR, LWR Data bus Address bus RD HWR, LWR Data bus Data collision Long output floating time (a) No idle cycle insertion (b) Idle cycle insertion Figure 6.16 Examples of Idle Cycle Operation Table 6.5 shows the pin states in an idle cycle. Table 6.5 Pins A23 to A0, IOS D15 to D0 AS RD HWR, LWR Pin States in Idle Cycle Pin State Contents of immediately following bus cycle High impedance High High High Rev. 3.00 Mar 21, 2006 page 143 of 788 REJ09B0300-0300 Section 6 Bus Controller (BSC) 6.8 Bus Arbitration The bus controller has a bus arbiter that arbitrates bus master operations. There are two bus masters - the CPU and DTC - that perform read/write operations when they have possession of the bus. 6.8.1 Priority of Bus Masters Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus masters' bus request signals, and if a bus request occurs, it sends a bus request acknowledge signal to the bus master making the request at the designated timing. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) 6.8.2 Bus Transfer Timing When a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. Each bus master can relinquish the bus at the timings given below. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the DTC. * DTC bus transfer timing The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. For details, refer to the H8S/2600 Series, H8S/2000 Series Programming Manual. If the CPU is in sleep mode, the bus is transferred immediately. DTC: The DTC has the highest bus master priority. The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC does not release the bus until it completes its operation. Rev. 3.00 Mar 21, 2006 page 144 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to addresses H'(FF)EC00 to H'(FF)EFFF in on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. 7.1 Features * Transfer is possible over any number of channels * Three transfer modes Normal, repeat, and block transfer modes are available. * One activation source can trigger a number of data transfers (chain transfer) * Direct specification of 16-Mbyte address space is possible * Activation by software is possible * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC * Module stop mode can be set DTCH80AA_000020020700 Rev. 3.00 Mar 21, 2006 page 145 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request DTC activation request Legend: : DTC mode register A, B MRA, MRB : DTC transfer count register A, B CRA, CRB : DTC source address register SAR : DTC destination register DAR DTCERA to DTCERE : DTC enable registers A to E : DTC vector register DTVECR Figure 7.1 Block Diagram of DTC Rev. 3.00 Mar 21, 2006 page 146 of 788 REJ09B0300-0300 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTCERA to DTCERE DTVECR Section 7 Data Transfer Controller (DTC) 7.2 Register Descriptions The DTC has the following registers. * DTC mode register A (MRA) * DTC mode register B (MRB) * DTC source address register (SAR) * DTC destination address register (DAR) * DTC transfer count register A (CRA) * DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to on-chip RAM. * DTC enable registers A to E (DTCERA to DTCERE) * DTC vector register (DTVECR) 7.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Rev. 3.00 Mar 21, 2006 page 147 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W -- -- Description Source Address Mode 1, 0 These bits specify an SAR operation after a data transfer. 0X: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 5 4 DM1 DM0 Undefined Undefined -- -- Destination Address Mode 1, 0 These bits specify a DAR operation after a data transfer. 0X: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 3 2 MD1 MD0 Undefined Undefined -- -- DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined -- DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area 0 Sz Undefined -- DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: X: Don't care Rev. 3.00 Mar 21, 2006 page 148 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit 7 Bit Name CHNE Initial Value Undefined R/W -- Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 7.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. 6 DISEL Undefined -- DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time data transfer ends (the DTC clears the interrupt source flag for the activation source). When this bit is cleared to 0, a CPU interrupt request is generated only when the specified number of data transfer ends (the DTC does not clear the interrupt source flag for the activation source). 5 to 0 -- Undefined -- Reserved These bits have no effect on DTC operation. Only 0 should be written to these bits. 7.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev. 3.00 Mar 21, 2006 page 149 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 7.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 7.2.7 DTC Enable Registers (DTCER) DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers: DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in table 7.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. Bit 7 6 5 4 3 2 1 0 Bit Name DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source as a DTC activation source. [Clearing conditions] * * When data transfer has ended with the DISEL bit in MRB set to 1. When the specified number of transfers have ended. [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not been completed. Rev. 3.00 Mar 21, 2006 page 150 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 at a reset and in hardware standby mode. Bit 7 Bit Name SWDTE Initial Value 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can always be written to this bit. 0 can be written to after reading 1 from this bit. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended. When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended. During data transfer activated by software [Holding conditions] * * * 6 5 4 3 2 1 0 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W DTC Software Activation Vectors 6 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the SWDTE bit is 0, these bits can be written to. Rev. 3.00 Mar 21, 2006 page 151 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.3 Activation Sources The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag in SCI_0. When an interrupt has been designated as a DTC activation source, the existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block diagram of DTC activation source control. For details on the interrupt controller, see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Select Clear request IRQ interrupt Interrupt request Selection circuit On-chip peripheral module DTC DTVECR Interrupt controller Interrupt mask CPU Figure 7.2 Block Diagram of DTC Activation Source Control Rev. 3.00 Mar 21, 2006 page 152 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3. Locate MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 7.3, and the register information start address should be located at the vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the start address of the register information from the vector table set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal and advanced modes; a 2-byte unit is used in both cases. Specify the lower two bits of the register information start address. Lower address 0 Register information start address MRA MRB Chain transfer CRA MRA MRB CRA SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3 4 bytes Figure 7.3 DTC Register Information Location in Address Space Rev. 3.00 Mar 21, 2006 page 153 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) Table 7.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Source Write to DTVECR IRQ0 IRQ1 IRQ2 Vector Number DTVECR 16 17 18 19 28 48 49 52 53 64 65 68 69 72 73 76 77 81 82 85 86 89 90 92 94 108 109 DTC Vector Address H'0400 + (vector number x 2) H'0420 H'0422 H'0424 H'0426 H'0438 H'0460 H'0462 H'0468 H'046A H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0498 H'049A H'04A2 H'04A4 H'04AA H'04AC H'04B2 H'04B4 H'04B8 H'04BC H'04D8 H'04DA DTCE* -- DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCEE3 DTCEE2 1 Activation Source Origin Software External pins Priority High A/D converter FRT IRQ3 ADI ICIA ICIB OCIA OCIB TMR_0 TMR_1 TMR_Y XBS SCI_0 SCI_1 SCI_2 IIC_0 IIC_1 2 LPC* CMIA0 CMIB0 CMIA1 CMIB1 CMIAY CMIBY IBF1 IBF2 RXI0 TXI0 RXI1 TXI1 RXI2 TXI2 IICI0 IICI1 ERRI IBFI1 IBFI2 110 H'04DC DTCEE1 IBFI3 111 H'04DE DTCEE0 Low Notes: 1. DTCE bits with no corresponding interrupt are reserved, and only 0 should be written to this bit. 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page 154 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.5 Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1 No Yes Transfer counter = 0 or DISEL = 1 No Clear an activation flag Yes Clear DTCER End Interrupt exception handling Figure 7.4 DTC Operation Flowchart Rev. 3.00 Mar 21, 2006 page 155 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.5.1 Normal Mode In normal mode, one activation source transfers one byte or one word of data. Table 7.2 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested. Table 7.2 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Functions in Normal Mode Abbreviation SAR DAR CRA CRB Function Transfer source address Transfer destination address Transfer counter Not used SAR Transfer DAR Figure 7.5 Memory Mapping in Normal Mode Rev. 3.00 Mar 21, 2006 page 156 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.5.2 Repeat Mode In repeat mode, one activation source transfers one byte or one word of data. Table 7.3 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated. In repeat mode, the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when the DISEL bit in MRB is cleared to 0. Table 7.3 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Functions in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds number of transfers Transfer Count Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 7.6 Memory Mapping in Repeat Mode Rev. 3.00 Mar 21, 2006 page 157 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.5.3 Block Transfer Mode In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.4 lists the register functions in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored. The other address register is then incremented, decremented, or left fixed according to the register information. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt is requested. Table 7.4 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Functions in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds block size Block size counter Transfer counter 1st block SAR or DAR * * * Block area Transfer DAR or SAR N th block Figure 7.7 Memory Mapping in Block Transfer Mode Rev. 3.00 Mar 21, 2006 page 158 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the register information start address stored at the DTC vector address, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Source DTC vector address Register information start address Register information CHNE = 1 Register information CHNE = 0 Destination Source Destination Figure 7.8 Chain Transfer Operation Rev. 3.00 Mar 21, 2006 page 159 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control by the interrupt controller. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 7.5.6 Operation Timing DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Rev. 3.00 Mar 21, 2006 page 160 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) DTC activation request DTC request Data transfer Read Write Read Write Vector read Address Transfer information read Transfer information write Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Data transfer Transfer information read Transfer information write Transfer information read Transfer information write Figure 7.11 DTC Operation Timing (Example of Chain Transfer) 7.5.7 Number of DTC Execution States Table 7.5 lists the execution status for a single DTC data transfer, and table 7.6 shows the number of states required for each execution status. Rev. 3.00 Mar 21, 2006 page 161 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) Table 7.5 DTC Execution Status Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer N: Block size (initial setting of CRAH and CRAL) Table 7.6 Number of States Required for Each Execution Status OnChip RAM 32 1 -- 1 1 1 1 1 OnChip ROM 16 1 1 -- 1 1 1 1 On-Chip I/O Registers 8 2 -- -- 2 4 2 4 16 2 -- -- 2 2 2 2 1 2 4 -- 2 4 2 4 External Devices 8 3 6 + 2m -- 3+m 6 + 2m 3+m 6 + 2m 2 2 -- 2 2 2 2 16 3 3+m -- 3+m 3+m 3+m 3+m Object to be Accessed Bus width Access states Execution Vector read SI status Register information read/write SJ Byte data read Word data read Byte data write Word data write SK SK SL SL Internal operation SM The number of execution states is calculated from using the formula below. Note that is the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of data write is 10 states. Rev. 3.00 Mar 21, 2006 page 162 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.6 7.6.1 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After one data transfer has been completed, or after the specified number of data transfers have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 7.6.2 Activation by Software The procedure for using the DTC with software activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Check that the SWDTE bit is 0. 4. Write 1 to the SWDTE bit and the vector number to DTVECR. 5. Check the vector number written to DTVECR. 6. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1 or after the specified number of data transfers have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested. Rev. 3.00 Mar 21, 2006 page 163 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.7 7.7.1 Examples of Use of DTC Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI, RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after 128 data transfers have been completed, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine will perform wrap-up processing. Rev. 3.00 Mar 21, 2006 page 164 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.7.2 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the transfer destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform wrap-up processing. Rev. 3.00 Mar 21, 2006 page 165 of 788 REJ09B0300-0300 Section 7 Data Transfer Controller (DTC) 7.8 7.8.1 Usage Notes Module Stop Mode Setting DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop mode is set. Note that when the DTC is being activated, module stop mode cannot be specified. For details, refer to section 26, Power-Down Modes. 7.8.2 On-Chip RAM MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR should not be cleared to 0. 7.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. 7.8.4 Setting Required on Entering Subactive Mode or Watch Mode Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm that is set to 1 before making a transition to subactive mode or watch mode. 7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter Interrupt sources of the SCI, IIC, LPC, or A/D converter which activate the DTC are cleared when DTC reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit in MRB. Rev. 3.00 Mar 21, 2006 page 166 of 788 REJ09B0300-0300 Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview This LSI has ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7). For additional ports C to G in H8S/2160B and H8S/2161B, see section 8.13 Additional Overview for H8S/2160B and H8S/2161B. Table 8.1 is a summary of the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port) and data registers (DR, ODR) that store output data. Ports 1 to 3, 6, A, and B have an on-chip input pull-up MOS function. For ports A and B, the on/off status of the input pull-up MOS is controlled by DDR and ODR. Ports 1 to 3 and 6 have an input pull-up MOS control register (PCR), in addition to DDR, to control the on/off status of the input pull-up MOS. Ports 1 to 6, 8, 9, A, and B can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1 to 3 can drive an LED (10 mA sink current). Port A input and output use by the VccB power supply, which is independent of the VCC power supply. When the VccB voltage is 5V, the pins on port A will be 5-V tolerant. PA4 to PA7 of port A have bus-buffer drive capability. P52 in port 5, P97 in port 9, P86 in port 8 and P42 in port 4 are NMOS push-pull outputs. P52, P97, P86 and P42 are thus 5-V tolerant, with DC characteristics that are dependent on the VCC voltage. For the P42/SCK2, P52/SCK0, P86/SCK1, and P97 outputs, connect pull-up resistors to pins to raise output-high-level voltage. Rev. 3.00 Mar 21, 2006 page 167 of 788 REJ09B0300-0300 Section 8 I/O Ports Table 8.1 Port Port 1 Port Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B Description Mode 1 A7 A6 A5 A4 A3 A2 A1 A0 Modes 2 and 3 (EXPE = 1) A7/P17/PW7 A6/P16/PW6 A5/P15/PW5 A4/P14/PW4 A3/P13/PW3 A2/P12/PW2 A1/P11/PW1 A0/P10/PW0 A15/P27/PW15/ CBLANK A14/P26/PW14 A13/P25/PW13 A12/P24/PW12 A11/P23/PW11 A10/P22/PW10 A9/P21/PW9 A8/P20/PW8 (EXPE = 0) P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 P27/PW15/CBLANK P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 P37/HDB7/SERIRQ* P36/HDB6/LCLK* P35/HDB5/LRESET* P34/HDB4/LFRAME* P33/HDB3/LAD3* P32/HDB2/LAD2* P31/HDB1/LAD1* P30/HDB0/LAD0* On-chip input pullup MOSs On-chip input pullup MOSs I/O Status On-chip input pullup MOSs General I/O port also functioning as address output and PWM output pins Port 2 General I/O port also functioning as address output pin, PWM output pin, and timer connection output pin A15 A14 A13 A12 A11 A10 A9 A8 Port 3 General I/O port also functioning as data bus input/output, XBS data bus input/output, and LPC input/output pins D15 D14 D13 D12 D11 D10 D9 D8 Rev. 3.00 Mar 21, 2006 page 168 of 788 REJ09B0300-0300 Section 8 I/O Ports Modes 2 and 3 (EXPE = 1) (EXPE = 0) P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/ CSYNCI P44/TMO1/HIRQ1/ HSYNCO P43/TMCI1/HIRQ11/ HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD Port 5 General I/O port also functioning as SCI_0 input/output and IIC_0 input/output pins General I/O port also functioning as interrupt input, FRT input/output, TMR_X and TMR_Y input/output, timer connection input/output, key-sense interrupt input, and expansion A/D input pins P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P67/IRQ7/TMOX/KIN7/CIN7 P66/IRQ6/FTOB/KIN6/CIN6 P65/FTID/KIN5/CIN5 P64/FTIC/KIN4/CIN4/CLAMPO P63/FTIB/KIN3/CIN3/VFBACKI P62/FTIA/TMIY/KIN2/CIN2/VSYNCI P61/FTOA/KIN1/CIN1/VSYNCO P60/FTCI/TMIX/KIN0/CIN0/HFBACKI Port 7 General input port also functioning as A/D converter analog input and D/A converter analog output pins P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 On-chip input pullup MOSs I/O Status Port Port 4 Description General I/O port also functioning as PWMX output, TMR_0 and TMR_1 input/output, timer connection input/output, XBS host interrupt request output, SCI_2 input/output, IrDA interface input/output, and IIC_1 input/output pins Mode 1 P47/PWX1 P46/ PWX0 P45/TMRI1/CSYNCI P44/TMO1/HSYNCO P43/TMCI1/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD Port 6 Rev. 3.00 Mar 21, 2006 page 169 of 788 REJ09B0300-0300 Section 8 I/O Ports Modes 2 and 3 (EXPE = 1) (EXPE = 0) P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83/LPCPD* P82/HIFSD/CLKRUN* P81/CS2/GA20 P80/HA0/PME* P97/SDA0 P96//EXCL P95/CS1 P94/IOW P93/IOR P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG/ ECS2 PA7/KIN15/CIN15/ PS2CD PA6/KIN14/CIN14/ PS2CC PA5/KIN13/CIN13/ PS2BD PA4/KIN12/CIN12/ PS2BC PA3/KIN11/CIN11/ PS2AD PA2/KIN10/CIN10/ PS2AC On-chip input pullup MOSs I/O Status Port Port 8 Description General I/O port also functioning as interrupt input, SCI_1 input/output, XBS control input/output, LPC input/output, and IIC_1 input/output pins Mode 1 P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80 Port 9 General I/O port also functioning as extended data bus control input/output, IIC_0 input/output, subclock input, output, interrupt input, XBS control input, and A/D converter external trigger input pins P97/WAIT/SDA0 P96//EXCL AS/IOS HWR RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG Port A General I/O port also functioning as address output, key-sense interrupt input, extended A/D input, and keyboard buffer controller input/output pins PA7/KIN15/ PA7/A23/KIN15/ CIN15/PS2CD CIN15/PS2CD PA6/KIN14/ PA6/A22/KIN14/ CIN14/PS2CC CIN14/PS2CC PA5/KIN13/ PA5/A21/KIN13/ CIN13/PS2BD CIN13/PS2BD PA4/KIN12/ PA4/A20/KIN12/ CIN12/PS2BC CIN12/PS2BC PA3/KIN11/ PA3/A19/KIN11/ CIN11/PS2AD CIN11/PS2AD PA2/KIN10/ PA2/A18/KIN10/ CIN10/PS2AC CIN10/PS2AC PA1/KIN9/ CIN9 PA0/KIN8/ CIN8 PA1/A17/KIN9/CIN9 PA1/KIN9/CIN9 PA0/A16/KIN8/CIN8 PA0/KIN8/CIN8 Rev. 3.00 Mar 21, 2006 page 170 of 788 REJ09B0300-0300 Section 8 I/O Ports Modes 2 and 3 (EXPE = 1) (EXPE = 0) PB7/WUE7* PB6/WUE6* PB5/WUE5* PB4/WUE4* PB3/WUE3*/CS4 PB2/WUE2*/CS3 PB1/WUE1*/HIRQ4/ LSCI* PB0/WUE0*/HIRQ3/ LSMI* I/O Status On-chip input pullup MOSs Port Description Mode 1 PB7/D7/WUE7* PB6/D6/WUE6* PB5/D5/WUE5* PB4/D4/WUE4* PB3/D3/WUE3* PB2/D2/WUE2* PB1/D1/WUE1* PB0/D0/WUE0* Port B General I/O port also functioning as wakeup event interrupt input, data bus input/output, XBS control input/output, and LPC input/output pins Note: * Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page 171 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.2 Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as an address bus and PWM output pins. Port 1 functions change according to the operating mode. Port 1 has an on-chip input pull-up MOS function that can be controlled by software. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 pull-up MOS control register (P1PCR) 8.2.1 Port 1 Data Direction Register (P1DDR) P1DDR specifies input or output for the pins of port 1 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In mode 1: Each pin of port 1 is address output regardless of the set value of P1DDR. In modes 2 and 3 (EXPE=1): The corresponding port 1 pins are address output or PWM output ports when P1DDR bits are set to 1, and input ports when cleared to 0. In modes 2 and 3 (EXPE=0): The corresponding port 1 pins are output ports or PWM outputs when the P1DDR bits are set to 1, and input ports when cleared to 0. Rev. 3.00 Mar 21, 2006 page 172 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.2.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 1 read is performed while the P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while the P1DDR bits are cleared to 0, the pin states are read. 8.2.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on/off status of the port 1 on-chip input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a P1PCR bit is set to 1. Rev. 3.00 Mar 21, 2006 page 173 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.2.4 Pin Functions * P17/A7/PW7 to P10/A0/PW0 The pin function is switched as shown below according to the combination of the OEn bit in PWOERA of PWM, the P1nDDR bit, and operating mode. Operating Mode P1nDDR OEn Pin Function Mode 1 -- -- A7 to A0 output pins 0 -- P17 to P10 input pins 0 A7 to A0 output pins Mode 2, 3 (EXPE = 1) 1 1 PW7 to PW0 output pins 0 -- P17 to P10 input pins 0 P17 to P10 output pins Mode 2, 3 (EXPE = 0) 1 1 PW7 to PW0 output pins Note: n = 7 to 0 8.2.5 Port 1 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 8.2 summarizes the input pull-up MOS states. Table 8.2 Mode 1 2, 3 Input Pull-Up MOS States (Port 1) Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P1DDR = 0, and P1PCR = 1; otherwise off. Rev. 3.00 Mar 21, 2006 page 174 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.3 Port 2 Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus output function, 8-bit PWM output pins, and the timer connection output pin. Port 2 functions change according to the operating mode. Port 2 has an on-chip input pull-up MOS function that can be controlled by software. Port 2 has the following registers. * Port 2 data direction register (P2DDR) * Port 2 data register (P2DR) * Port 2 pull-up MOS control register (P2PCR) 8.3.1 Port 2 Data Direction Register (P2DDR) P2DDR specifies input or output for the pins of port 2 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In Mode 1: The corresponding port 2 pins are address outputs, regardless of the P2DDR setting. Modes 2 and 3 (EXPE = 1): The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to 1. P27 can be used as an on-chip peripheral module output pin regardless of the P27DDR setting, but to ensure normal access to external space, P27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. Modes 2 and 3 (EXPE = 0): The corresponding port 2 pins are output ports or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 can be used as an on-chip peripheral module output pin regardless of the P27DDR setting. Rev. 3.00 Mar 21, 2006 page 175 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.3.2 Port 2 Data Register (P2DR) P2DR stores output data for port 2. Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly, regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. 8.3.3 Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the port 2 on-chip input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 2 and 3, the input pull-up MOS is turned on when a P2PCR bit is set to 1 in the input port state. Rev. 3.00 Mar 21, 2006 page 176 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.3.4 Pin Functions To ensure normal access to external space, P27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. * P27/A15/PW15/CBLANK The pin function is switched as shown below according to the combination of the IOSE bit in SYSCR, the CBOE bit in TCONRO of timer connection, the OE15 bit in PWOERB of PWM, the P27DDR bit, and operating mode. Operating Mode CBOE P27DDR OE15 IOSE Pin Function Mode 1 -- -- -- -- A15 output pin 0 -- -- P27 input pin 0 A15 output pin 0 1 P27 output pin Mode 2, 3 (EXPE = 1) 0 1 1 -- PW15 output pin 1 -- -- -- CBLANK Mode 2, 3 (EXPE = 0) 0 0 -- -- P27 input pin 0 -- P27 output pin 1 1 -- PW15 output pin 1 -- -- -- CBLANK output pin output pin * P26/A14/PW14, P25/A13/PW13, P24/A12/PW12 The pin function is switched as shown below according to the combination of the IOSE bit in SYSCR, the OEm bit in PWOERB of PWM, the P2nDDR bit, and operating mode. Operating Mode P2nDDR OEm IOSE Pin Function Mode 1 -- -- -- A14 to A12 output pins 0 -- -- P26 to P24 input pins 0 A14 to A12 output pins 0 1 P26 to P24 output pins Mode 2, 3 (EXPE = 1) 1 1 -- PW14 to PW12 output pins Mode 2, 3 (EXPE = 0) 0 -- -- P26 to P24 input pins 0 1 P26 to P24 output pins 1 1 -- PW14 to PW12 output pins Note: n = 6 to 4 m = 14 to 12 Rev. 3.00 Mar 21, 2006 page 177 of 788 REJ09B0300-0300 Section 8 I/O Ports * P23/A11/PW11, P22/A10/PW10, P21/A9/PW9, P20/A8/PW8 The pin function is switched as shown below according to the combination of the OEm bit in PWOERB of PWM, the P2nDDR bit, and operating mode. Operating Mode P2nDDR OEm Pin Function Mode 1 -- -- A11 to A8 output pins 0 -- P23 to P20 input pins 0 A11 to A8 output pins Mode 2, 3 (EXPE = 1) 1 1 PW11 to PW8 output pins 0 -- P23 to P20 input pins 0 P23 to P20 output pins Mode 2, 3 (EXPE = 0) 1 1 PW11 to PW8 output pins Note: n = 3 to 0 m = 11 to 8 8.3.5 Port 2 Input Pull-Up MOS Port 2 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 8.3 summarizes the input pull-up MOS states. Table 8.3 Mode 1 2, 3 Input Pull-Up MOS States (Port 2) Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P2DDR = 0, and P2PCR = 1; otherwise off. Rev. 3.00 Mar 21, 2006 page 178 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.4 Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as a bidirectional data bus, XBS bidirectional data bus, and LPC input/output pins. Port 3 functions change according to the operating mode. Port 3 has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 pull-up MOS control register (P3PCR) 8.4.1 Port 3 Data Direction Register (P3DDR) P3DDR specifies input or output for the pins of port 3 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Modes 1, 2, and 3 (EXPE = 1) The input/output direction specified by P3DDR is ignored, and pins automatically function as data I/O pins. Modes 2 and 3 (EXPE = 0) The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports when cleared to 0. Rev. 3.00 Mar 21, 2006 page 179 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.4.2 Port 3 Data Register (P3DR) P3DR stores output data of port 3. Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. 8.4.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 on-chip input pull-up MOSs on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 2 and 3 (when EXPE = 0), the input pullup MOS is turned on when a P3PCR bit is set to 1 in the input port state. The input pull-up MOS function cannot be used when the host interface is enabled. Rev. 3.00 Mar 21, 2006 page 180 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.4.4 Pin Functions * P37/D15/HDB7/SERIRQ*, P36/D14/HDB6/LCLK*, P35/D13/HDB5/LRESET*, P34/D12/HDB4/LFRAME*, P33/D11/HDB3/LAD3*, P32/D10/HDB2/LAD2*, P31/D9/HDB1/LAD1*, P30/D8/HDB0/LAD0* The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the LPC3E to LPC1E bits in HICR0 of host interface (LPC), the P3nDDR bit, and operating mode. Note: * Not supported by the H8S/2148B and H8S/2145B (5-V version). Operating Mode LPCmE HI12E P3nDDR Pin Function Mode 1, 2, 3 (EXPE = 1) All 0 0 -- D15 to D8 input/output pins 0 P37 to P30 input pins 0 1 P37 to P30 output pins Mode 2, 3 (EXPE = 0) All 0 1 -- HDB7 to HDB0 input/output pins Not all 0 0 0 LPC input/output pins Notes: The combination of bits not described in the above table must not be used. m = 3 to 1: LPC input/output pins (SERIRQ, LCLK, LRESET, LFRAME, LAD3 to LAD0) when at least one of LPC3E to LPC1E is set to 1. n = 7 to 0 8.4.5 Port 3 Input Pull-Up MOS Port 3 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 8.4 summarizes the input pull-up MOS states. Table 8.4 Mode 1, 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Input Pull-Up MOS States (Port 3) Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P3DDR = 0, and P3PCR = 1; otherwise off. Rev. 3.00 Mar 21, 2006 page 181 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.5 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as PWMX output pins, TMR_0 and TMR_1 I/O pins, timer connection I/O pins, SCI_2 I/O pins, IrDA interface I/O pins, XBS output pins, and the IIC_1 I/O pin. The output type of P42 and SCK2 is NMOS push-pull output. The output type of SDA1 is NMOS open drain output. Port 4 pin functions are the same in all operating modes. Port 4 has the following registers. * Port 4 data direction register (P4DDR) * Port 4 data register (P4DR) 8.5.1 Port 4 Data Direction Register (P4DDR) P4DDR specifies input or output for the pins of port 4 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a bit in P4DDR is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. As 14-bit PWM and SCI_2 are initialized in software standby mode, the pin states are determined by the TMR_0, TMR_1, XBS, IIC_1, P4DDR, and P4DR specifications. Rev. 3.00 Mar 21, 2006 page 182 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.5.2 Port 4 Data Register (P4DR) P4DR stores output data for port 4. Bit 7 6 5 4 3 2 1 0 Bit Name P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly, regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0, the pin states are read. 8.5.3 Pin Functions * P47/PWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR of the 14-bit PWM and the P47DDR bit. OEB P47DDR Pin Function 0 P47 input pin 0 1 P47 output pin 1 -- PWX1 output pin * P46/PWX0 The pin function is switched as shown below according to the combination of the OEA bit in DACR of the 14-bit PWM and the P46DDR bit. OEA P46DDR Pin Function 0 P46 input pin 0 1 P46 output pin 1 -- PWX0 output pin Rev. 3.00 Mar 21, 2006 page 183 of 788 REJ09B0300-0300 Section 8 I/O Ports * P45/TMRI1/HIRQ12/CSYNCI The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2 and the P45DDR bit. P45DDR HI12E Pin Function Note: * 0 0 P45 input pin 0 P45 output pin TMRI1 input pin, CSYNCI input pin* When bits CCLR1 and CCLR0 in TCR1 of TMR_1 are set to 1, this pin is used as the TMRI1 input pin. It can also be used as the CSYNCI input pin. 1 1 HIRQ12 output pin * P44/TMO1/HIRQ1/HSYNCO The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the OS3 to OS0 bits in TCSR of TMR_1, the HOE bit in TCONRO of the timer connection function, and the P44DDR bit. HOE OS3 to OS0 P44DDR HI12E Pin Function 0 -- P44 input pin 0 P44 output pin All 0 1 1 HIRQ1 output pin 0 Not all 0 -- -- TMO1 output pin 1 -- -- -- HSYNCO output pin * P43/TMCI1/HIRQ11/HSYNCI The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2 and the P43DDR bit. P43DDR HI12E Pin Function Note: * 0 -- P43 input pin 0 P43 output pin TMCI1 input pin, HSYNCI input pin* When the external clock is selected by bits CKS2 to CKS0 in TCR1 of TMR_1, this pin is used as the TMCI1 input pin. It can also be used as the HSYNCI input pin. 1 1 HIRQ11 output pin Rev. 3.00 Mar 21, 2006 page 184 of 788 REJ09B0300-0300 Section 8 I/O Ports * P42/TMRI0/SCK2/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC1, the CKE1 and CKE0 bits in SCR of SCI_2, the C/A bit in SMR of SCI_2, and the P42DDR bit. ICE CKE1 C/A CKE0 P42DDR Pin Function 0 P42 input pin 0 1 P42 output pin 0 1 -- SCK2 output pin 0 1 -- -- 0 1 -- -- -- SCK2 input pin 1 0 0 0 -- SDA1 I/O pin SCK2 output pin TMRI0 input pin* Note: * When this pin is used as the SDA1 I/O pin, bits CKE1 and CKE0 in SCR of SCI_2 and bit C/A in SMR of SCI_2 must all be cleared to 0. SDA1 is an NMOS-only output, and has direct bus drive capability. When bits CCLR1 and CCLR0 in TCR0 of TMR_0 are set to 1, this pin is used as the TMRI0 input pin. When the P42 output pin and SCK2 output pin are set, the output type is NMOS pushpull output. * P41/TMO0/RxD2/IrRxD The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR0, the RE bit in SCR of SCI_2 and the P41DDR bit. OS3 to OS0 RE P41DDR Pin Function 0 P41 input pin 0 1 P41 output pin All 0 1 -- RxD2/IrRxD input pin Not all 0 0 -- TMO0 output pin Note: When this pin is used as the TMO0 output pin, bit RE in SCR of SCI_2 must be cleared to 0. Rev. 3.00 Mar 21, 2006 page 185 of 788 REJ09B0300-0300 Section 8 I/O Ports * P40/TMCI0/TxD2/IrTxD The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_2 and the P40DDR bit. TE P40DDR Pin Function 0 P40 input pin 0 1 P40 output pin TMCI0 input pin* Note: * When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR_0, this pin is used as the TMCI0 input pin. 1 -- TxD2/IrTxD output pin 8.6 Port 5 Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_0 I/O pins, and the IIC_0 I/O pin. P52 and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 has the following registers. * Port 5 data direction register (P5DDR) * Port 5 data register (P5DR) 8.6.1 Port 5 Data Direction Register (P5DDR) P5DDR specifies input or output for the pins of port 5 on a bit-by-bit basis. Bit 7 to 3 2 1 0 Bit Name -- Initial Value All 1 R/W -- Description Reserved The initial value must not be changed. P52DDR P51DDR P50DDR 0 0 0 W W W The corresponding port 5 pins are output ports when P5DDR bits are set to 1, and input ports when cleared to 0. As SCI_0 is initialized in software standby mode, the pin states are determined by the IIC_0 ICCR, P5DDR, and P5DR specifications. Rev. 3.00 Mar 21, 2006 page 186 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.6.2 Port 5 Data Register (P5DR) P5DR stores output data for port 5 pins. Bit 7 to 3 2 1 0 Bit Name -- Initial Value All 1 R/W -- Description Reserved The initial value must not be changed. P52DR P51DR P50DR 0 0 0 R/W R/W R/W If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly, regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. 8.6.3 Pin Functions * P52/SCK0/SCL0 The pin function is switched as shown below according to the combination of the CKE1 and CKE0 bits in SCR of SCI_0, the C/A bit in SMR of SCI_0, the ICE bit in ICCR of IIC_0, and the P52DDR bit. ICE CKE1 C/A CKE0 P52DDR Pin Function 0 P52 input pin 0 1 P52 output pin 0 1 -- SCK0 output pin 0 1 -- -- SCK0 output pin 0 1 -- -- -- SCK0 input pin 1 0 0 0 -- SCL0 I/O pin Note: When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of SCI0 and bit C/A in SMR of SCI0 must all be cleared to 0. SCL0 is an NMOS open-drain output, and has direct bus drive capability. When set as the P52 output pin or SCK0 output pin, this pin is an NMOS push-pull output. Rev. 3.00 Mar 21, 2006 page 187 of 788 REJ09B0300-0300 Section 8 I/O Ports * P51/RxD0 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_0 and the P51DDR bit. RE P51DDR Pin Function 0 P51 input pin 0 1 P51 output pin 1 -- RxD0 input pin * P50/TxD0 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_0 and the P50DDR bit. TE P50DDR Pin Function 0 P50 input pin 0 1 P50 output pin 1 -- TxD0 output pin 8.7 Port 6 Port 6 is an 8-bit I/O port. Port 6 pins also function as the FRT I/O pins, TMR_X I/O pins, the TMR_Y input pin, timer connection I/O pins, key-sense interrupt input pins, expansion A/D converter input pins, and external interrupt input pins. The port 6 input level can be switched in four stages. Port 6 pin functions are the same in all operating modes. For details on the system control register 2 (SYSCR2), refer to section 18, Host Interface X-Bus Interface (XBS). Port 6 has the following registers. * Port 6 data direction register (P6DDR) * Port 6 data register (P6DR) * Port 6 pull-up MOS control register (KMPCR) * System control register 2 (SYSCR2) Rev. 3.00 Mar 21, 2006 page 188 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.7.1 Port 6 Data Direction Register (P6DDR) P6DDR specifies input or output for the pins of port 6 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 6 pins are output ports when P6DDR bits are set to 1, and input ports when cleared to 0. 8.7.2 Port 6 Data Register (P6DR) P6DR stores output data for port 6. Bit 7 6 5 4 3 2 1 0 Bit Name P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. Rev. 3.00 Mar 21, 2006 page 189 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.7.3 Port 6 Pull-Up MOS Control Register (KMPCR) KMPCR controls the port 6 on-chip input pull-up MOSs on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The input pull-up MOS is turned on when a KMPCR bit is set to 1 while the corresponding P6DDR bit is cleared to 0 (input port setting). 8.7.4 Pin Functions * P67/TMOX/CIN7/KIN7/IRQ7 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_X and the P67DDR bit. OS3 to OS0 P67DDR Pin Function Note: * 0 P67 input pin All 0 1 P67 output pin Not all 0 -- TMOX output pin IRQ7 input pin, KIN7 input pin, CIN7 input pin* This pin is used as the IRQ7 input pin when bit IRQ7E is set to 1 in IER. It can always be used as the KIN7 or CIN7 input pin. Rev. 3.00 Mar 21, 2006 page 190 of 788 REJ09B0300-0300 Section 8 I/O Ports * P66/FTOB/CIN6/KIN6/IRQ6 The pin function is switched as shown below according to the combination of the OEB bit in TOCR of the FRT and the P66DDR bit. OEB P66DDR Pin Function Note: * 0 0 P66 input pin 1 P66 output pin 1 -- FTOB output pin IRQ6 input pin, KIN6 input pin, CIN6 input pin* This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER while the KMIMR6 bit in KMIMR is 0. It can always be used as the KIN6 or CIN6 input pin. * P65/FTID/CIN5/KIN5 P65DDR Pin Function Note: * 0 P65 input pin 1 P65 output pin FTID input pin, KIN5 input pin, CIN5 input pin* This pin can always be used as the FTID, KIN5, or CIN5 input pin. * P64/FTIC/CIN4/KIN4/CLAMPO The pin function is switched as shown below according to the combination of the CLOE bit in TCONRO of the timer connection function and the P64DDR bit. CLOE P64DDR Pin Function Note: * 0 P64 input pin 0 1 P64 output pin 1 -- CLAMPO output pin FTIC input pin, KIN4 input pin, CIN4 input pin* This pin can always be used as the FTIC, KIN4, or CIN4 input pin. * P63/FTIB/CIN3/KIN3/VFBACKI P63DDR Pin Function Note: * 0 P63 input pin 1 P63 output pin FTIB input pin, VFBACKI input pin, KIN3 input pin, CIN3 input pin* This pin can always be used as the FTIB, KIN3, CIN3, or VFBACKI input pin. Rev. 3.00 Mar 21, 2006 page 191 of 788 REJ09B0300-0300 Section 8 I/O Ports * P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P62DDR Pin Function 0 P62 input pin 1 P62 output pin FTIA input pin, VSYNCI input pin, TMIY input pin, KIN2 input pin, CIN2 input pin* Note: * This pin can always be used as the FTIA, TMIY, KIN2, CIN2, or VSYNCI input pin. * P61/FTOA/CIN1/KIN1/VSYNCO The pin function is switched as shown below according to the combination of the OEA bit in TOCR of the FRT, the VOE bit in TCONRO of the timer connection function, and the P61DDR bit. VOE OEA P61DDR Pin Function 0 P61 input pin 0 1 P61 output pin 0 1 -- FTOA output pin 1 -- -- VSYNCO output pin KIN1 input pin, CIN1 input pin* Note: * When this pin is used as the VSYNCO pin, bit OEA in TOCR of the FRT must be cleared to 0. This pin can always be used as the KIN1 or CIN1 input pin. * P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P60DDR Pin Function 0 P60 input pin 1 P60 output pin FTCI input pin, HFBACKI input pin, TMIX input pin, KIN0 input pin, CIN0 input pin* Note: * This pin is used as the FTCI input pin when an external clock is selected with bits CKS1 and CKS0 in TCR of the FRT. It can always be used as the TMIX, KIN0, CIN0, or HFBACKI input pin. Rev. 3.00 Mar 21, 2006 page 192 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.7.5 Port 6 Input Pull-Up MOS Port 6 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. The input pull-up MOS current specification can be changed by means of the P6PUE bit. When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is always off. Table 8.5 summarizes the input pull-up MOS states. Table 8.5 Mode 1 to 3 Input Pull-Up MOS States (Port 6) Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P6DDR = 0, and KMPCR = 1; otherwise off. 8.8 Port 7 Port 7 is an 8-bit input only port. Port 7 pins also function as the A/D converter analog input pins and D/A converter analog output pins. Port 7 functions are the same in all operating modes. Port 7 has the following register. * Port 7 input data register (P7PIN) Rev. 3.00 Mar 21, 2006 page 193 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.8.1 Port 7 Input Data Register (P7PIN) P7PIN reflects the pin states of port 7. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When a P7PIN read is performed, the pin states are always read. P7PIN has the same address as PBDDR; if a write is performed, data will be written into PBDDR and the port B setting will be changed. Determined by the pin states of P77 to P70. 8.8.2 Pin Functions * P77/AN7/DA1 The pin function is switched as shown below according to the combination of the DAE bit in DACR of the D/A converter and the DAOE1 bit. DAOE1 DAE Pin Function Note: * 0 P77 input pin 0 1 DA1 input pin AN7 input pin* 1 -- DA1 output pin This pin can always be used as the AN7 input pin. * P76/AN6/DA0 The pin function is switched as shown below according to the combination of the DAE bit in DACR of the D/A converter and the DAOE0 bit. DAOE0 DAE Pin Function Note: * 0 P76 input pin 0 1 DA0 output pin AN6 input pin* 1 -- DA0 output pin This pin can always be used as the AN6 input pin. Rev. 3.00 Mar 21, 2006 page 194 of 788 REJ09B0300-0300 Section 8 I/O Ports * P75/AN5, P74/AN4, P73/AN3, P72/AN2, P71/AN1, P70/AN0 Pin Function Note: * P75 to P70 input pins AN5 to AN0 input pin* This pin can always be used as the AN5 to AN0 input pins. 8.9 Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins, the IIC_1 I/O pin, XBS I/O pins, LPC I/O pins, and interrupt input pins. The output type of P86 and SCK1 is NMOS push-pull output. The output type of SCL1 is NMOS open drain output and direct bus driving is enabled. Port 8 pin functions are the same in all operating modes except host interface function. Port 8 has the following registers. * Port 8 data direction register (P8DDR) * Port 8 data register (P8DR) 8.9.1 Port 8 Data Direction Register (P8DDR) P8DDR specifies input or output for the pins of port 8 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name -- P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial Value 1 0 0 0 0 0 0 0 R/W -- W W W W W W W Description Reserved The initial value must not be changed. P8DDR has the same address as PBPIN, and if read, the port B state will be returned. The corresponding port 8 pins are output ports when P8DDR bits are set to 1, and input ports when cleared to 0. Rev. 3.00 Mar 21, 2006 page 195 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.9.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins (P86 to P80). Bit 7 6 5 4 3 2 1 0 Bit Name -- P86DR P85DR P84DR P83DR P82DR P81DR P80DR Initial Value 1 0 0 0 0 0 0 0 R/W -- R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value must not be changed. If a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read directly, regardless of the actual pin states. If a port 8 read is performed while P8DDR bits are cleared to 0, the pin states are read. 8.9.3 Pin Functions * P86/IRQ5/ SCK1/SCL1 The pin function is switched as shown below according to the combination of the CKE1 and CKE0 bits in SCR of SCI_1, the C/A bit in SMR of SCI_1, the ICE bit in ICCR of IIC_1, and the P86DDR bit. ICE CKE1 C/A CKE0 P86DDR Pin Function 0 P86 input pin 0 1 P86 output pin 0 1 -- SCK1 output pin 0 1 -- -- 0 1 -- -- -- SCK1 input pin 1 0 0 0 -- SCL1 I/O pin SCK1 output pin IRQ5 input pin* Note: * When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 input pin. When this pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of SCI_1 and bit C/A in SMR of SCI_1 must all be cleared to 0. When the P86 output pin and SCK1 output pin are set, the output type is NMOS push-pull output. SCL1 is an NMOS-only output, and has direct bus drive capability. Rev. 3.00 Mar 21, 2006 page 196 of 788 REJ09B0300-0300 Section 8 I/O Ports * P85/IRQ4/RxD1 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P85DDR bit. RE P85DDR Pin Function Note: * 0 P85 input pin 0 1 P85 output pin IRQ4 input pin* 1 -- RxD1 input pin When the IRQ4E bit in IER is set to 1, this pin is used as the IRQ4 input pin. * P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P84DDR bit. TE P84DDR Pin Function Note: * 0 P84 input pin 0 1 P84 output pin IRQ3 input pin* When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 input pin. 2 1 -- TxD1 output pin * P83/LPCPD* The pin function is switched as shown below according to the P83DDR bit. P83DDR Pin Function 0 P83 input pin 12 LPCPD input pin* * 1 P83 output pin Notes: 1. When at least one of bits LPC3E to LPC1E is set to 1 in HICR0, this pin is used as the LPCPD input pin. The LPCPD input pin can only be used in mode 2 or 3 (EXPE = 0). 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page 197 of 788 REJ09B0300-0300 Section 8 I/O Ports * P82/HIFSD/CLKRUN* 2 The pin function is switched as shown below according to the combination of the HI12E and SDE bits in SYSCR2, the LPC3E to LPC1E bits in HICR0, and the P82DDR bit. LPC3E to LPC1E HI12E SDE P82DDR Pin Function Notes: 0 P82 input pin 0 -- 1 P82 output pin 0 P82 input pin 0 1 P82 output pin All 0 1 1 -- HIFSD input pin Not all 0 0* 1 -- 1 0* CLKRUN 2 I/O pin* The HIFSD input pin and CLKRUN I/O pin can only be used in mode 2 or 3 (EXPE = 0). 1. When at least one of bits LPC3E to LPC1E is set to 1, bits HI12E and P82DDR should be cleared to 0. 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). * P81/CS2/GA20 The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the CS2E bit in SYSCR, the FGA20E bit in HICR, the FGA20E bit in HICR0, and the P81DDR bit. FGA20E (LPC) HI12E FGA20E (XBS) CS2E P81DDR Pin Function 0 P81 input pin 0 -- -- 1 P81 output pin 0 P81 input pin 0 1 P81 output pin 0 1 -- 0 P81 input pin CS2 input 2 pin* 2 GA20 input pin* 0 1 1 -- 1 GA20 output pin 1 1 0* -- -- 1 0* GA20 output pin Notes: 1. When bit FGA20E is set to 1 in HICR0, bits HI12E and P81DDR should be cleared to 0. 2. The GA20 output pin and CS2 input pin can only be used in mode 2 or 3 (EXPE = 0). Rev. 3.00 Mar 21, 2006 page 198 of 788 REJ09B0300-0300 Section 8 I/O Ports * P80/HA0/PME* 3 The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the PMEE bit in HICR0, and the P80DDR bit. PMEE HI12E P80DDR Pin Function 0 P80 input pin 0 1 P80 output pin 0 1 -- HA0 input pin* 23 PME input pin* * 2 1 1 0* 0* 1 PME output pin Notes: 1. When bit PMEE is set to 1 in HICR0, bits HI12E and P80DDR should be cleared to 0. 2. The HA0 input pin can only be used in mode 2 or 3 (EXPE = 0). 3. Not supported by the H8S/2148B and H8S/2145B (5-V version). 8.10 Port 9 Port 9 is an 8-bit I/O port. Port 9 pins also function as external interrupt input pins, the A/D converter input pin, host interface (XBS) input pins, the IIC_0 I/O pin, the subclock input pin, bus control signal I/O pins, and the system clock () output pin. P97 is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. Port 9 has the following registers. * Port 9 data direction register (P9DDR) * Port 9 data register (P9DR) Rev. 3.00 Mar 21, 2006 page 199 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.10.1 Port 9 Data Direction Register (P9DDR) P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial Value 0 1/0* 0 0 0 0 0 0 R/W W W W W W W W W Description P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2 and 3). Modes 1, 2, and 3 (EXPE = 1): Pin P97 functions as a bus control input (WAIT), the IIC_0 I/O pin (SDA0), or an I/O port, according to the wait mode setting. When P97 functions as an I/O port, it becomes an output port when P97DDR is set to 1, and an input port when P97DDR is cleared to 0. Pin P96 functions as the output pin when P96DDR is set to 1, and as the subclock input (EXCL) or an input port when P96DDR is cleared to 0. Pins P95 to P93 automatically become bus control outputs (AS/IOS, HWR, RD), regardless of the input/output direction indicated by P95DDR to P93DDR. Pins P92 and P91 become output ports when P92DDR and P91DDR are set to 1, and input ports when P92DDR and P91DDR are cleared to 0. When the ABW bit in WSCR is cleared to 0, pin P90 becomes a bus control output (LWR), regardless of the input/output direction indicated by P90DDR. When the ABW bit is 1, pin P90 becomes an output port if P90DDR is set to 1, and an input port if P90DDR is cleared to 0. Modes 2 and 3 (EXPE = 0): When the corresponding P9DDR bits are set to 1, pin P96 functions as the output pin and pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the corresponding pins become input ports. Note: * The initial value of P96DDR is 1 (mode 1) or 0 (modes 2 and 3). Rev. 3.00 Mar 21, 2006 page 200 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.10.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR * Initial Value 0 Undefined* 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W R/W Description With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR values are read directly, regardless of the actual pin states. If a port 9 read is performed while P9DDR bits are cleared to 0, the pin states are read. For P96, the pin state is always read. The initial value of bit 6 is determined according to the P96 pin state. 8.10.3 Pin Functions * P97/WAIT/SDA0 The pin function is switched as shown below according to the combination of operating mode, the WMS1 bit in WSCR, the ICE bit in ICCR of IIC_0, and the P97DDR bit. Operating Mode WMS1 ICE P97DDR Pin Function 0 0 1 Modes 1, 2, 3 (EXPE = 1) 0 1 -- 1 -- -- WAIT input pin 0 0 1 Modes 2, 3 (EXPE = 0) -- 1 -- P97 input P97 SDA0 I/O pin output pin pin P97 input P97 SDA0 I/O pin output pin pin Note: When this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. Rev. 3.00 Mar 21, 2006 page 201 of 788 REJ09B0300-0300 Section 8 I/O Ports * P96//EXCL The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P96DDR bit. P96DDR EXCLE Pin Function 0 P96 input pin 0 1 EXCL input pin 1 0 output pin Note: When this pin is used as the EXCL input pin, P96DDR should be cleared to 0. * P95/AS/IOS/CS1 The pin function is switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, the HI12E bit in SYSCR2, and the P95DDR bit. Operating Mode HI12E P95DDR IOSE Pin Function 0 AS output pin Modes 1, 2, 3 (EXPE = 1) -- -- 1 IOS output pin 0 -- P95 input pin Modes 2, 3 (EXPE = 0) 0 1 -- P95 output pin 1 -- -- CS1 input pin * P94/HWR/IOW The pin function is switched as shown below according to the combination of operating mode, the HI12E bit in SYSCR2, and the P94DDR bit. Operating Mode HI12E P94DDR Pin Function Modes 1, 2, 3 (EXPE = 1) -- -- HWR output pin 0 P94 input pin Modes 2, 3 (EXPE = 0) 0 1 P94 output pin 1 -- IOW input pin Rev. 3.00 Mar 21, 2006 page 202 of 788 REJ09B0300-0300 Section 8 I/O Ports * P93/RD/IOR The pin function is switched as shown below according to the combination of operating mode, the HI12E bit in SYSCR2, and the P93DDR bit. Operating Mode HI12E P93DDR Pin Function Modes 1, 2, 3 (EXPE = 1) -- -- RD output pin 0 P93 input pin Modes 2, 3 (EXPE = 0) 0 1 P93 output pin 1 -- IOR input pin * P92/IRQ0 P92DDR Pin Function Note: * 0 P92 input pin IRQ0 input pin* When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin. 1 P92 output pin * P91/IRQ1 P91DDR Pin Function Note: * 0 P91 input pin IRQ1 input pin* When bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin. 1 P91 output pin Rev. 3.00 Mar 21, 2006 page 203 of 788 REJ09B0300-0300 Section 8 I/O Ports * P90/LWR/IRQ2/ADTRG/ECS2 The pin function is switched as shown below according to the combination of operating mode, the ABW bit in WSCR, the HI12E and CS2E bits in SYSCR2, the FGA20E bit in HICR, and the P90DDR bit. Operating Mode ABW HI12E FGA20E CS2E P90DDR Pin Function -- LWR output pin 0 -- -- -- 0 P90 input pin 1 P90 output pin 0 P90 input pin 1 P90 output pin Modes 1, 2, 3 (EXPE = 1) 1 Any one 0 Modes 2, 3 (EXPE = 0) -- 1 1 1 -- ECS2 input pin IRQ2 input pin, ADTRG input pin* Note: * When the IRQ2E bit in IER is set to 1 in mode 1, 2, or 3 (EXPE = 1) with the ABW bit in WSCR set to 1, or in mode 2 and 3 (EXPE = 0), this pin is used as the IRQ2 input pin. When TRGS1 and TRGS0 in ADCR of the A/D converter are both set to 1, this pin is used as the ADTRG input pin. 8.11 Port A Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins, keysense interrupt input pins, expansion A/D converter input pins, and address output pins. Port A pin functions change according to the operating mode. Port A input/output operates by VccB power independent from the Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the following registers. PADDR and PAPIN have the same address. * Port A data direction register (PADDR) * Port A output data register (PAODR) * Port A input data register (PAPIN) Rev. 3.00 Mar 21, 2006 page 204 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.11.1 Port A Data Direction Register (PADDR) PADDR specifies input or output for the pins of port A on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In mode 1, 2 (EXPE = 0), or 3: The corresponding port A pins are output ports when PADDR bits are set to 1, and input ports when cleared to 0. In mode 2 (EXPE = 1): The corresponding port A pins are address output when PADDR bits are set to 1, and input ports when cleared to 0. The port A pins changes from the address I/O ports to output ports by setting the IOSE bit to 1. PA7 to PA2 pins are used as the keyboard buffer controller I/O pins by setting the KBIOE bit to 1 regardless of the operating mode, while the I/O direction according to PA7DDR to PA2DDR is ignored. PADDR has the same address as PAPIN, if read, port A status is returned. 8.11.2 Port A Output Data Register (PAODR) PAODR stores output data for port A. Bit 7 6 5 4 3 2 1 0 Bit Name PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PAODR can always be read or written to, regardless of the contents of PADDR. Rev. 3.00 Mar 21, 2006 page 205 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.11.3 Port A Input Data Register (PAPIN) PAPIN indicates the port A state. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description Reading PAPIN always returns the pin states. PAPIN has the same address as PADDR. If a write is performed, the port A settings will change. The initial value is determined according to the PA7 to PA0 pin states. 8.11.4 Pin Functions * PA7/A23/KIN15/CIN15/PS2CD The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_2 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA7DDR bit. Operating Mode KBIOE PA7DDR IOSE Pin Function 0 -- PA7 input pin Modes 1, 2 (EXPE = 0), 3 0 1 -- 1 -- -- 0 -- PA7 input pin 0 Mode 2 (EXPE = 1) 0 1 1 1 -- -- PA7 PS2CD output pin output pin A23 PA7 PS2CD output pin output pin output pin KIN15 input pin, CIN15 input pin, PS2CD input pin* Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2CD, KIN15, or CIN15 input pin. Rev. 3.00 Mar 21, 2006 page 206 of 788 REJ09B0300-0300 Section 8 I/O Ports * PA6/A22/KIN14/CIN14/PS2CC The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_2 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA6DDR bit. Operating Mode KBIOE PA6DDR IOSE Pin Function 0 -- PA6 input pin Modes 1, 2 (EXPE = 0), 3 0 1 -- 1 -- -- 0 -- PA6 input pin 0 Mode 2 (EXPE = 1) 0 1 1 1 -- -- PA6 PS2CC output pin output pin A22 PA6 PS2CC output pin output pin output pin KIN14 input pin, CIN14 input pin, PS2CC input pin* Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2CC, KIN14, or CIN14 input pin. * PA5/A21/KIN13/CIN13/PS2BD The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_1 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA5DDR bit. Operating Mode KBIOE PA5DDR IOSE Pin Function 0 -- PA5 input pin Modes 1, 2 (EXPE = 0), 3 0 1 -- 1 -- -- 0 -- PA5 input pin 0 Mode 2 (EXPE = 1) 0 1 1 1 -- -- PA5 PS2BD output pin output pin A21 PA5 PS2BD output pin output pin output pin KIN13 input pin, CIN13 input pin, PS2BD input pin* Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2BD, KIN13, or CIN13 input pin. Rev. 3.00 Mar 21, 2006 page 207 of 788 REJ09B0300-0300 Section 8 I/O Ports * PA4/A20/KIN12/CIN12/PS2BC The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_1 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA4DDR bit. Operating Mode KBIOE PA4DDR IOSE Pin Function 0 -- PA4 input pin Modes 1, 2 (EXPE = 0), 3 0 1 -- 1 -- -- 0 -- PA4 input pin 0 Mode 2 (EXPE = 1) 0 1 1 1 -- -- PA4 PS2BC output pin output pin A20 PA4 PS2BC output pin output pin output pin KIN12 input pin, CIN12 input pin, PS2BC input pin* Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2BC, KIN12, or CIN12 input pin. * PA3/A19/KIN11/CIN11/PS2AD The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_0 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA3DDR bit. Operating Mode KBIOE PA3DDR IOSE Pin Function 0 -- PA3 input pin Modes 1, 2 (EXPE = 0), 3 0 1 -- 1 -- -- 0 -- PA3 input pin 0 Mode 2 (EXPE = 1) 0 1 1 1 -- -- PA3 PS2AD output pin output pin A19 PA3 PS2AD output pin output pin output pin KIN11 input pin, CIN11 input pin, PS2AD input pin* Note: * When the KBIOE bit is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2AD, KIN11, or CIN11 input pin. Rev. 3.00 Mar 21, 2006 page 208 of 788 REJ09B0300-0300 Section 8 I/O Ports * PA2/A18/KIN10/CIN10/PS2AC The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_0 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA2DDR bit. Operating Mode KBIOE PA2DDR IOSE Pin Function 0 -- PA2 input pin Modes 1, 2 (EXPE = 0), 3 0 1 -- 1 -- -- 0 -- PA2 input pin 0 Mode 2 (EXPE = 1) 0 1 1 1 -- -- PA2 PS2AC output pin output pin A18 PA2 PS2AC output pin output pin output pin KIN10 input pin, CIN10 input pin, PS2AC input pin* Note: * When the KBIOE bit is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2AC, KIN10, or CIN10 input pin. * PA1/A17/KIN9/CIN9 The pin function is switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR and the PA1DDR bit. Operating Mode PA1DDR IOSE Pin Function Modes 1, 2 (EXPE = 0), 3 0 -- PA1 input pin 1 -- PA1 output pin 0 -- PA1 input pin 0 Mode 2 (EXPE = 1) 1 1 PA1 output pin A17 output pin KIN9 input pin, CIN9 input pin* Note: * This pin can always be used as the KIN9 or CIN9 input pin. Rev. 3.00 Mar 21, 2006 page 209 of 788 REJ09B0300-0300 Section 8 I/O Ports * PA0/A16/ KIN8/CIN8 The pin function is switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR and the PA0DDR bit. Operating Mode PA0DDR IOSE Pin Function Modes 1, 2 (EXPE = 0), 3 0 -- PA0 input pin 1 -- PA0 output pin 0 -- PA0 input pin 0 Mode 2 (EXPE = 1) 1 1 PA0 output pin A16 output pin KIN8 input pin, CIN8 input pin* Note: * This pin can always be used as the KIN8 or CIN8 input pin. 8.11.5 Port A Input Pull-Up MOS Port A has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. The input pull-up MOS for pins PA7 to PA4 is always off when IICS is set to 1. When the keyboard buffer control pin function is selected for pins PA7 to PA2, the input pull-up MOS is always off. Table 8.6 summarizes the input pull-up MOS states. Table 8.6 Mode 1 to 3 Input Pull-Up MOS States (Port A) Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, PADDR = 0, and PAODR = 1; otherwise off. Rev. 3.00 Mar 21, 2006 page 210 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.12 Port B Port B is an 8-bit I/O port. Port B pins also have XBS input/output pins, LPC input/output pins, wakeup event interrupt input pins, and a data bus input/output function. The pin functions depend on the operating mode. Port B has the following registers. * Port B data direction register (PBDDR) * Port B output data register (PBODR) * Port B input data register (PBPIN) 8.12.1 Port B Data Direction Register (PBDDR) PBDDR specifies input or output for the pins of port B on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description PBDDR has the same address as P7PIN, and if read, the port 7 pin states will be returned. * Modes 1, 2, and 3 (EXPE = 1) When the ABW bit in WSCR is cleared to 0, port B pins automatically become data I/O pins (D7 to D0), regardless of the input/output direction indicated by PBDDR. When the ABW bit is 1, a port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0. * Modes 2 and 3 (EXPE = 0) A port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0. Rev. 3.00 Mar 21, 2006 page 211 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.12.2 Port B Output Data Register (PBODR) PBODR stores output data for port B. Bit 7 6 5 4 3 2 1 0 Bit Name PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PBODR can always be read or written to, regardless of the contents of PBDDR. 8.12.3 Port B Input Data Register (PBPIN) PBPIN indicates the port B state. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description Reading PBPIN always returns the pin states. PBPIN has the same address as P8DDR. If a write is performed, data will be written to P8DDR and the port 8 settings will change. The initial value is determined according to the PB7 to PB0 pin states. Rev. 3.00 Mar 21, 2006 page 212 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.12.4 Pin Functions 2 2 2 2 * PB7/D7/WUE7* , PB6/D6/WUE6* , PB5/D5/WUE5* , PB4/D4/WUE4* The pin function is switched as shown below according to the combination of the operating mode, the PBnDDR bit, and the ABW bit in WSCR. Operating Mode ABW PBnDDR Pin Function Mode 1 and Modes 2, 3 (EXPE = 1) 0 -- Dn I/O pin 0 PBn input pin 1 1 PBn output pin 0 PBn input pin 1 WUEn input pin* Modes 2, 3 (EXPE = 0) -- 1 PBn output pin Notes: 1. Except when used as a data bus pin, this pin can always be used as the WUEn input pin. (n = 7 to 4) 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 2 * PB3/D3/WUE3* /CS4 The pin function is switched as shown below according to the combination of the operating mode, the HI12E and CS4E bits in SYSCR2, the ABW bit in WSCR, and the PB3DDR bit. Operating Mode HI12E CS4E ABW PB3DDR Pin Function 0 -- D3 I/O pin 0 PB3 input pin Mode 1 and Modes 2, 3 (EXPE = 1) -- -- 1 1 PB3 output pin 0 PB3 input pin WUE3 input pin* 1 Modes 2, 3 (EXPE = 0) Either cleared to 0 1 1 -- 1 PB3 output pin -- -- CS4 input pin Notes: 1. Except when used as a data bus pin, this pin can always be used as the WUE3 input pin. The CS4 input pin can only be used in mode 2 or 3 (EXPE = 0). 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 2 * PB2/D2/WUE2* /CS3 The pin function is switched as shown below according to the combination of the operating mode, the HI12E and CS3E bits in SYSCR2, the ABW bit in WSCR, and the PB2DDR bit. Rev. 3.00 Mar 21, 2006 page 213 of 788 REJ09B0300-0300 Section 8 I/O Ports Operating Mode HI12E CS3E ABW PB2DDR Pin Function 0 -- D2 I/O pin 0 PB2 input pin Mode 1 and Modes 2, 3 (EXPE = 1) -- -- 1 1 PB2 output pin 0 PB2 input pin WUE2 input pin* 1 Modes 2, 3 (EXPE = 0) Either cleared to 0 1 1 -- 1 PB2 output pin -- -- CS3 input pin Notes: 1. Except when used as a data bus pin, this pin can always be used as the WUE2 input pin. The CS3 input pin can only be used in mode 2 or 3 (EXPE = 0). 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). * PB1/D1/WUE1/HIRQ4/LSCI* 4 The pin function is switched as shown below according to the combination of the operating mode, the HI12E and CS4E bits in SYSCR2, the LSCIE bits in HICR0 of host interface (LPC), the ABW bit in WSCR, and the PB1DDR bit. Operating Mode LSCIE HI12E CS4E ABW PB1DDR Pin Function 0 -- D1 I/O pin 0 PB1 input pin Modes 1, 2, 3 (EXPE = 1) 0* 3 Mode 2, 3 (EXPE = 0) 0 Either cleared to 0 1 1 1 1 0* -- -- 0* 1 4 -- -- 1 1 PB1 output pin -- 0 PB1 input pin 1 PB1 output pin -- -- HIRQ4 output pin 2 LSCI* output pin LSCI input pin* 24 WUE1 input pin* * Notes: 1. When bit LSCIE is set to 1 in HICR0, bits HI12E and PB1DDR should be cleared to 0. 2. Except when used as a data bus pin, this pin can always be used as the WUE1 input pin. The HIRQ4 output pin and LSCI I/O pin can only be used in mode 2 or 3 (EXPE = 0). 3. In mode 1, 2, 3 (EXPE = 1), clear the LSCIE bit to 0. 4. Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page 214 of 788 REJ09B0300-0300 Section 8 I/O Ports * PB0/D0/WUE0/HIRQ3/LSMI* 4 The pin function is switched as shown below according to the combination of the operating mode, the HI12E and CS3E bits in SYSCR2, the LSMIE bits in HICR0 of host interface (LPC), the ABW bit in WSCR, and the PB0DDR bit. Operating Mode LSMIE HI12E CS3E ABW PB0DDR Pin Function 0 -- D0 I/O pin 0 PB0 input pin Modes 1, 2, 3 (EXPE = 1) 0* 3 Mode 2, 3 (EXPE = 0) 0 Either cleared to 0 1 1 1 1 0* -- -- 0* 1 4 -- -- 1 1 PB0 output pin -- 0 PB0 input pin 1 PB0 output pin -- -- HIRQ3 output pin 2 LSMI* output pin LSMI input pin* 2 WUE0 input pin* Notes: 1. When bit LSMIE is set to 1 in HICR0, bits HI12E and PB0DDR should be cleared to 0. 2. Except when used as a data bus pin, this pin can always be used as the WUE0 input pin. The HIRQ3 output pin and LSMI I/O pin can only be used in mode 2 or 3 (EXPE = 0). 3. In mode 1, 2, 3 (EXPE = 1), clear the LSMIE bit to 0. 4. Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page 215 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.12.5 Port B Input Pull-Up MOS Port B has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is always off. Table 8.7 summarizes the input pull-up MOS states. Table 8.7 Mode 1, 2, 3 (EXPE = 1) with ABW in WSCR = 0 1, 2, 3 (EXPE = 1) with ABW in WSCR = 1, or 2, 3 (EXPE = 0) Input Pull-Up MOS States (Port B) Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, PBDDR = 0, and PBODR = 1; otherwise off. 8.13 Additional Overview for H8S/2160B and H8S/2161B The H8S/2160B and H8S/2161B has fifteen I/O ports (ports 1 to 6, 8, 9, A to G), and one inputonly port (port 7). Table 8.8 is a summary of the additional port functions. As the functions of ports 1 to 9, A, and B are the same on the H8S/2140B, H8S/2141B, H8S/2148B, and H8S/2145B, table 8.1 provides a summary. Each extra port includes a data direction register (DDR) that controls input/output, and data registers (ODR) for storing output data. Ports C to E, and F have an on-chip input pull-up MOS function. On ports C to F, whether the input pull-up MOS is on or off is controlled by the corresponding DDR and ODR. Ports C to F, and G can drive a single-TTL load and 30-pF-capacitive load. All I/O port pins are capable of driving a Darlington transistor when they are in output. Rev. 3.00 Mar 21, 2006 page 216 of 788 REJ09B0300-0300 Section 8 I/O Ports The output type on port G is NMOS push-pull output. Port G can be 5-V tolerant. When port G is used as an output pin, connect a pull-up resistor to the pin for raise an output highlevel voltage. Table 8.8 Port Port C Port D Port E Port F Port G H8S/2160B, H8S/2161B Additional Port Functions Description 8-bit I/O port 8-bit I/O port 8-bit I/O port 8-bit I/O port 8-bit I/O port Mode 1 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 PG7 to PG0 Mode 2, 3 (EXPE = 1) (EXPE = 0) I/O Status On-chip input pull-up MOSs On-chip input pull-up MOSs On-chip input pull-up MOSs On-chip input pull-up MOSs 8.14 Ports C, D Port C and port D are two sets of 8-bit I/O ports. The pin functions are the same in all operating modes. * Port C data direction register (PCDDR) * Port C output data register (PCODR) * Port C input data register (PCPIN) * Port C Nch-OD control register (PCNOCR) * Port D data direction register (PDDDR) * Port D output data register (PDODR) * Port D input data register (PDPIN) * Port D Nch-OD control register (PDNOCR) Rev. 3.00 Mar 21, 2006 page 217 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.14.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR) PCDDR and PDDDR select input or output for the pins of port C and port D on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description 0: Port C pin is an input pin 1: Port C pin is an output pin PCDDR has the same address as PCPIN, and if read, the port C pin states will be returned. Bit 7 6 5 4 3 2 1 0 Bit Name PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description 0: Port D pin is an input pin 1: Port D pin is an output pin PDDDR has the same address as PDPIN, and if read, the port D pin states will be returned. Rev. 3.00 Mar 21, 2006 page 218 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.14.2 Port C and Port D Output Data Registers (PCODR, PDODR) PCODR and PDODR store output data for the pins on ports C and D. Bit 7 6 5 4 3 2 1 0 Bit Name PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PCODR can always be read or written to, regardless of the contents of PCDDR. Bit 7 6 5 4 3 2 1 0 Bit Name PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PDODR can always be read or written to, regardless of the contents of PDDDR. Rev. 3.00 Mar 21, 2006 page 219 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.14.3 Port C and Port D Input Data Registers (PCPIN, PDPIN) Reading PCPIN and PDPIN always returns the pin states. Bit 7 6 5 4 3 2 1 0 Note: Bit 7 6 5 4 3 2 1 0 Note: Bit Name PC7PIN PC6PIN PC5PIN PC4PIN PC3PIN PC2PIN PC1PIN PC0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description PCPIN indicates the port C state. PCPIN has the same address as PCDDR. If a write is performed, the port C settings will change. The initial value is determined according to the PC7 to PC0 pin states. Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description PDPIN indicates the port D state. PDPIN has the same address as PDDDR. If a write is performed, the port D settings will change. Bit Name PD7PIN PD6PIN PD5PIN PD4PIN PD3PIN PD2PIN PD1PIN PD0PIN * The initial value is determined according to the PD7 to PD0 pin states. Rev. 3.00 Mar 21, 2006 page 220 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.14.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR) PCNOCR and PDNOCR specify the output driver type for pins on ports C and D which are configured as outputs on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PC7NOCR PC6NOCR PC5NOCR PC4NOCR PC3NOCR PC2NOCR PC1NOCR PC0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: CMOS (p-channel driver enabled) 1: N-channel open drain (p-channel driver disabled) Bit 7 6 5 4 3 2 1 0 Bit Name PD7NOCR PD6NOCR PD5NOCR PD4NOCR PD3NOCR PD2NOCR PD1NOCR PD0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: CMOS (p-channel driver enabled) 1: N-channel open drain (p-channel driver disabled) 8.14.5 DDR NOCR ODR Pin Functions 0 -- 0 OFF OFF OFF Input pin ON 1 0 ON OFF 0 1 OFF ON OFF Output pin 0 ON OFF 1 1 1 OFF N-ch. driver P-ch. driver Input pull-up MOS Pin function Rev. 3.00 Mar 21, 2006 page 221 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.14.6 Input Pull-Up MOS in Ports C and D Port C and port D have an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be switched on or off on a bit-by-bit basis. Table 8.9 is a summary of the input pull-up MOS states. Table 8.9 Mode 1 to 3 Input Pull-Up MOS States (Port C and port D) Reset Off Hardware Standby Mode Off Software Standby Mode On/Off Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when PCDDR = 0 and PCODR = 1 (PDDDR = 0 and PDODR = 1); otherwise off. 8.15 Ports E, F Port E and port F are two sets of 8-bit I/O ports. The pins of ports E and F have the same functions in all operating modes. * Port E data direction register (PEDDR) * Port E output data register (PEODR) * Port E input data register (PEPIN) * Port E Nch-OD control register (PENOCR) * Port F data direction register (PFDDR) * Port F output data register (PFODR) * Port F input data register (PFPIN) * Port F Nch-OD control register (PFNOCR) Rev. 3.00 Mar 21, 2006 page 222 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.15.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) PEDDR and PFDDR select input or output for the pins of port E and port F on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description 0: Port E pin is an input pin 1: Port E pin is an output pin PEDDR has the same address as PEPIN, and if read, the port E pin states will be returned. Bit 7 6 5 4 3 2 1 0 Bit Name PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description 0: Port F pin is an input pin 1: Port F pin is an output pin PFDDR has the same address as PFPIN, and if read, the port F pin states will be returned. Rev. 3.00 Mar 21, 2006 page 223 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.15.2 Port E and Port F Output Data Registers (PEODR, PFODR) PEODR and PFODR store output data for the pins on ports E and F. Bit 7 6 5 4 3 2 1 0 Bit Name PE7ODR PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PEODR can always be read or written to, regardless of the contents of PEDDR. Bit 7 6 5 4 3 2 1 0 Bit Name PF7ODR PF6ODR PF5ODR PF4ODR PF3ODR PF2ODR PF1ODR PF0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PFODR can always be read or written to, regardless of the contents of PFDDR. Rev. 3.00 Mar 21, 2006 page 224 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.15.3 Port E and Port F Input Data Registers (PEPIN, PFPIN) Reading PEPIN and PFPIN always returns the pin states. Bit 7 6 5 4 3 2 1 0 Note: Bit 7 6 5 4 3 2 1 0 Note: Bit Name PE7PIN PE6PIN PE5PIN PE4PIN PE3PIN PE2PIN PE1PIN PE0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description PEPIN indicates the port E state. PEPIN has the same address as PEDDR. If a write is performed, the port E settings will change. The initial value is determined according to the PE7 to PE0 pin states. Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description PFPIN indicates the port F state. PFPIN has the same address as PFDDR. If a write is performed, the port F settings will change. Bit Name PF7PIN PF6PIN PF5PIN PF4PIN PF3PIN PF2PIN PF1PIN PF0PIN * The initial value is determined according to the PF7 to PF0 pin states. Rev. 3.00 Mar 21, 2006 page 225 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.15.4 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR) PENOCR and PFNOCR specify the output driver type for pins on ports E and F which are configured as outputs on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PE7NOCR PE6NOCR PE5NOCR PE4NOCR PE3NOCR PE2NOCR PE1NOCR PE0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: CMOS (p-channel driver enabled) 1: N-channel open drain (p-channel driver disabled) Bit 7 6 5 4 3 2 1 0 Bit Name PF7NOCR PF6NOCR PF5NOCR PF4NOCR PF3NOCR PF2NOCR PF1NOCR PF0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: CMOS (p-channel driver enabled) 1: N-channel open drain (p-channel driver disabled) 8.15.5 DDR NOCR ODR Pin Functions 0 -- 0 OFF OFF OFF Input pin ON 1 0 ON OFF 0 1 OFF ON OFF Output pin 0 ON OFF 1 1 1 OFF N-ch. driver P-ch. driver Input pull-up MOS Pin function Rev. 3.00 Mar 21, 2006 page 226 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.15.6 Input Pull-Up MOS in Ports E and F Port E and port F have an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be switched on or off on a bit-by-bit basis. Table 8.10 is a summary of the input pull-up MOS states. Table 8.10 Input Pull-Up MOS States (Port E and port F) Mode 1 to 3 Reset Off Hardware Standby Mode Off Software Standby Mode On/Off Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when PEDDR = 0 and PEODR = 1 (PFDDR = 0 and PFODR = 1); otherwise off. 8.16 Port G Port G is an 8-bit I/O port. Port G pin functions are the same in all operating modes. The output type of port G is NMOS open-drain. * Port G data direction register (PGDDR) * Port G output data register (PGODR) * Port G input data register (PGPIN) * Port G Nch-OD control register (PGNOCR) Rev. 3.00 Mar 21, 2006 page 227 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.16.1 Port G Data Direction Register (PGDDR) PGDDR selects input or output for the pins of port G on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PG7DDR PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description 0: Port G pin is an input pin 1: Port G pin is an output pin PGDDR has the same address as PGPIN, and if read, the port G pin states will be returned. 8.16.2 Port G Output Data Register (PGODR) PGODR stores output data for the pins on port G. Bit 7 6 5 4 3 2 1 0 Bit Name PG7ODR PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PGODR can always be read or written to, regardless of the contents of PGDDR. Rev. 3.00 Mar 21, 2006 page 228 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.16.3 Port G Input Data Register (PGPIN) Reading PGPIN always returns the pin states. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PG7PIN PG6PIN PG5PIN PG4PIN PG3PIN PG2PIN PG1PIN PG0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description PGPIN indicates the port G state. PGPIN has the same address as PGDDR. If a write is performed, the port G settings will change. The initial value is determined according to the PG7 to PG0 pin states. 8.16.4 Port G Nch-OD Control Register (PGNOCR) PGNOCR specifies the output driver type for pins on port G which are configured as outputs on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PG7NOCR PG6NOCR PG5NOCR PG4NOCR PG3NOCR PG2NOCR PG1NOCR PG0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: NMOS push-pull (Vcc-side n-channel driver enabled) 1: Vss-side N-channel open drain (Vcc-side Nchannel driver disabled) Rev. 3.00 Mar 21, 2006 page 229 of 788 REJ09B0300-0300 Section 8 I/O Ports 8.16.5 DDR NOCR ODR Pin Functions 0 -- 0 OFF OFF Input pin 1 0 ON OFF 0 1 OFF ON Output pin 0 ON OFF 1 1 1 OFF Vss-side N-ch. driver Vcc-side N-ch. driver Pin function Rev. 3.00 Mar 21, 2006 page 230 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) Section 9 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. 9.1 Features * Operable at a maximum carrier frequency of 625 kHz using pulse division (at 10 MHz operation) * Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) * Direct or inverted PWM output, and PWM output enable/disable control PWM0800A_010020020700 Rev. 3.00 Mar 21, 2006 page 231 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) Figure 9.1 shows a block diagram of the PWM timer. P10/PW0 P11/PW1 P12/PW2 P13/PW3 P14/PW4 P15/PW5 P16/PW6 P17/PW7 P20/PW8 P21/PW9 P22/PW10 P23/PW11 P24/PW12 P25/PW13 P26/PW14 P27/PW15 Port/PWM output control Comparator 0 Comparator 1 Comparator 2 Comparator 3 Comparator 4 Comparator 5 Comparator 6 Comparator 7 Comparator 8 Comparator 9 Comparator 10 Comparator 11 Comparator 12 Comparator 13 Comparator 14 Comparator 15 PWDR0 PWDR1 PWDR2 PWDR3 PWDR4 PWDR5 Module data bus Bus interface PWDR6 PWDR7 PWDR8 PWDR9 PWDR10 PWDR11 PWDR12 PWDR13 PWDR14 PWDR15 Internal data bus PWDPRB PWOERB P2DDR P2DR Legend: PWSL PWDR PWDPRA PWDPRB PWOERA PWOERB PCSR P1DDR P2DDR P1DR P2DR PWDPRA PWOERA P1DDR P1DR TCNT Select clock PWSL PCSR : PWM register select : PWM data register : PWM data polarity register A : PWM data polarity register B : PWM output enable register A : PWM output enable register B : Peripheral clock select register : Port 1 data direction register : Port 2 data direction register : Port 1 data register : Port 2 data register /2 /4 /8 /16 Internal clock Figure 9.1 Block Diagram of PWM Timer Rev. 3.00 Mar 21, 2006 page 232 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) 9.2 Input/Output Pin Table 9.1 shows the PWM output pins. Table 9.1 Name PWM output 15 to 0 Pin Configuration Abbreviation PW15 to PW0 I/O Output Function PWM timer pulse output 15 to 0 9.3 Register Descriptions The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR). * PWM register select (PWSL) * PWM data registers 0 to 15 (PWDR0 to PWDR15) * PWM data polarity register A (PWDPRA) * PWM data polarity register B (PWDPRB) * PWM output enable register A (PWOERA) * PWM output enable register B (PWOERB) * Peripheral clock select register (PCSR) Rev. 3.00 Mar 21, 2006 page 233 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) 9.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit 7 6 Bit Name PWCKE PWCKS Initial Value 0 0 R/W R/W R/W Description PWM Clock Enable PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM. For details, see table 9.2. The resolution, PWM conversion period, and carrier frequency depend on the selected internal clock, and can be obtained from the following equations. Resolution (minimum pulse width) = 1/internal clock frequency PWM conversion period = resolution x 256 Carrier frequency = 16/PWM conversion period With a 10 MHz system clock (), the resolution, PWM conversion period, and carrier frequency are as shown in table 9.3. 5 4 -- -- 1 0 R R Reserved This bit is always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 234 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) Bit 3 2 1 0 Bit Name RS3 RS2 RS1 RS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Register Select These bits select the PWM data register. 0000: PWDR0 selected 0001: PWDR1 selected 0010: PWDR2 selected 0011: PWDR3 selected 0100: PWDR4 selected 0101: PWDR5 selected 0110: PWDR6 selected 0111: PWDR7 selected 1000: PWDR8 selected 1001: PWDR9 selected 1010: PWDR10 selected 1011: PWDR11 selected 1100: PWDR12 selected 1101: PWDR13 selected 1110: PWDR14 selected 1111: PWDR15 selected Table 9.2 Internal Clock Selection PCSR PWCKB -- -- 0 PWCKA -- -- 0 1 1 0 1 Description Clock input is disabled (system clock) is selected /2 is selected /4 is selected /8 is selected /16 is selected (Initial value) PWSL PWCKE 0 1 PWCKS -- 0 1 Rev. 3.00 Mar 21, 2006 page 235 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) Table 9.3 Resolution, PWM Conversion Period and Carrier Frequency when = 10 MHz Resolution 100 ns 200 ns 400 ns 800 ns 1600 ns PWM Conversion Period 25.6 s 51.2 s 102.4 s 204.8 s 409.6 s Carrier Frequency 625 kHz 312.5 kHz 156.3 kHz 78.1 kHz 39.1 kHz Internal Clock Frequency /2 /4 /8 /16 9.3.2 PWM Data Registers (PWDR0 to PWDR15) PWDR are 8-bit readable/writable registers. The PWM has sixteen PWM data registers. Each PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The lower four bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output should be used. PWDR0 to PWDR15 are initialized to H'00. 9.3.3 PWM Data Polarity Registers A and B (PWDPRA, PWDPRB) Each PWDPR selects the PWM output phase. * PWDPRA Bit 7 6 5 4 3 2 1 0 Bit Name OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Select 7 to 0 These bits select the PWM output phase. Bits OS7 to OS0 correspond to outputs PW7 to PW0. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output) Rev. 3.00 Mar 21, 2006 page 236 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) * PWDPRB Bit 7 6 5 4 3 2 1 0 Bit Name OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Select 15 to 8 These bits select the PWM output phase. Bits OS15 to OS8 correspond to outputs PW15 to PW8. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output) 9.3.4 PWM Output Enable Registers A and B (PWOERA, PWOERB) Each PWOER switches between PWM output and port output. * PWOERA Bit 7 6 5 4 3 2 1 0 Bit Name OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Enable 7 to 0 These bits, together with P1DDR, specify the P1n/PWn pin state. Bits OE7 to OE0 correspond to outputs PW7 to PW0. P1nDDR OEn: Pin state 0X: Port input 10: Port output or PWM 256/256 output 11: PWM output (0 to 255/256 output) Legend: X: Don't care Rev. 3.00 Mar 21, 2006 page 237 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) * PWOERB Bit 7 6 5 4 3 2 1 0 Bit Name OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Enable 15 to 8 These bits, together with P2DDR, specify the P2n/PWn pin state. Bits OE15 to OE8 correspond to outputs PW15 to PW8. P2nDDR OEn: Pin state 0X: Port input 10: Port output or PWM 256/256 output 11: PWM output (0 to 255/256 output) Legend: X: Don't care To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set to port output. The corresponding pin can be set as port output in single-chip mode or when IOSE = 1 and CS256E = 0 in SYSCR in extended mode with on-chip ROM. Otherwise, it should be noted that an address bus is output to the corresponding pin. DR data is output when the corresponding pin is used as port output. A value corresponding to PWM 256/256 output is determined by the OS bit, so the value should have been set to DR beforehand. 9.3.5 Peripheral Clock Select Register (PCSR) PCSR selects the PWM input clock. Bit 3 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0. The initial value should not be changed. 2 1 PWCKB PWCKA 0 0 R/W R/W PWM Clock Select B, A Together with bits PWCKE and PWCKS in PWSL, these bits select the internal clock input to TCNT in the PWM. For details, see table 9.2. Reserved This bit is always read as 0. The initial value should not be changed. 0 -- 0 R Rev. 3.00 Mar 21, 2006 page 238 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) 9.4 Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 9.4 shows the duty cycles of the basic pulse. Table 9.4 Upper 4 Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Duty Cycle of Basic Pulse Basic Pulse Waveform (Internal) 0123456789ABCDEF0 The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse. When the upper four bits of PWDR are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 9.5 shows the positions of Rev. 3.00 Mar 21, 2006 page 239 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) the additional pulses added to the basic pulses, and figure 9.2 shows an example of additional pulse timing. Table 9.5 Lower 4 Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Position of Pulses Added to Basic Pulses Basic Pulse No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No additional pulse Resolution width With additional pulse Basic pulse Figure 9.2 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000) Rev. 3.00 Mar 21, 2006 page 240 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) 9.5 9.5.1 Usage Note Module Stop Mode Setting PWM operation can be enabled or disabled using the module stop control register. The initial setting is for PWM operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 241 of 788 REJ09B0300-0300 Section 9 8-Bit PWM Timer (PWM) Rev. 3.00 Mar 21, 2006 page 242 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) Section 10 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 10.1 Features * Division of pulse into multiple base cycles to reduce ripple * Two resolution settings The resolution can be set equal to one or two system clock cycles. * Two base cycle settings The base cycle can be set equal to T x 64 or T x 256, where T is the resolution. * Four operating speeds * Four operation clocks (by combination of two resolution settings and two base cycle settings) Figure 10.1 shows a block diagram of the PWM (D/A) module. Internal clock /2 Select clock Clock Base cycle compare match A PWX0 PWX1 Fine-adjustment pulse addition Internal data bus Bus interface Comparator A Comparator B DADRA DADRB Base cycle compare match B Fine-adjustment pulse addition Control logic Base cycle overflow DACNT DACR Module data bus Legend: DACR : PWM D/A control register DADRA : PWM D/A data register A DADRB : PWM D/A data register B DACNT : PWM D/A counter Figure 10.1 PWM (D/A) Block Diagram PWM1411A_010020020700 Rev. 3.00 Mar 21, 2006 page 243 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) 10.2 Input/Output Pins Table 10.1 lists the PWM (D/A) module input and output pins. Table 10.1 Pin Configuration Name PWM output pin X0 PWM output pin X1 Abbreviation PWX0 PWX1 I/O Output Output Function PWM output of PWMX channel A PWM output of PWMX channel B 10.3 Register Descriptions The PWM (D/A) module has the following registers. The PWM (D/A) registers are assigned to the same addresses with other registers. The registers are selected by the IICE bit in the serial timer control register (STCR). For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * PWM (D/A) counter H (DACNTH) * PWM (D/A) counter L (DACNTL) * PWM (D/A) data register AH (DADRAH) * PWM (D/A) data register AL (DADRAL) * PWM (D/A) data register BH (DADRBH) * PWM (D/A) data register BL (DADRBL) * PWM (D/A) control register (DACR) Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB. Rev. 3.00 Mar 21, 2006 page 244 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) 10.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. Since DACNT consists of 16-bit data, DACNT transfers data to the CPU via the temporary register (TEMP). For details, refer to section 10.4, Bus Master Interface. DACNTH Bit (CPU) Bit (Counter) : : 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 7 8 6 9 5 10 DACNTL 4 11 3 12 2 13 1 -- -- 0 -- REGS * DACNTH Bit 7 to 0 Bit Name UC7 to UC0 Initial Value All 0 R/W R/W Description Upper Up-Counter * DACNTL Bit 7 to 2 1 0 Bit Name UC8 to UC13 -- REGS Initial Value All 0 R/W R/W Description Lower Up-Counter 1 1 R R/W Reserved This bit is always read as 1 and cannot be modified. Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed Rev. 3.00 Mar 21, 2006 page 245 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) 10.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB) DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. Since DADR consists of 16-bit data, DADR transfers data to the CPU via the temporary register (TEMP). For details, refer to section 10.4, Bus Master Interface. * DADRA Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA1 and DA0) cleared to 0. The two lowest data bits correspond to the two highest bits in DACNT. Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DADR range = H'0401 to H'FFFD 1: Base cycle = resolution (T) x 256 DADR range = H'0103 to H'FFFF 0 -- 1 R Reserved This bit is always read as 1 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 246 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) * DADRB Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA1 and DA0) cleared to 0. The two lowest data bits correspond to the two highest bits in DACNT. Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DADR range = H'0401 to H'FFFD 1: Base cycle = resolution (T) x 256 DADR range = H'0103 to H'FFFF 0 REGS 1 R/W Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed Rev. 3.00 Mar 21, 2006 page 247 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) 10.3.3 PWM (D/A) Control Register (DACR) DACR selects test mode, enables the PWM outputs, and selects the output phase and operating speed. Bit 7 Bit Name TEST Initial Value 0 R/W R/W Description Test Mode Selects test mode, which is used in testing this LSI. Normally this bit should be cleared to 0. 0: PWM (D/A) in user state: Normal operation 1: PWM (D/A) in test state: Correct conversion results unobtainable 6 PWME 0 R/W PWM Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5, 4 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. 3 OEB 0 R/W Output Enable B Enables or disables output on PWM (D/A) channel B. 0: PWM (D/A) channel B output (at the PWX1 pin) is disabled 1: PWM (D/A) channel B output (at the PWX1 pin) is enabled Rev. 3.00 Mar 21, 2006 page 248 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) Bit 2 Bit Name OEA Initial Value 0 R/W R/W Description Output Enable A Enables or disables output on PWM (D/A) channel A. 0: PWM (D/A) channel A output (at the PWX0 pin) is disabled 1: PWM (D/A) channel A output (at the PWX0 pin) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWM (D/A) output. 0: Direct PWM (D/A) output 1: Inverted PWM (D/A) output 0 CKS 0 R/W Clock Select Selects the PWM (D/A) resolution. If the system clock () frequency is 10 MHz, resolutions of 100 ns and 200 ns, can be selected. 0: Operates at resolution (T) = system clock cycle time (tcyc) 1: Operates at resolution (T) = system clock cycle time (tcyc) x 2 Rev. 3.00 Mar 21, 2006 page 249 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) 10.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. Write: When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the lower byte is written to, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. Read: When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lower-byte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Example 1: Write to DACNT MOV.W R0, @DACNT ; Write R0 contents to DACNT Example 2: Read DADRA MOV.W @DADRA, R0 ; Copy contents of DADRA to R0 Table 10.2 Read and Write Access Methods for 16-Bit Registers Read Register Name DADRA and DADRB DACNT Word Yes Yes Byte Yes x Word Yes Yes Write Byte x x Legend: Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte (first) and lower byte (second). x: This type of access may give incorrect results. Rev. 3.00 Mar 21, 2006 page 250 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) 10.5 Operation A PWM waveform like the one shown in figure 10.2 is output from the PWMX pin. The value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 10.3 and 10.4 show the types of waveform output available. 1 conversion cycle (T x 214 (= 16384)) tf Base cycle (T x 64 or T x 256) tL Notes: T: Resolution TL = tLn (OS = 0) n=1 m (When CFS = 0, m = 256 When CFS = 1, m = 64) Figure 10.2 PWM D/A Operation Rev. 3.00 Mar 21, 2006 page 251 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) Table 10.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR contains at least a certain minimum value. Table 10.3 Settings and Operation (Examples when = 10 MHz) CKS 0 Resolution Base Conversion T CFS Cycle Cycle (s) (s) (s) 0.1 0 6.4 1638.4 Fixed DADR Bits TL (if OS = 0) TH (if OS = 1) 1. Always low (or high) (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 1. Always low (or high) (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) 3276.8 1. Always low (or high) (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 1 51.2 1. Always low (or high) (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) Precision Bit Data (Bits) 3210 14 12 10 14 12 10 14 12 10 14 12 10 00 0000 00 0000 00 0000 00 0000 Conversion Cycle* (s) 1638.4 409.6 102.4 1638.4 409.6 102.4 3276.8 819.2 204.8 3276.8 819.2 204.8 1 25.6 1 0.2 0 12.8 Note: * This column indicates the conversion cycle when specific DADR bits are fixed. Rev. 3.00 Mar 21, 2006 page 252 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tL1 tL2 tL3 tL255 tL256 tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tL1 + tL2 + tL3+ *** + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tL1 + tL2 + tL3 + *** + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) x 256] Figure 10.3 Output Waveform (OS = 0, DADR Corresponds to TL) Rev. 3.00 Mar 21, 2006 page 253 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tH1 tH2 tH3 tH255 tH256 tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tH1 + tH2 + tH3 + *** + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf63 tf64 tH1 tH2 tH3 tH63 tH64 tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tH1 + tH2 + tH3 + *** + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) x 256] Figure 10.4 Output Waveform (OS = 1, DADR Corresponds to TH) An example of setting CFS to 1 (basic cycle = resolution (T) x 256) and OS to 1 (PWMX inverted output) is shown as an additional pulse. When CFS is set to 1, the duty ratio of the basic pulse is determined by the upper eight bits (DA13 to DA6) in DADR, and the position of the additional pulse is determined by the following six bits (DA5 to DA0) as shown in figure 10.5. Table 10.4 shows the position of the additional pulse. DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 Basic pulse duty ratio Additional pulse position Figure 10.5 D/A Data Register Configuration when CFS = 1 Here, the case of DADR = H'0207 (B'0000 0010 0000 0111) is considered. Figure 10.6 shows an output waveform. Because CFS = 1 and the value of upper eight bits is B'0000 0010, the duty ratio of the basic pulse is 2/256 x (T) of high width. Rev. 3.00 Mar 21, 2006 page 254 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) Since the value of the following six bits is B'0000 01, the additional pulse is output at the position of basic pulse No. 63 as shown in table 10.4. Only 1/256 x (T) of the additional pulse is added to the basic pulse. One conversion cycle Basic cycle No.0 Basic cycle No.1 Basic cycle No.63 Basic pulse High width: 2/256 x (T) Additional pulse output position Basic pulse 2/256 x (T) Additional pulse 1/256 x (T) Figure 10.6 Output Waveform when DADR = H'0207 (OS = 1) Note that the case of CFS = 0 (basic cycle = resolution (T) x 64) is similar other than the duty ratio of the basic pulse is determined by the upper six bits, and the position of the additional pulse is determined by the following eight bits. Rev. 3.00 Mar 21, 2006 page 255 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) Rev. 3.00 Mar 21, 2006 page 256 of 788 REJ09B0300-0300 7 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 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Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 8 Basic Pulse No. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Table 10.4 Position of Pulse to Be Added to Basic Pulse (CFS = 1) 0 1 2 3 4 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Lower 6 bits 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 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Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Section 10 14-Bit PWM Timer (PWMX) 10.6 10.6.1 Usage Note Module Stop Mode Setting PWMX operation can be enabled or disabled using the module stop control register. The initial setting is for PWMX operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 257 of 788 REJ09B0300-0300 Section 10 14-Bit PWM Timer (PWMX) Rev. 3.00 Mar 21, 2006 page 258 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Section 11 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 11.1 Features * Selection of four clock sources One of the three internal clocks (/2, /8, or /32), or an external clock input can be selected (enabling use as an external event counter). * Two independent comparators Two independent waveforms can be output. * Four independent input capture channels The rising or falling edge can be selected. Buffer modes can be specified. * Counter clearing The free-running counters can be cleared on compare-match A. * Seven independent interrupts Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. * Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention. The contents of ICRD can be added automatically to the contents of OCRDM x 2, enabling input capture operations in this interval to be restricted. TIM8FR1A_010020020700 Rev. 3.00 Mar 21, 2006 page 259 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Figure 11.1 shows a block diagram of the FRT. External clock Internal clock FTCI Clock selector /2 /8 /32 Clock OCRAR/F (H/L) OCRA (H/L) Compare-match A Bus interface FTOA FTOB FTIA FTIB FTIC FTID Input capture Overflow Module data bus Comparator A Internal data bus FRC (H/L) Clear Compare-match B Control logic Comparator B OCRB (H/L) ICRA (H/L) ICRB (H/L) ICRC (H/L) ICRD (H/L) Comparator M Compare-match M x1 x2 OCRDM L TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt signal Legend: OCRA, OCRB : Output compare register A, B (16-bit) OCRAR,OCRAF : Output compare register AR, AF (16-bit) OCRDM : Output compare register DM (16-bit) FRC : Free-running counter (16-bit) ICRA to D : Input capture registers A to D (16-bit) TCSR TIER TCR TOCR : Timer control/status register (8-bit) : Timer interrupt enable register (8-bit) : Timer control register (8-bit) : Timer output compare control register (8-bit) Figure 11.1 Block Diagram of 16-Bit Free-Running Timer Rev. 3.00 Mar 21, 2006 page 260 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.2 Input/Output Pins Table 11.1 lists the FRT input and output pins. Table 11.1 Pin Configuration Name Counter clock input pin Output compare A output pin Output compare B output pin Input capture A input pin Input capture B input pin Input capture C input pin Input capture D input pin Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function FRC counter clock input Output compare A output Output compare B output Input capture A input Input capture B input Input capture C input Input capture D input 11.3 Register Descriptions The FRT has the following registers. * Free-running counter (FRC) * Output compare register A (OCRA) * Output compare register B (OCRB) * Input capture register A (ICRA) * Input capture register B (ICRB) * Input capture register C (ICRC) * Input capture register D (ICRD) * Output compare register AR (OCRAR) * Output compare register AF (OCRAF) * Output compare register DM (OCRDM) * Timer interrupt enable register (TIER) * Timer control/status register (TCSR) * Timer control register (TCR) * Timer output compare control register (TOCR) Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS bit in TOCR. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and OCRDM. Register selection is controlled by the ICRS bit in TOCR. Rev. 3.00 Mar 21, 2006 page 261 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 11.3.2 Output Compare Registers A and B (OCRA, OCRB) The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit readable/writable register whose contents are continually compared with the value in FRC. When a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCR is initialized to H'FFFF. 11.3.3 Input Capture Registers A to D (ICRA to ICRD) The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is detected, the current FRC value is transferred to the corresponding input capture register (ICRA to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR. ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then transferred to the buffer register ICRC. To ensure input capture, the input capture pulse width should be at least 1.5 system clocks () for a single edge. When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clocks (). ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is initialized to H'0000. Rev. 3.00 Mar 21, 2006 page 262 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A following addition of OCRAR. When using the OCRA automatic addition function, do not select internal clock /2 as the FRC input clock together with a set value of H'0001 or less for OCRAR (or OCRAF). OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRAR and OCRAF are initialized to H'FFFF. 11.3.5 Output Compare Register DM (OCRDM) OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00. When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the operation of ICRD is changed to include the use of OCRDM. The point at which input capture D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the contents of ICRD, and the result is compared with the FRC value. The point at which the values match is taken as the end of the mask interval. New input capture D events are disabled during the mask interval. A mask interval is not generated when the contents of OCRDM are H'0000 while the ICRDMS bit is set to 1. OCRDM should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRDM is initialized to H'0000. Rev. 3.00 Mar 21, 2006 page 263 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit 7 Bit Name ICIAE Initial Value 0 R/W R/W Description Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1. 0: ICIA requested by ICFA is disabled 1: ICIA requested by ICFA is enabled 6 ICIBE 0 R/W Input Capture Interrupt B Enable Selects whether to enable input capture interrupt B request (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. 0: ICIB requested by ICFB is disabled 1: ICIB requested by ICFB is enabled 5 ICICE 0 R/W Input Capture Interrupt C Enable Selects whether to enable input capture interrupt C request (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. 0: ICIC requested by ICFC is disabled 1: ICIC requested by ICFC is enabled 4 ICIDE 0 R/W Input Capture Interrupt D Enable Selects whether to enable input capture interrupt D request (ICID) when input capture flag D (ICFD) in TCSR is set to 1. 0: ICID requested by ICFD is disabled 1: ICID requested by ICFD is enabled 3 OCIAE 0 R/W Output Compare Interrupt A Enable Selects whether to enable output compare interrupt A request (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. 0: OCIA requested by OCFA is disabled 1: OCIA requested by OCFA is enabled Rev. 3.00 Mar 21, 2006 page 264 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Bit 2 Bit Name OCIBE Initial Value 0 R/W R/W Description Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled 1 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. 0: FOVI requested by OVF is disabled 1: FOVI requested by OVF is enabled 0 -- 1 R Reserved This bit is always read as 1 and cannot be modified. 11.3.7 Timer Control/Status Register (TCSR) TCSR is used for counter clear selection and control of interrupt request signals. Bit 7 Bit Name ICFA Initial Value 0 R/W Description R/(W)* Input Capture Flag A This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA [Clearing condition] Read ICFA when ICFA = 1, then write 0 to ICFA Rev. 3.00 Mar 21, 2006 page 265 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Bit 6 Bit Name ICFB Initial Value 0 R/W Description R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB [Clearing condition] Read ICFB when ICFB = 1, then write 0 to ICFB * Input Capture Flag C R/(W) This status flag indicates that the FRC value has been transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of an input capture signal specified by the IEDGC bit at the FTIC input pin, ICFC is set but data is not transferred to ICRC. In buffer operation, ICFC can be used as an external interrupt signal by setting the ICICE bit to 1. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFC when ICFC = 1, then write 0 to ICFC * Input Capture Flag D R/(W) This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of an input capture signal specified by the IEDGD bit at the FTID input pin, ICFD is set but data is not transferred to ICRD. In buffer operation, ICFD can be used as an external interrupt signal by setting the ICIDE bit to 1. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFD when ICFD = 1, then write 0 to ICFD 5 ICFC 0 4 ICFD 0 Rev. 3.00 Mar 21, 2006 page 266 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Bit 3 Bit Name OCFA Initial Value 0 R/W Description R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA * Output Compare Flag B R/(W) This status flag indicates that the FRC value matches the OCRB value. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC = OCRB [Clearing condition] Read OCFB when OCFB = 1, then write 0 to OCFB * Timer Overflow R/(W) This status flag indicates that the FRC has overflowed. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC overflows (changes from H'FFFF to H'0000) [Clearing condition] Read OVF when OVF = 1, then write 0 to OVF 2 OCFB 0 1 OVF 0 0 CCLRA 0 R/W Counter Clear A This bit selects whether the FRC is to be cleared at compare-match A (when the FRC and OCRA values match). 0: FRC clearing is disabled 1: FRC is cleared at compare-match A Note: * Only 0 can be written to clear the flag. Rev. 3.00 Mar 21, 2006 page 267 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit 7 Bit Name IEDGA Initial Value 0 R/W R/W Description Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA). 0: Capture on the falling edge of FTIA 1: Capture on the rising edge of FTIA 6 IEDGB 0 R/W Input Edge Select B Selects the rising or falling edge of the input capture B signal (FTIB). 0: Capture on the falling edge of FTIB 1: Capture on the rising edge of FTIB 5 IEDGC 0 R/W Input Edge Select C Selects the rising or falling edge of the input capture C signal (FTIC). 0: Capture on the falling edge of FTIC 1: Capture on the rising edge of FTIC 4 IEDGD 0 R/W Input Edge Select D Selects the rising or falling edge of the input capture D signal (FTID). 0: Capture on the falling edge of FTID 1: Capture on the rising edge of FTID 3 BUFEA 0 R/W Buffer Enable A Selects whether ICRC is to be used as a buffer register for ICRA. 0: ICRC is not used as a buffer register for ICRA 1: ICRC is used as a buffer register for ICRA 2 BUFEB 0 R/W Buffer Enable B Selects whether ICRD is to be used as a buffer register for ICRB. 0: ICRD is not used as a buffer register for ICRB 1: ICRD is used as a buffer register for ICRB Rev. 3.00 Mar 21, 2006 page 268 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W Description Clock Select 1, 0 Select clock source for FRC. 00: /2 internal clock source 01: /8 internal clock source 10: /32 internal clock source 11: External clock source (counting at FTCI rising edge) 11.3.9 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating modes, and switches access to input capture registers A, B, and C. Bit 7 Bit Name ICRDMS Initial Value 0 R/W R/W Description Input Capture D Mode Select Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM. 0: The normal operating mode is specified for ICRD 1: The operating mode using OCRDM is specified for ICRD 6 OCRAMS 0 R/W Output Compare A Mode Select Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 0: The normal operating mode is specified for OCRA 1: The operating mode using OCRAR and OCRAF is specified for OCRA 5 ICRS 0 R/W Input Capture Register Select The same addresses are shared by ICRA and OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which registers are selected when the shared addresses are read from or written to. The operation of ICRA, ICRB, and ICRC is not affected. 0: ICRA, ICRB, and ICRC are selected 1: OCRAR, OCRAF, and OCRDM are selected Rev. 3.00 Mar 21, 2006 page 269 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Bit 4 Bit Name OCRS Initial Value 0 R/W R/W Description Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected 3 OEA 0 R/W Output Enable A Enables or disables output of the output compare A output pin (FTOA). 0: Output compare A output is disabled 1: Output compare A output is enabled 2 OEB 0 R/W Output Enable B Enables or disables output of the output compare B output pin (FTOB). 0: Output compare B output is disabled 1: Output compare B output is enabled 1 OLVLA 0 R/W Output Level A Selects the level to be output at the output compare A output pin (FTOA) in response to compare-match A (signal indicating a match between the FRC and OCRA values). When the OCRAMS bit is 1, this bit is ignored. 0: 0 is output at compare-match A 1: 1 is output at compare-match A 0 OLVLB 0 R/W Output Level B Selects the level to be output at the output compare B output pin (FTOB) in response to compare-match B (signal indicating a match between the FRC and OCRB values). 0: 0 is output at compare-match B 1: 1 is output at compare-match B Rev. 3.00 Mar 21, 2006 page 270 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.4 11.4.1 Operation Pulse Output Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 11.2 Example of Pulse Output Rev. 3.00 Mar 21, 2006 page 271 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.5 11.5.1 Operation Timing FRC Increment Timing Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (). Internal clock FRC input clock FRC N-1 N N+1 Figure 11.3 Increment Timing with Internal Clock Source External clock input pin FRC input clock FRC N N+1 Figure 11.4 Increment Timing with External Clock Source Rev. 3.00 Mar 21, 2006 page 272 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A. FRC N N+1 N N+1 OCRA N N Compare-match A signal Clear* OLVLA Output compare A output pin FTOA Note: * Indicates instruction execution by software. Figure 11.5 Timing of Output Compare A Output 11.5.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this operation. Compare-match A signal FRC N H'0000 Figure 11.6 Clearing of FRC by Compare-Match A Signal Rev. 3.00 Mar 21, 2006 page 273 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is selected. Input capture input pin Input capture signal Figure 11.7 Input Capture Input Signal Timing (Usual Case) If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (). Figure 11.8 shows the timing for this case. Read cycle of ICRA to ICRD T1 T2 Input capture input pin Input capture signal Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) 11.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. Rev. 3.00 Mar 21, 2006 page 274 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) FTIA Input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 11.9 Buffered Input Capture Timing Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if either set of two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture input signal arrives, input capture is delayed by one system clock (). Figure 11.10 shows the timing when BUFEA = 1. CPU read cycle of ICRA or ICRC T1 T2 FTIA Input capture signal Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) Rev. 3.00 Mar 21, 2006 page 275 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD). Figure 11.11 shows the timing of setting the ICFA to ICFD flag. Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting 11.5.7 Timing of Output Compare Flag (OCF) setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. When the FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next cycle of the clock source. Figure 11.12 shows the timing of setting the OCFA or OCFB flag. Rev. 3.00 Mar 21, 2006 page 276 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) FRC N N+1 OCRA, OCRB N Compare-match signal OCFA, OCFB Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting 11.5.8 Timing of FRC Overflow Flag Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of setting the OVF flag. FRC H'FFFF H'0000 Overflow signal OVF Figure 11.13 Timing of Overflow Flag (OVF) Setting Rev. 3.00 Mar 21, 2006 page 277 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 11.14 shows the OCRA write timing. FRC N N +1 OCRA N N+A OCRAR, OCRAF A Compare-match signal Figure 11.14 OCRA Automatic Addition Timing 11.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. Figure 11.15 shows the timing of setting the mask signal. Figure 11.16 shows the timing of clearing the mask signal. Input capture signal Input capture mask signal Figure 11.15 Timing of Input Capture Mask Signal Setting Rev. 3.00 Mar 21, 2006 page 278 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) FRC N N+1 ICRD + OCRDM x 2 N Compare-match signal Input capture mask signal Figure 11.16 Timing of Input Capture Mask Signal Clearing 11.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.2 lists the sources and priorities of these interrupts. The ICIA, ICIB, OCIA, and OCIB interrupts can be used as the on-chip DTC activation sources. Table 11.2 FRT Interrupt Sources Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt Source Input capture of ICRA Input capture of ICRB Input capture of ICRC Input capture of ICRD Compare match of OCRA Compare match of OCRB Overflow of FRC Interrupt Flag ICFA ICFB ICFC ICFD OCFA OCFB OVF DTC Activation Enabled Enabled Disabled Disabled Enabled Enabled Disabled Low Priority High Rev. 3.00 Mar 21, 2006 page 279 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.7 11.7.1 Usage Notes Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of conflict. Write cycle of FRC T1 T2 Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 11.17 FRC Write-Clear Conflict Rev. 3.00 Mar 21, 2006 page 280 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict. Write cycle of FRC T1 T2 Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 11.18 FRC Write-Increment Conflict Rev. 3.00 Mar 21, 2006 page 281 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of conflict. If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of conflict. Write cycle of OCR T1 T2 Address OCR address Internal write signal FRC N N+1 OCR N M Write data Compare-match signal Disabled Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) Rev. 3.00 Mar 21, 2006 page 282 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Write cycle of OCRAR/OCRAF T1 T2 Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Old data New data Compare-match signal Disabled FRC N N+1 OCRA N Automatic addition is not performed because compare-match signals are disabled. Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used) Rev. 3.00 Mar 21, 2006 page 283 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) 11.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 11.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.3, the changeover is regarded as a falling edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock and external clock can also cause FRC to increment. Table 11.3 Switching of Internal Clock and FRC Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low No. 1 FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 CKS bit rewrite 2 Switching from low to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Rev. 3.00 Mar 21, 2006 page 284 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to low No. 3 FRC Operation Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. 11.7.5 Module Stop Mode Setting FRT operation can be enabled or disabled using the module stop control register. The initial setting is for FRT operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 285 of 788 REJ09B0300-0300 Section 11 16-Bit Free-Running Timer (FRT) Rev. 3.00 Mar 21, 2006 page 286 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Section 12 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can count external events, and can also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. This LSI also has a similar on-chip 8-bit timer module (TMR_Y and TMR_X) with two channels, which can be used through connection to the timer connection. 12.1 Features * Selection of clock sources TMR_0, TMR_1: The counter input clock can be selected from six internal clocks and an external clock TMR_Y, TMR_X: The counter input clock can be selected from three internal clocks and an external clock * Selection of three ways to clear the counters The counters can be cleared on compare-match A or compare-match B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. (The TMR_Y does not have a timer output pin.) * Cascading of TMR_0 and TMR_1 (TMR_Y and TMR_X cannot be cascaded.) Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel TMR_0, TMR_1, and TMR_Y: Three types of interrupts: Compare-match A, comparematch B, and overflow TMR_X: Input capture TIMH261A_010020020700 Rev. 3.00 Mar 21, 2006 page 287 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Figures 12.1 and 12.2 show block diagrams of the 8-bit timer module. TMR_X and TMR_Y have a similar configuration, but cannot be cascaded. TMR_X also has an input capture function. For details, see section 13, Timer Connection. External clock sources TMCI0 TMCI1 Internal clock sources TMR_0 /2, /8 /32, /64 /256, /1024 TMR_1 /2, /8 /64, /128 /1024, /2048 Clock 1 Clock 0 Clock select TCORA_0 Compare-match A1 Compare-match A0 Comparator A_0 Overflow 1 Overflow 0 Clear 0 Clear 1 Compare-match B1 Compare-match B0 Comparator B_0 TMO1 TMRI1 Control logic TCORB_0 TCORB_1 Comparator B_1 TCORA_1 Comparator A_1 TMO0 TMRI0 TCNT_0 TCNT_1 Internal bus TCSR_0 TCSR_1 TCR_0 Interrupt signals CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Legend: TCORA_0 TCORB_0 TCNT_0 TCSR_0 TCR_0 : Time constant register A_0 : Time constant register B_0 : Timer counter_0 : Timer control/status register_0 : Timer control register_0 TCORA_1 TCORB_1 TCNT_1 TCSR_1 TCR_1 TCR_1 : Time constant register A_1 : Time constant register B_1 : Timer counter_1 : Timer control/status register_1 : Timer control register_1 Figure 12.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1) Rev. 3.00 Mar 21, 2006 page 288 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) External clock sources TMCIY TMCIX Internal clock sources TMR_Y /4 /256 /2048 Clock X Clock Y TMR_X /2 /4 Clock select TCORA_Y Compare-match AX Compare-match AY Overflow X Overflow Y Clear Y Clear X TCORA_X Comparator A_Y Comparator A_X TCNT_Y TCNT_X TMRIY IVG signal Comparator B_Y Comparator B_X Compare-match BY TCORB_Y Control logic TCORB_X TMOX TMRIX Input capture TICRR TICRF TICR Compare-match C Comparator C + TCORC TCSR_Y TCR_Y TISR Interrupt signals CMIAY CMIBY OVIY ICIX Legend: TCORA_Y: Time constant register A_Y TCORB_Y: Time constant register B_Y TCNT_Y: Timer counter_Y TCSR_Y: Timer control/status register_Y TCR_Y: Timer control register_Y TISR: Timer input select register TCORA_X: TCORB_X: TCNT_X: TCSR_X: TCR_X: TICR: TCORC: TICRR: TICRF: TCSR_X TCR_X Time constant register A_X Time constant register B_X Timer counter_X Timer control/status register_X Timer control register_X Input capture register Time constant register C Input capture register R Input capture register F Figure 12.2 Block Diagram of 8-Bit Timers (TMR_Y and TMR_X) Rev. 3.00 Mar 21, 2006 page 289 of 788 REJ09B0300-0300 Internal bus Compare- match BX Section 12 8-Bit Timer (TMR) 12.2 Input/Output Pins Table 12.1 summarizes the input and output pins of the TMR. Table 12.1 Pin Configuration Channel TMR_0 Name Timer output Timer clock input Timer reset input TMR_1 Timer output Timer clock input Timer reset input TMR_Y TMR_X Timer clock/reset input Timer output Timer clock/reset input Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Output controlled by compare-match External clock input for the counter External reset input for the counter Output controlled by compare-match External clock input for the counter External reset input for the counter External clock input/external reset input for the counter Output controlled by compare-match External clock input/external reset input for the counter VSYNCI/TMIY Input (TMCIY/TMRIY) TMOX Output HFBACKI/TMIX Input (TMCIX/TMRIX) 12.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR). For details on timer connection register S, refer to section 13.3.3, Timer Connection Register S (TCONRS). * Timer counter (TCNT) * Time constant register A (TCORA) * Time constant register B (TCORB) * Timer control register (TCR) * Timer control/status register (TCSR) 1 * Timer input select register (TISR)* * Time constant register C (TCORC)* 2 * Input capture register R (TICRR)* * Input capture register F (TICRF)* 2 2 Notes: 1. TISR is only for the TMR_Y. 2. TCORC, TICRR, and TICRF are only for the TMR_X. Rev. 3.00 Mar 21, 2006 page 290 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, comparematch A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00. 12.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by these compare-match A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. 12.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by these compare-match B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. 12.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. Rev. 3.00 Mar 21, 2006 page 291 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Bit 7 Bit Name Initial Value R/W Description CMIEB 0 R/W Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. Note that a CMIB interrupt is not generated by TMR_X, regardless of the CMIEB value. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. Note that a CMIA interrupt is not generated by TMR_X, regardless of the CMIEA value. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. Note that an OVI interrupt is not generated by TMR_X, regardless of the OVIE value. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 3 CCLR1 CCLR0 0 0 R/W Counter Clear 1, 0 R/W These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W Clock Select 2 to 0 R/W These bits select the clock input to TCNT and count R/W condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 12.2. Rev. 3.00 Mar 21, 2006 page 292 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Table 12.2 Clock Input to TCNT and Count Condition TCR Channel TMR_0 CKS2 0 0 0 0 0 0 0 1 TMR_1 0 0 0 0 0 0 0 1 TMR_Y 0 0 0 0 1 TMR_X 0 0 0 0 1 Common 1 1 1 Note: CKS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 STCR ICKS1 -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ICKS0 -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /32 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /256 Increments at overflow signal from TCNT_1* Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /128 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /2048 Increments at compare-match A from TCNT_0* Disables clock input Increments at falling edge of internal clock /4 Increments at falling edge of internal clock /256 Increments at falling edge of internal clock /2048 Disables clock input Disables clock input Increments at falling edge of internal clock Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /4 Disables clock input Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock. * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated. Rev. 3.00 Mar 21, 2006 page 293 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. * TCSR_0 Bit 7 Bit Name Initial Value R/W CMFB 0 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing conditions] * Read CMFB when CMFB = 1, then write 0 in CMFB * When the DTC is activated by a CMIB interrupt * Compare-Match Flag A R/(W) [Setting condition] When the values of TCNT_0 and TCORA_0 match [Clearing conditions] * Read CMFA when CMFA = 1, then write 0 in CMFA * When the DTC is activated by a CMIA interrupt * Timer Overflow Flag R/(W) [Setting condition] When TCNT_0 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 CMFA 0 5 OVF 0 4 ADTE 0 R/W A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled Rev. 3.00 Mar 21, 2006 page 294 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Bit 3 2 Bit Name Initial Value R/W OS3 OS2 0 0 R/W R/W Description Output Select 3, 2 These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. * TCSR_1 Bit 7 Bit Name Initial Value R/W CMFB 0 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing conditions] * * Read CMFB when CMFB = 1, then write 0 in CMFB When the DTC is activated by a CMIB interrupt 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing conditions * * Read CMFA when CMFA = 1, then write 0 in CMFA When the DTC is activated by a CMIA interrupt Rev. 3.00 Mar 21, 2006 page 295 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Bit 5 Bit Name Initial Value R/W OVF 0 Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 3 2 -- OS3 OS2 1 0 0 R R/W R/W Reserved This bit is always read as 1 and cannot be modified. Output Select 3, 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. Rev. 3.00 Mar 21, 2006 page 296 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) * TCSR_Y Bit 7 Bit Name Initial Value R/W CMFB 0 1 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing conditions] * Read CMFB when CMFB = 1, then write 0 in CMFB * When the DTC is activated by a CMIB interrupt *1 Compare-Match Flag A R/(W) [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing conditions] * Read CMFA when CMFA = 1, then write 0 in CMFA * When the DTC is activated by a CMIA interrupt *1 Timer Overflow Flag R/(W) [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 CMFA 0 5 OVF 0 4 ICIE 0 R/W Input Capture Interrupt Enable Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSR_X is set to 1. 0: ICF interrupt request (ICIX) is disabled 1: ICF interrupt request (ICIX) is enabled Rev. 3.00 Mar 21, 2006 page 297 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Bit 3 2 Bit Name Initial Value R/W OS3 OS2 0 0 R/W R/W Description Output Select 3, 2 These bits specify how the TMOY pin* output level is to be changed by compare-match B of TCORB_Y and TCNT_Y. 2 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMOY pin* output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 2 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Notes: 1. Only 0 can be written, for flag clearing. 2. This product does not have a TMOY external output pin. * TCSR_X Bit 7 Bit Name Initial Value R/W CMFB 0 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing conditions] * Read CMFB when CMFB = 1, then write 0 in CMFB * When the DTC is activated by a CMIB interrupt * Compare-Match Flag A R/(W) [Setting condition] When the values of TCNT_X and TCORA_X match [Clearing conditions] * * Read CMFA when CMFA = 1, then write 0 in CMFA When the DTC is activated by a CMIA interrupt 6 CMFA 0 Rev. 3.00 Mar 21, 2006 page 298 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Bit 5 Bit Name Initial Value R/W OVF 0 Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ICF 0 R/(W)* Input Capture Flag [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order, after the ICST bit in TCONRI of the timer connection is set to 1 [Clearing condition] Read ICF when ICF = 1, then write 0 in ICF 3 2 OS3 OS2 0 0 R/W R/W Output Select 3, 2 These bits specify how the TMOX pin output level is to be changed by compare-match B of TCORB_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. Rev. 3.00 Mar 21, 2006 page 299 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.3.6 Input Capture Register (TICR) TICR is an 8-bit register. The contents of TCNT are transferred to TICR at the rising edge of the external reset input. TICR cannot be directly accessed by the CPU. The TICR function is used for the timer connection. For details, refer to section 13, Timer Connection. 12.3.7 Time Constant Register (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT. When a match is detected, a compare-match C signal is generated. However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of TICR is disabled. TCORC is initialized to H'FF. The TCORC function is used for the timer connection. For details, refer to section 13, Timer Connection. 12.3.8 Input Capture Registers R and F (TICRR, TICRF) TICRR and TICRF are 8-bit read-only registers. The contents of TCNT are transferred at the rising edge and falling edge of the external reset input in that order, when the ICST bit in TCONRI of the timer connection is set to 1. The ICST bit is cleared to 0 when one capture operation ends. TICRR and TICRF are initialized to H'00. The TICRR and TICRF functions are used for timer connection. For details, refer to section 13, Timer Connection. 12.3.9 Timer Input Select Register (TISR) TISR selects a signal source of external clock/reset input for the counter. Bit 7 to 1 0 Bit Name Initial Value R/W -- All 1 R/(W) Description Reserved The initial values should not be modified. IS 0 R/W Input Select Selects an internal synchronization signal (IVG signal) or timer clock/reset input pin VSYNCI/TMIY (TMCIY/TMRIY) as the signal source of external clock/reset input for the TMR_Y counter. 0: IVG signal is selected 1: VSYNCI/TMIY (TMCIY/TMRIY) is selected Rev. 3.00 Mar 21, 2006 page 300 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.4 12.4.1 Operation Pulse Output Figure 12.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of TCORA, and then set the CCLR0 bit to 1. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB. According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width can be output without the intervention of software. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 12.3 Pulse Output Example Rev. 3.00 Mar 21, 2006 page 301 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.5 12.5.1 Operation Timing TCNT Count Timing Figure 12.4 shows the TCNT count timing with an internal clock source. Figure 12.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks () for a single edge and at least 2.5 system clocks () for both edges. The counter will not increment correctly if the pulse width is less than these values. Internal clock TCNT input clock TCNT N-1 N N+1 Figure 12.4 Count Timing for Internal Clock Input External clock input pin TCNT input clock TCNT N-1 N N+1 Figure 12.5 Count Timing for External Clock Input (Both Edges) Rev. 3.00 Mar 21, 2006 page 302 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 12.6 shows the timing of CMF flag setting. TCNT N N+1 TCOR Compare-match signal N CMF Figure 12.6 Timing of CMF Setting at Compare-Match 12.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 12.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal. Compare-match A signal Timer output pin Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal Rev. 3.00 Mar 21, 2006 page 303 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.8 shows the timing of clearing the counter by a compare-match. Compare-match signal TCNT N H'00 Figure 12.8 Timing of Counter Clear by Compare-Match 12.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 12.9 shows the timing of clearing the counter by an external reset input. External reset input pin Clear signal TCNT N-1 N H'00 Figure 12.9 Timing of Counter Clear by External Reset Input Rev. 3.00 Mar 21, 2006 page 304 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 12.10 shows the timing of OVF flag setting. TCNT H'FF H'00 Overflow signal OVF Figure 12.10 Timing of OVF Flag Setting 12.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit count mode) or the compare-matches of the 8-bit timer of channel 0 can be counted by the 8-bit timer of channel 1 (compare-match count mode). 12.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. Setting of Compare-Match Flags: * The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. * The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. Rev. 3.00 Mar 21, 2006 page 305 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Counter Clear Specification: * If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set. * The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. Pin Output: * Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions. * Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 12.6.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel. 12.7 Input Capture Operation TMR_X has input capture registers (TICR, TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture operation controlled by the ICST bit in TCONRI of the timer connection. If the falling edge of TMRIX is detected after its rising edge has been detected while the ICST bit is set to 1, the value of TCNT at that time is transferred to both TICRR and TICRF, and the ICST bit is cleared to 0. The input signal to TMRIX can be switched by the setting of the other bits in TCONRI. Rev. 3.00 Mar 21, 2006 page 306 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Input Capture Signal Input Timing: Figure 12.11 shows the timing of the input capture operation. TMRIX Input capture signal TCNTX TICRR TICRF M m n n n+1 n m N N N+1 Figure 12.11 Timing of Input Capture Operation If the input capture signal is input while TICRR and TICRF are being read, the input capture signal is delayed by one system clock () cycle. Figure 12.12 shows the timing of this operation. TICRR, TICRF read cycle T1 T2 TMRIX Input capture signal Figure 12.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR and TICRF Read) Rev. 3.00 Mar 21, 2006 page 307 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Selection of Input Capture Signal Input: Input capture input signal of TMR_X (TMRIX) is switched according to the setting of the bits in TCONRI of the timer connection. Input capture signal selections are shown in figure 12.13 and table 12.3. For details, see section 13.3.1, Timer Connection Register I (TCONRI). TMR_X TMIX pin Polarity inversion Signal selector TMRIX TMRI1 pin Polarity inversion TMCI1 pin Polarity inversion HFINV, HIINV SIMOD1, SIMOD0 ICST Figure 12.13 Input Capture Signal Selection Table 12.3 Input Capture Signal Selection TCONRI Bit 4 ICST 0 1 Bit 7 SIMOD1 -- 0 Bit 6 SIMOD0 -- 0 1 1 1 Bit 3 HFINV -- 0 1 -- -- -- -- Bit 1 HIINV -- -- -- 0 1 0 1 Description Input capture function not used TMIX pin input selection Inverted TMIX pin input selection TMRI1 pin input selection Inverted TMRI1 pin input selection TMCI1 pin input selection Inverted TMCI1 pin input selection Rev. 3.00 Mar 21, 2006 page 308 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate an ICIX interrupt. Table 12.4 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. The CMIA and CMIB interrupts can be used as DTC activation interrupt sources. Table 12.4 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X Channel Name TMR_0 CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_Y CMIAY CMIBY OVIY TMR_X ICIX Interrupt Source TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_Y compare-match TCORB_Y compare-match TCNT_Y overflow Input capture Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF ICF DTC Activation Enabled Enabled Disabled Enabled Enabled Disabled Enabled Enabled Disabled Disabled Low Interrupt Priority High Rev. 3.00 Mar 21, 2006 page 309 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.9 12.9.1 Usage Notes Conflict between TCNT Write and Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 12.14, clearing takes priority, so that the counter is cleared and the write is not performed. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal TCNT input clock TCNT N H'00 Figure 12.14 Conflict between TCNT Write and Clear Rev. 3.00 Mar 21, 2006 page 310 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.9.2 Conflict between TCNT Write and Increment If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 12.15, the write takes priority and the counter is not incremented. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.15 Conflict between TCNT Write and Increment Rev. 3.00 Mar 21, 2006 page 311 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 12.16, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled. TCOR write cycle by CPU T1 T2 Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match signal Disabled Figure 12.16 Conflict between TCOR Write and Compare-Match Rev. 3.00 Mar 21, 2006 page 312 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) 12.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.5. Table 12.5 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 12.9.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12.6 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 12.6, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge, and TCNT is incremented. Erroneous incrementation can also happen when switching between internal and external clocks. Rev. 3.00 Mar 21, 2006 page 313 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Table 12.6 Switching of Internal Clocks and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from low 1 to low level* No. 1 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N CKS bit rewrite N+1 2 Clock switching from low 2 to high level* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite 3 Clock switching from high 3 to low level* Clock before switchover Clock after switchover TCNT clock *4 TCNT N N+1 CKS bit rewrite N+2 Rev. 3.00 Mar 21, 2006 page 314 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high to high level No. 4 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 12.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. 12.9.7 Module Stop Mode Setting TMR operation can be enabled or disabled using the module stop control register. The initial setting is for TMR operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 315 of 788 REJ09B0300-0300 Section 12 8-Bit Timer (TMR) Rev. 3.00 Mar 21, 2006 page 316 of 788 REJ09B0300-0300 Section 13 Timer Connection Section 13 Timer Connection This LSI allows interconnection between a 16-bit free-running timer (FRT) and three 8-bit timer channels (TMR_1, TMR_X, and TMR_Y). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output. 13.1 Features * Five input pins and four output pins, all of which can be designated for phase inversion. Positive logic is assumed for all signals used within the timer connection facility. * An edge-detection circuit is connected to the input pins, simplifying signal input detection. * TMR_X can be used for PWM input signal decoding. * TMR_X can be used for clamp waveform generation. * An external clock signal divided by TMR_1 can be used as the FRT capture input signal. * An internal synchronization signal can be generated using the FRT and TMR_Y. * A signal generated/modified using an input signal and timer connection can be selected and output. Figure 13.1 shows a block diagram of the timer connection facility. TIMC0N01_010020020700 Rev. 3.00 Mar 21, 2006 page 317 of 788 REJ09B0300-0300 VSYNCI/ FTIA/TMIY IVI signal IVO signal selection Phase inversion FRT output selection Phase inversion SET sync RES VSYNC modify FTIA SET IVG signal 16-bit FRT FTOA IVI signal selection Edge detection Phase inversion READ flag VFBACKI/ FTIB Edge detection VSYNCO/ FTOA FTIC FRT input selection FTIB OCRA +VR, +VF CMA(R) FTIC ICRD +1M, +2M CMA(F) compare match FTOB FTID CM1M CM2M RES VSYNC generation SET RES 2f H mask generation 2f H mask/flag Section 13 Timer Connection FTID IVO signal Rev. 3.00 Mar 21, 2006 page 318 of 788 REJ09B0300-0300 TMIY signal selection TMRI/TMCI 8-bit TMRY TMO phase inversion IHG signal CBLANK waveform generation CBLANK IHO signal selection CMB TMCI 8-bit TMR1 TMO TMRI PDC signal PWM decoding Phase inversion IHI signal TMCI TMRI CM1C 8-bit TMRX ICR ICR +1C compare match CMB TMO CMA CL signal selection READ flag CLAMP waveform generation CL1 signal CL2 signal CL3 signal CL4 signal IHI signal selection Phase inversion CL4 generation TMOX phase inversion TMO1 output selection TMR1 input selection HSYNCO/ TMO1 Phase inversion CLAMPO/ FTIC Figure 13.1 Block Diagram of Timer Connection HSYNCI/ TMCI1 Edge detection CSYNCI/ TMRI1 Edge detection HFBACKI/ FTCI/TMIX Phase inversion Edge detection Section 13 Timer Connection 13.2 Input/Output Pins Table 13.1 lists the timer connection input and output pins. Table 13.1 Pin Configuration Name Vertical synchronization signal input pin Abbreviation VSYNCI Input/ Output Input Function Vertical synchronization signal input pin or FTIA input pin/TMIY input pin Horizontal synchronization signal input pin or TMCI1 input pin Composite synchronization signal input pin or TMRI1 input pin Spare vertical synchronization signal input pin or FTIB input pin Spare horizontal synchronization signal input pin or FTCI input pin/TMIX input pin Vertical synchronization signal output pin or FTOA output pin Horizontal synchronization signal output pin or TMO1 output pin Clamp waveform output pin or FTIC input pin Blanking waveform output pin Horizontal synchronization signal HSYNCI input pin Composite synchronization signal CSYNCI input pin Spare vertical synchronization signal input pin VFBACKI Input Input Input Input Spare horizontal synchronization HFBACKI signal input pin Vertical synchronization signal output pin VSYNCO Output Output Output Output Horizontal synchronization signal HSYNCO output pin Clamp waveform output pin Blanking waveform output pin CLAMPO CBLANK 13.3 Register Descriptions The timer connection has the following registers. * Timer connection register I (TCONRI) * Timer connection register O (TCONRO) * Timer connection register S (TCONRS) * Edge sense register (SEDGR) Rev. 3.00 Mar 21, 2006 page 319 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.3.1 Timer Connection Register I (TCONRI) TCONRI controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. Bit 7 6 Bit Name SIMOD1 SIMOD0 Initial Value 0 0 R/W R/W R/W Description Input Synchronization Mode Select 1, 0 These bits select the signal source of the IHI and IVI signals. * Mode 00: No signal 01: S-on-G mode 10: Composite mode 11: Separate mode * IHI Signal 00: HFBACKI input 01: CSYNCI input 1X: HSYNCI input * IVI Signal 00: VFBACKI input 01: PDC input 10: PDC input 11: VSYNCI input 5 SCONE 0 R/W Synchronization Signal Connection Enable Selects the signal source of the FRT FTI input and the TMR_1 TMI1 input and TMCI1/TMRI1 input. For details, see table 13.2. Rev. 3.00 Mar 21, 2006 page 320 of 788 REJ09B0300-0300 Section 13 Timer Connection Bit 4 Bit Name ICST Initial Value 0 R/W R/W Description Input Capture Start Bit The TMR_X external reset input (TMRIX) is connected to the IHI signal. TMR_X has input capture registers (TICR, TICRR, and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF, respectively, and the ICST bit is cleared to 0. [Clearing condition] When a rising edge followed by a falling edge is detected on TMRIX [Setting condition] When 1 is written in ICST after reading ICST = 0 Rev. 3.00 Mar 21, 2006 page 321 of 788 REJ09B0300-0300 Section 13 Timer Connection Bit 3 2 1 0 Bit Name HFINV VFINV HIINV VIINV Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Input Synchronization Signal Inversion These bits select inversion of the input phase of the spare horizontal synchronization signal (HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal synchronization signal (HSYNCI), composite synchronization signal (CSYNCI), and the vertical synchronization signal (VSYNCI). * HFINV 0: The HFBACKI pin state is used directly as the HFBACKI input 1: The HFBACKI pin state is inverted before use as the HFBACKI input * VFINV 0: The VFBACKI pin state is used directly as the VFBACKI input 1: The VFBACKI pin state is inverted before use as the VFBACKI input * HIINV 0: The HSYNCI and CSYNCI pin states are used directly as the HSYNCI and CSYNCI inputs 1: The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and CSYNCI inputs * VIINV 0: The VSYNCI pin state is used directly as the VSYNCI input 1: The VSYNCI pin state is inverted before use as the VSYNCI input Legend: X: Don't care Table 13.2 Synchronization Signal Connection Enable Bit 5 SCONE 0 1 Mode Normal connection (Initial value) Synchronization signal connection mode FTIA FTIA input IVI signal Description FTIB FTIB input TMO1 signal FTIC FTIC input VFBACKI input FTID FTID input IHI signal TMCI1 TMCI1 input IHI signal TMRI1 TMRI1 input IVI inverse signal Rev. 3.00 Mar 21, 2006 page 322 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.3.2 Timer Connection Register O (TCONRO) TCONRO controls output signal output, phase inversion, etc. Bit 7 6 5 4 Bit Name HOE VOE CLOE CBOE Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Output Enable These bits control enabling/disabling of output of horizontal synchronization signal (HSYNCO), vertical synchronization signal (VSYNCO), clamp waveform (CLAMPO), and blanking waveform (CBLANK). When output is disabled, the state of the relevant pin is determined by port DR and DDR, FRT, TMR, and PWM settings. Output enabling/disabling control does not affect the port, FRT, or TMR input functions, but some FRT and TMR input signal sources are determined by the SCONE bit in TCONRI. HOE: 0: The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/HIRQ1 pin 1: The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin VOE: 0: The P61/FTOA/CIN1/KIN1/VSYNCO pin functions as the P61/FTOA/CIN1/KIN1 pin 1: The P61/FTOA/CIN1/KIN1/VSYNCO pin functions as the VSYNCO pin CLOE: 0: The P64/FTIC/CIN4/KIN4/CLAMPO pin functions as the P64/FTIC/CIN4/KIN4 pin 1: The P64/FTIC/CIN4/KIN4/CLAMPO pin functions as the CLAMPO pin CBOE: 0: The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin In mode 1: 1: The P27/A15/PW15/CBLANK pin functions as the A15 pin In modes 2 and 3: 1: The P27/A15/PW15/CBLANK pin functions as the CBLANK pin Rev. 3.00 Mar 21, 2006 page 323 of 788 REJ09B0300-0300 Section 13 Timer Connection Bit 3 2 1 0 Bit Name HOINV VOINV CLOINV CBOINV Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Output Synchronization Signal Inversion These bits select inversion of the output phase of the horizontal synchronization signal (HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO), and the blanking waveform (CBLANK). * HOINV: 0: The IHO signal is used directly as the HSYNCO output 1: The IHO signal is inverted before use as the HSYNCO output * VOINV: 0: The IVO signal is used directly as the VSYNCO output 1: The IVO signal is inverted before use as the VSYNCO output * CLOINV: 0: The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the CLAMPO output 1: The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as the CLAMPO output * CBOINV: 0: The CBLANK signal is used directly as the CBLANK output 1: The CBLANK signal is inverted before use as the CBLANK output Rev. 3.00 Mar 21, 2006 page 324 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.3.3 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers, and the synchronization signal output signal source and generation method. Bit 7 Bit Name TMRX/Y Initial Value 0 R/W R/W Description TMR_X/TMR_Y Access Select For details, see table 13.3. 0: The TMR_X registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 1: The TMR_Y registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 6 ISGENE 0 R/W Internal Synchronization Signal Selects internal synchronization signals (IHG, IVG, and CL4 signals) as the signal sources for the IHO, IVO, and CLO signals together with the HOMOD1, HOMOD0, VOMOD1, VOMOD0, CLMOD1, and CLMOD0 bits. 5 4 HOMOD1 HOMOD0 0 0 R/W R/W Horizontal Synchronization Output Mode Select 1, 0 These bits select the signal source and generation method for the IHO signal. * ISGENE = 0 00: The IHI signal (without 2fH modification) is selected 01: The IHI signal (with 2fH modification) is selected 1X: The CL1 signal is selected * ISGENE = 1 XX: The IHG signal is selected Rev. 3.00 Mar 21, 2006 page 325 of 788 REJ09B0300-0300 Section 13 Timer Connection Bit 3 2 Bit Name VOMOD1 VOMOD0 Initial Value 0 0 R/W R/W R/W Description Vertical Synchronization Output Mode Select 1, 0 These bits select the signal source and generation method for the IVO signal. * ISGENE = 0 00: The IVI signal (without fall modification or IHI synchronization) is selected 01: The IVI signal (without fall modification, with IHI synchronization) is selected 10: The IVI signal (with fall modification, without IHI synchronization) is selected 11: The IVI signal (with fall modification and IHI synchronization) is selected * 1 0 CLMOD1 CLMOD0 0 0 R/W R/W ISGENE = 1 XX: The IVG signal is selected Clamp Waveform Mode Select 1, 0 These bits select the signal source for the CLO signal (clamp waveform). * ISGENE = 0 00: The CL1 signal is selected 01: The CL2 signal is selected 1X: The CL3 signal is selected * Legend: X: Don't care ISGENE = 1 XX: The CL4 signal is selected Table 13.3 Registers Accessible by TMR_X/TMR_Y TMRX/Y 0 H'FFF0 TMR_X TCR_X 1 TMR_Y TCR_Y H'FFF1 TMR_X TCSR_X TMR_Y TCSR_Y H'FFF2 TMR_X TICRR TMR_Y TCORA_Y H'FFF3 TMR_X TICRF TMR_Y TCORB_Y H'FFF4 TMR_X TCNT_X TMR_Y TCNT_Y H'FFF5 TMR_X TCORC TMR_Y TISR H'FFF6 TMR_X TCORA_X H'FFF7 TMR_X TCORB_X Rev. 3.00 Mar 21, 2006 page 326 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.3.4 Edge Sense Register (SEDGR) SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH modification, and determines the phase of the IVI and IHI signals. Bit 7 Bit Name VEDG Initial Value 0 R/W Description 1 R/(W)* VSYNCI Edge Detects a rising edge on the VSYNCI pin. [Clearing condition] When 0 is written in VEDG after reading VEDG = 1 [Setting condition] When a rising edge is detected on the VSYNCI pin 6 HEDG 0 R/(W)* HSYNCI Edge 1 Detects a rising edge on the HSYNCI pin. [Clearing condition] When 0 is written in HEDG after reading HEDG = 1 [Setting condition] When a rising edge is detected on the HSYNCI pin 5 CEDG 0 R/(W)* CSYNCI Edge 1 Detects a rising edge on the CSYNCI pin. [Clearing condition] When 0 is written in CEDG after reading CEDG = 1 [Setting condition] 4 HFEDG 0 When a rising edge is detected on the CSYNCI pin *1 HFBACKI Edge R/(W) Detects a rising edge on the HFBACKI pin. [Clearing condition] When 0 is written in HFEDG after reading HFEDG = 1 [Setting condition] When a rising edge is detected on the HFBACKI pin Rev. 3.00 Mar 21, 2006 page 327 of 788 REJ09B0300-0300 Section 13 Timer Connection Bit 3 Bit Name VFEDG Initial Value 0 R/W Description 1 R/(W)* VFBACKI Edge Detects a rising edge on the VFBACKI pin. [Clearing condition] When 0 is written in VFEDG after reading VFEDG = 1 [Setting condition] When a rising edge is detected on the VFBACKI pin 2 PREQF 0 R/(W)* Pre-Equalization Flag 1 Detects the occurrence of an IHI signal 2fH modification condition. The generation of a falling/rising edge in the IHI signal during a mask interval is expressed as the occurrence of a 2fH modification condition. For details, see section 13.4.4, 2fH Modification of IHI Signal. [Clearing condition] When 0 is written in PREQF after reading PREQF = 1 [Setting condition] When an IHI signal 2fH modification condition is detected 1 IHI 2 Undefined* R IHI Signal Level Indicates the current level of the IHI signal. Signal source and phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IHI signal at positive phase by modifying TCONRI. 0: The IHI signal is low 1: The IHI signal is high 0 IVI Undefined* 2 R IVI Signal Level Indicates the current level of the IVI signal. Signal source and phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IVI signal at positive phase by modifying TCONRI. 0: The IVI signal is low 1: The IVI signal is high Notes: 1. Only 0 can be written, to clear the flag. 2. The initial value is undefined since it depends on the pin state. Rev. 3.00 Mar 21, 2006 page 328 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.4 13.4.1 Operation PWM Decoding (PDC Signal Generation) The timer connection facility and TMR_X can be used to decode a PWM signal in which 0 and 1 are represented by the pulse width. To do this, a signal in which a rising edge is generated at regular intervals must be selected as the IHI signal. The timer counter (TCNT) in TMR_X is set to count the internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI signal (the result of the pulse width decision) at the first compare-match signal B timing after TCNT is reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using TICRR and TICRF of TMR_X can be used to determine the pulse width decision threshold. Examples of TCR and TCORB settings of TMR_X are shown in tables 13.4 and 13.5, and the PWM decoding timing chart is shown in figure 13.2. Table 13.4 Examples of TCR Settings Bit 7 6 5 4 and 3 2 to 0 Abbreviation CMIEB CMIEA OVIE Contents 0 0 0 TCNT is cleared by the rising edge of the external reset signal (IHI signal) Incremented on internal clock () Description Interrupts due to compare-match and overflow are disabled CCLR1 and CCLR0 11 CKS2 to CKS0 001 Table 13.5 Examples of TCORB (Pulse Width Threshold) Settings : 10 MHz H'07 H'0F H'1F H'3F H'7F 0.8 s 1.6 s 3.2 s 6.4 s 12.8 s : 12 MHz 0.67 s 1.33 s 2.67 s 5.33 s 10.67 s : 16 MHz 0.5 s 1 s 2 s 4 s 8 s : 20 MHz 0.4 s 0.8 s 1.6 s 3.2 s 6.4 s Rev. 3.00 Mar 21, 2006 page 329 of 788 REJ09B0300-0300 Section 13 Timer Connection IHI signal is tested at compare-match IHI signal PDC signal TCNT TCORB (threshold) Counter reset caused by IHI signal Counter clear caused by TCNT overflow At the 2nd compare-match, IHI signal is not tested Figure 13.2 Timing Chart for PWM Decoding 13.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) The timer connection facility and TMR_X can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal). Three clamp waveforms can be generated: the CL1 to CL3 signals. In addition, the CL4 signal can be generated using TMR_Y. The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1 and CL2 signals can be specified by TCORA. The rise of the CL3 signal can be specified as simultaneous with the sampling of the fall of the IHI signal using the system clock, and the fall of the CL3 signal can be specified by TCORC. The CL3 signal can also fall when the IHI signal rises. TCNT in TMR_X is set to count internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal). The value to be used as the CL1 signal pulse width is written in TCORA. Write a value of H'02 or more in TCORA when internal clock is selected as the TMR_X counter clock, and a value or H'01 or more when /2 is selected. When internal clock is selected, the CL1 signal pulse width is (TCORA set value + 3 0.5). When the CL2 signal is used, the setting must be made so that this pulse width is greater than the IHI signal pulse width. The value to be used as the CL3 signal pulse width is written in TCORC. TICR in TMR_X captures the value of TCNT at the inverse of the external reset signal edge (in this case, the falling edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of the Rev. 3.00 Mar 21, 2006 page 330 of 788 REJ09B0300-0300 Section 13 Timer Connection contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes the fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall. Examples of TCR settings of TMR_X are the same as those in table 13.4. The clamp waveform timing charts are shown in figures 13.3 and 13.4. Since the rise of the CL1 and CL2 signals is synchronized with the edge of the IHI signal, and their fall is synchronized with the system clock, the pulse width variation is equivalent to the resolution of the system clock. Both the rise and the fall of the CL3 signal are synchronized with the system clock and the pulse width is fixed, but there is a variation in the phase relationship with the IHI signal equivalent to the resolution of the system clock. IHI signal CL1 signal CL2 signal TCNT TCORA Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) IHI signal CL3 signal TCNT TICR + TCORC TICR Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) Rev. 3.00 Mar 21, 2006 page 331 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.4.3 Measurement of 8-Bit Timer Divided Waveform Period The timer connection facility, TMR_1, and the free-running timer (FRT) can be used to measure the period of an IHI signal divided waveform. Since TMR_1 can be cleared by a rising edge of the inverted IVI signal, the rise and fall of the IHI signal divided waveform can be synchronized with the IVI signal. This enables period measurement to be carried out efficiently. To measure the period of an IHI signal divided waveform, TCNT in TMR_1 is set to count the external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal (inverse of the IVI signal). The value to be used as the division factor is written in TCORA, and the TMO output method is specified by the OS bits in TCSR. Examples of TCR and TCSR settings in TMR_1, and TCR and TCSR settings in the FRT are shown in table 13.6, and the timing chart for measurement of the IVI signal and IHI signal divided waveform periods is shown in figure 13.5. The period of the IHI signal divided waveform is given by (ICRD(3) - ICRD(2)) x resolution. Rev. 3.00 Mar 21, 2006 page 332 of 788 REJ09B0300-0300 Section 13 Timer Connection Table 13.6 Examples of TCR and TCSR Settings Register TCR in TMR_1 Bit 7 6 5 Abbreviation CMIEB CMIEA OVIE Contents Description 0 0 0 11 TCNT is cleared by the rising edge of the external reset signal (inverse of the IVI signal) TCNT is incremented on the rising edge of the external clock (IHI signal) Not changed by compare-match B; output inverted by compare-match A (toggle output): Division by 512 When TCORB < TCORA, 1 output on compare-match B, and 0 output on compare-match A: Division by 256 0: FRC value is transferred to ICRB on falling edge of input capture input B (IHI divided signal waveform) 1: FRC value is transferred to ICRB on rising edge of input capture input B (IHI divided signal waveform) 1 and 0 CKS1 and CKS0 TCSR in FRT 0 CCLRA 01 0 FRC is incremented on internal clock: /8 FRC clearing is disabled Interrupts due to compare-match and overflow are disabled 4 and 3 CCLR1 and CCLR0 2 to 0 TCSR in TMR_1 3 to 0 CKS2 to CKS0 OS3 to OS0 101 0011 1001 TCR in FRT 6 IEDGB 0/1 Rev. 3.00 Mar 21, 2006 page 333 of 788 REJ09B0300-0300 Section 13 Timer Connection IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) FRC ICRB Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 13.4.4 2fH Modification of IHI Signal By using the timer connection facility and FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated. In order for this function to operate properly, the duty cycle of the IHI signal must be approximately 30% or less, or approximately 70% or above. The 8-bit OCRDM contents or twice the OCRDM contents can be added automatically to the data captured in ICRD in the FRT, and compare-matches generated at these points. The interval between the two compare-matches is called a mask interval. A value equivalent to approximately 1/3 the IHI signal period is written in OCRDM. ICRD is set so that capture is performed on the rise of the IHI signal. Since the IHI signal supplied to the IHO signal selection circuit is normally set on the rise of the IHI signal and reset on the fall, its waveform is the same as that of the original IHI signal. When 2fH modification is selected, IHI signal edge detection is disabled during mask intervals. Capture is also disabled during these intervals. Examples of TCR, TCSR, TOCR, and OCRDM settings in the FRT are shown in table 13.7, and the 2fH modification timing chart is shown in figure 13.6. Rev. 3.00 Mar 21, 2006 page 334 of 788 REJ09B0300-0300 Section 13 Timer Connection Table 13.7 Examples of TCR, TCSR, TOCR, and OCRDM Settings Register TCR in FRT Bit 4 Abbreviation IEDGD Contents 1 Description FRC value is transferred to ICRD on the rising edge of input capture input D (IHI signal) FRC is incremented on internal clock: /8 FRC clearing is disabled ICRD is set to the operating mode in which OCRDM is used 1 and 0 TCSR in FRT TOCR in FRT 0 7 CKS1 and CKS0 CCLRA ICRDMS OCRDM7 to OCRDM0 01 0 1 OCRDM in FRT 7 to 0 H'01 to H'FF Specifies the period during which ICRD operation is masked IHI signal (without 2fH modification) IHI signal (with 2fH modification) Mask interval ICRD + OCRDM x 2 ICRD + OCRDM FRC ICRD Figure 13.6 2fH Modification Timing Chart Rev. 3.00 Mar 21, 2006 page 335 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.4.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection facility and TMR_1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized with the rise of the IHI signal. To perform 8-bit timer divided waveform period measurement, TCNT in TMR_1 is set to count external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal (inverse of the IVI signal). The number of IHI signal pulses until the fall of the IVI signal is written in TCORB. Since the IVI signal supplied to the IVO signal selection circuit is normally set on the rise of the IVI signal and reset on the fall, its waveform is the same as that of the original IVI signal. When fall modification is selected, a reset is performed on a TMR_1 TCORB compare-match in TMR_1. The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal, regardless of whether or not fall modification is selected. Examples of TCR, TCSR, and TCORB settings in TMR_1 are shown in table 13.8, and the fall modification/IHI synchronization timing chart is shown in figure 13.7. Rev. 3.00 Mar 21, 2006 page 336 of 788 REJ09B0300-0300 Section 13 Timer Connection Table 13.8 Examples of TCR, TCSR, and TCORB Settings Register TCR in TMR_1 Bit 7 6 5 4 and 3 Abbreviation CMIEB CMIEA OVIE CCLR1 and CCLR0 CKS2 to CKS0 OS3 to OS0 Contents 0 0 0 11 TCNT is cleared by the rising edge of the external reset signal (inverse of the IVI signal) TCNT is incremented on the rising edge of the external clock (IHI signal) Not changed by compare-match B; output inverted by compare-match A (toggle output) When TCORB < TCORA, 1 output on compare-match B, 0 output on comparematch A Compare-match on the 4th (example) rise of the IHI signal after the rise of the inverse of the IVI signal Description Interrupts due to compare-match and overflow are disabled 2 to 0 TCSR in TMR_1 3 to 0 101 0011 1001 TCORB in TMR_1 H'03 (example) IHI signal IVI signal (PDC signal) IVO signal (without fall modification, with IHI synchronization) IVO signal (with fall modification, without IHI synchronization) IVO signal (with fall modification and IHI synchronization) TCNT 0 1 2 3 4 5 TCNT = TCORB (3) Figure 13.7 Fall Modification and IHI Synchronization Timing Chart Rev. 3.00 Mar 21, 2006 page 337 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) By using the timer connection facility, FRT, and TMR_Y, it is possible to automatically generate internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the IVG signal period in order to keep it constant. In addition, the CL4 signal can be generated in synchronization with the IHG signal. The contents of OCRA in the FRT are updated by the automatic addition of the contents of OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the 0 interval of the IVG signal is written in OCRAR, and a value corresponding to the 1 interval of the IVG signal is written in OCRAF. The IVG signal is set by a compare-match after an OCRAR addition, and reset by a compare-match after an OCRAF addition. The IHG signal is the TMR_Y timer output. TMR_Y is set to count internal clock pulses, and to be cleared on a TCORA compare-match, to fix the period and set the timer output. TCORB is set so as to reset the timer output. The IVG signal is connected as the TMR_Y reset input (TMRI), and the rise of the IVG signal can be treated in the same way as a TCORA compare-match. The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG signal, and has an interval of 1 for 6 system clock periods. Examples of TCR, TCSR, TCORA, and TCORB settings in TMR_Y, and TCR, OCRAR, OCRAF, and TOCR settings in the FRT are shown in table 13.9, and the IHG signal/IVG signal timing chart is shown in figure 13.8. Rev. 3.00 Mar 21, 2006 page 338 of 788 REJ09B0300-0300 Section 13 Timer Connection Table 13.9 Examples of OCRAR, OCRAF, TCORA, TCORB, TCR, and TCSR Settings Register TCR in TMR_Y Bit 7 6 5 4 and 3 2 to 0 TCSR in TMR_Y 3 to 0 Abbreviation CMIEB CMIEA OVIE CCLR1 and CCLR0 Contents 0 0 0 01 TCNT is cleared by compare-match A TCNT is incremented on internal clock: /4 0 output on compare-match B 1 output on compare-match A IHG signal period = x 256 IHG signal 1 interval = x 16 FRC is incremented on internal clock: /8 IVG signal 0 interval = x 262016 IVG signal 1 interval = x 128 OCRA is set to the operating mode in which OCRAR and OCRAF are used IVG signal period = x 262144 (1024 times IHG signal) Description Interrupts due to compare-match and overflow are disabled CKS2 to CKS0 001 OS3 to OS0 0110 H'3F (example) H'03 (example) CKS1 and CKS0 01 H'7FEF (example) H'000F (example) TCORA in TMR_Y TCORB in TMR_Y TCR in FRT OCRAR in FRT 1 and 0 OCRAF in FRT TOCR in FRT 6 OCRAMS 1 Rev. 3.00 Mar 21, 2006 page 339 of 788 REJ09B0300-0300 Section 13 Timer Connection IVG signal OCRA (1) = OCRA (0) + OCRAF OCRA FRC OCRA (2) = OCRA (1) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (4) = OCRA (3) + OCRAR 6 system clocks CL4 signal IHG signal TCORA TCORB TCNT 6 system clocks 6 system clocks Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart Rev. 3.00 Mar 21, 2006 page 340 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.4.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by external circuitry. The HSYNCO output modes are shown in table 13.10. Table 13.10 HSYNCO Output Modes Mode No signal IHI Signal HFBACKI input IHO Signal IHI signal (without 2fH modification) IHI signal (with 2fH modification) CL1 signal IHG signal S-on-G mode CSYNCI input IHI signal (without 2fH modification) IHI signal (with 2fH modification) CL1 signal Meaning of IHO Signal HFBACKI input is output directly Meaningless unless there is a double-frequency part in the HFBACKI input HFBACKI input 1 interval is changed before output Internal synchronization signal is output CSYNCI input (composite synchronization signal) is output directly Double-frequency part of CSYNCI input (composite synchronization signal) is eliminated before output CSYNCI input (composite synchronization signal) horizontal synchronization signal part is separated before output Internal synchronization signal is output HSYNCI input (composite synchronization signal) is output directly Double-frequency part of HSYNCI input (composite synchronization signal) is eliminated before output HSYNCI input (composite synchronization signal) horizontal synchronization signal part is separated before output Internal synchronization signal is output HSYNCI input (horizontal synchronization signal) is output directly Meaningless unless there is a double-frequency part in the HSYNCI input (horizontal synchronization signal) HSYNCI input (horizontal synchronization signal) 1 interval is changed before output Internal synchronization signal is output IHG signal Composite HSYNCI mode input IHI signal (without 2fH modification) IHI signal (with 2fH modification) CL1 signal IHG signal Separate mode HSYNCI input IHI signal (without 2fH modification) IHI signal (with 2fH modification) CL1 signal IHG signal Rev. 3.00 Mar 21, 2006 page 341 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.4.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by external circuitry. The VSYNCO output modes are shown in table 13.11. Table 13.11 VSYNCO Output Modes Mode No signal IVI Signal VFBACKI input IVO Signal IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) IVI signal (with fall modification, without IHI synchronization) IVI signal (with fall modification and IHI synchronization) IVG signal S-on-G PDC signal mode or composite mode IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) Meaning of IVO Signal VFBACKI input is output directly Meaningless unless VFBACKI input is synchronized with HFBACKI input VFBACKI input fall is modified before output VFBACKI input fall is modified and signal is synchronized with HFBACKI input before output Internal synchronization signal is output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated before output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, and signal is synchronized with CSYNCI/HSYNCI input before output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, and fall is modified before output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, fall is modified, and signal is synchronized with CSYNCI/HSYNCI input before output Internal synchronization signal is output IVI signal (with fall modification, without IHI synchronization) IVI signal (with fall modification and IHI synchronization) IVG signal Rev. 3.00 Mar 21, 2006 page 342 of 788 REJ09B0300-0300 Section 13 Timer Connection Mode Separate mode IVI Signal VSYNCI input IVO Signal IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) IVI signal (with fall modification, without IHI synchronization) IVI signal (with fall modification and IHI synchronization) IVG signal Meaning of IVO Signal VSYNCI input (vertical synchronization signal) is output directly Meaningless unless VSYNCI input (vertical synchronization signal) is synchronized with HSYNCI input (horizontal synchronization signal) VSYNCI input (vertical synchronization signal) fall is modified before output VSYNCI input (vertical synchronization signal) fall is modified and signal is synchronized with HSYNCI input (horizontal synchronization signal) before output Internal synchronization signal is output 13.4.9 CBLANK Output Using the signals generated/selected with timer connection, it is possible to generate a waveform based on the composite synchronization signal (blanking waveform). One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs, with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, with the IVO signal. The logic of CBLANK output waveform generation is shown in figure 13.9. HFBACKI input (positive) VFBACKI input (positive) Falling edge sensing Rising edge sensing IVO signal (positive) Reset Q Set CBLANK signal (positive) Figure 13.9 CBLANK Output Waveform Generation Rev. 3.00 Mar 21, 2006 page 343 of 788 REJ09B0300-0300 Section 13 Timer Connection 13.5 13.5.1 Usage Note Module Stop Mode Setting Timer connection operation can be enabled or disabled using the module stop control register. The initial setting is for timer connection operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 344 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can output an overflow signal (RESO) externally. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. A block diagram of the WDT_0 and WDT_1 is shown in figure 14.1. 14.1 Features * Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks. * Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode: * If the counter overflows, an internal reset or an internal NMI interrupt is generated. * When the LSI is selected to be internally reset at counter overflow, a low level signal is output from the RESO pin if the counter overflows. Internal Timer Mode: * If the counter overflows, an internal timer interrupt (WOVI) is generated. WDT0102A_010020020700 Rev. 3.00 Mar 21, 2006 page 345 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signall*1 Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock selection /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock TCNT_0 TCSR_0 Module bus Bus interface WDT_0 WOVI1 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock selection /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256 TCNT_1 TCSR_1 Module bus Bus interface WDT_1 Legend: TCSR_0 TCNT_0 TCSR_1 TCNT_1 : Timer control/status register_0 : Timer counter_0 : Timer control/status register_1 : Timer counter_1 Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal first resets the WDT in which the overflow has occurred first. 2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1. The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from that from WDT_1. Figure 14.1 Block Diagram of WDT Rev. 3.00 Mar 21, 2006 page 346 of 788 REJ09B0300-0300 Internal bus Internal bus Section 14 Watchdog Timer (WDT) 14.2 Input/Output Pins The WDT has the pins listed in table 14.1. Table 14.1 Pin Configuration Name Reset output pin Symbol RESO I/O Output Input Function Outputs the counter overflow signal in watchdog timer mode Inputs the clock pulses to the WDT_1 prescaler counter External sub-clock input EXCL pin 14.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, refer to section 14.6.1, Notes on Register Access. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). * Timer counter (TCNT) * Timer control/status register (TCSR) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in the timer control/status register (TCSR) is cleared to 0. Rev. 3.00 Mar 21, 2006 page 347 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. * TCSR_0 Bit 7 Initial Bit Name Value OVF 0 R/W Description 1 R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * 6 WT/IT 0 R/W When TCSR is read when OVF = 1* , then 0 is written to OVF 2 When 0 is written to TME Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 3 -- 0 R/(W) R/W Reserved The initial value should not be modified. Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested RST/NMI 0 Rev. 3.00 Mar 21, 2006 page 348 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) Bit 2 1 0 Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to. The overflow frequency for = 10 MHz is enclosed in parentheses. 000: /2 (frequency: 51.2 s) 001: /64 (frequency: 1.64 ms) 010: /128 (frequency: 3.28 ms) 011: /512 (frequency: 13.1 ms) 100: /2048 (frequency: 52.4 ms) 101: /8192 (frequency: 209.7 ms) 110: /32768 (frequency: 0.84 s) 111: /131072 (frequency: 3.36 s) Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. Rev. 3.00 Mar 21, 2006 page 349 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) * TCSR_1 Bit 7 Bit Name Initial Value R/W OVF 0 1 Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * 6 WT/IT 0 R/W When TCSR is read when OVF = 1* , then 0 is written to OVF 2 When 0 is written to TME Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of -based prescaler (PSM) 1: Counts the divided cycle of SUB-based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested Rev. 3.00 Mar 21, 2006 page 350 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) Bit 2 1 0 Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle for = 10 MHz and SUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: /2 (frequency: 51.2 s) 001: /64 (frequency: 1.64 ms) 010: /128 (frequency: 3.28 ms) 011: /512 (frequency: 13.1 ms) 100: /2048 (frequency: 52.4 ms) 101: /8192 (frequency: 209.7 ms) 110: /32768 (frequency: 0.84 s) 111: /131072 (frequency: 3.36 s) When PSS = 1: 000: SUB/2 (cycle: 15.6 ms) 001: SUB/4 (cycle: 31.3 ms) 010: SUB/8 (cycle: 62.5 ms) 011: SUB/16 (cycle: 125 ms) 100: SUB/32 (cycle: 250 ms) 101: SUB/64 (cycle: 500 ms) 110: SUB/128 (cycle: 1 s) 111: SUB/256 (cycle: 2 s) Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. Rev. 3.00 Mar 21, 2006 page 351 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) 14.4 14.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the RESO pin for 132 states, as shown in figure 14.2. If the RST/NMI bit is cleared to 0, when the TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin remains high. An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time. Rev. 3.00 Mar 21, 2006 page 352 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT OVF = 1* RESO and internal reset signals generated Time WT/IT = 1 Write H'00 to TME = 1 TCNT RESO signal 132 system clocks Internal reset signal 518 system clocks Legend: WT/IT : Timer mode select bit TME : Timer enable bit OVF : Overflow flag Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation NMI Rev. 3.00 Mar 21, 2006 page 353 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 14.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1. The timing is shown figure 14.4. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time WOVI: Internal timer interrupt request occurrence Figure 14.3 Interval Timer Mode Operation TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 14.4 OVF Flag Set Timing Rev. 3.00 Mar 21, 2006 page 354 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) 14.4.3 RESO Signal Output Timing When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 14.5. TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal 132 states Internal reset signal 518 states Figure 14.5 Output Timing of RESO signal 14.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow. Table 14.2 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Not possible Rev. 3.00 Mar 21, 2006 page 355 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) 14.6 14.6.1 Usage Notes Notes on Register Access The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.6 to write to TCNT or TCSR. To write to TCNT, the upper bytes must contain the value H'5A and the lower bytes must contain the write data before the transfer instruction execution. To write to TCSR, the upper bytes must contain the value H'A5 and the lower bytes must contain the write data. Figure 14.6 Writing to TCNT and TCSR (WDT_0) Reading from TCNT and TCSR (Example of WDT_0): These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT. Rev. 3.00 Mar 21, 2006 page 356 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.7 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.7 Conflict between TCNT Write and Increment 14.6.3 Changing Values of CKS2 to CKS0 Bits If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 3.00 Mar 21, 2006 page 357 of 788 REJ09B0300-0300 Section 14 Watchdog Timer (WDT) 14.6.5 System Reset by RESO Signal Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 14.8. This LSI Reset input RES Reset signal for entire system RESO Figure 14.8 Sample Circuit for Resetting System by RESO Signal 14.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes When WDT_1 is used as a clock counter and is allowed to transit between high-speed mode and sub-active or watch mode, the counter does not display the correct value due to internal clock switching. Specifically, when transiting from high-speed mode to sub-active or watch mode, that is, when the control clock for WDT_1 switches from the main clock to the sub-clock, the counter incrementing timing is delayed for approximately two to three clock cycles. Similarly, when transiting from sub-active or watch mode to high-speed mode, the clock is not supplied until stabilized internal oscillation is available because the main clock oscillator is halted in sub-clock mode. The counter is therefore prevented from incrementing for the time specified by the STS2 to STS0 bits in SBYCR after internal oscillation starts, thus producing counter value differences for this time. Special care must be taken when using WDT_1 as a clock counter. Note that no counter value difference is produced while operated in the same mode. Rev. 3.00 Mar 21, 2006 page 358 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Section 15 Serial Communication Interface (SCI and IrDA) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function) in asynchronous mode. SCI_2 can handle communication using the waveform based on the Infrared Data Association (IrDA) standard version 1.0. 15.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * The on-chip baud rate generator allows any bit rate to be selected An external clock can be selected as a transfer clock source. * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources -- transmit-end, transmit-data-empty, receive-data-full, and receive error -- that can issue requests. The transmit-data-empty and receive-data-full interrupt sources can activate the DTC. Asynchronous Mode: * Data length: 7 or 8 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error SCI0022B_000020020700 Rev. 3.00 Mar 21, 2006 page 359 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Clocked Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors * Serial data communication with other LSIs that have the clock synchronized communication function A block diagram of the SCI is shown in figure 15.1. Internal data bus Bus interface Module data bus RDR TDR SCMR SSR SCR BRR Baud rate generator /4 /16 /64 Clock External clock TEI TXI RXI ERI RxD RSR TSR SMR Transmission/ reception control TxD Parity check SCK Parity generation Legend: RSR RDR TSR TDR SMR : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register SCR SSR SCMR BRR : Serial control register : Serial status register : Serial interface mode register : Bit rate register Figure 15.1 Block Diagram of SCI Rev. 3.00 Mar 21, 2006 page 360 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.2 Input/Output Pins Table 15.1 shows the input/output pins for each SCI channel. Table 15.1 Pin Configuration Channel 0 Symbol* SCK0 RxD0 TxD0 1 SCK1 RxD1 TxD1 2 SCK2 RxD2/IrRxD TxD2/IrTxD Note: * Input/Output Input/Output Input Output Input/Output Input Output Input/Output Input Output Function Channel 0 clock input/output Channel 0 receive data input Channel 0 transmit data output Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Channel 2 clock input/output Channel 2 receive data input (normal/IrDA) Channel 2 transmit data output (normal/IrDA) Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 15.3 Register Descriptions The SCI has the following registers for each channel. * Receive shift register (RSR) * Receive data register (RDR) * Transmit data register (TDR) * Transmit shift register (TSR) * Serial mode register (SMR) * Serial control register (SCR) * Serial status register (SSR) * Serial interface mode register (SCMR) * Bit rate register (BRR) * Keyboard comparator control register (KBCOMP) Rev. 3.00 Mar 21, 2006 page 361 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 15.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. 15.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. Rev. 3.00 Mar 21, 2006 page 362 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock source. Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. Rev. 3.00 Mar 21, 2006 page 363 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Bit 2 Bit Name MP Initial Value 0 R/W R/W Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1,0 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR. 15.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, refer to section 15.8, Interrupt Sources. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 TE RE 0 0 R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Rev. 3.00 Mar 21, 2006 page 364 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Bit 3 Bit Name MPIE Initial Value 0 R/W R/W Description Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 15.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 These bits select the clock source and SCK pin function. Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output.) 1X: External clock (SCK pin functions as clock input.) Legend: X: Don't care Rev. 3.00 Mar 21, 2006 page 365 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing the DTC to write data to TDR [Clearing conditions] * * 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] * * When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing the DTC to read data from RDR The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] When the next data is received while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 Rev. 3.00 Mar 21, 2006 page 366 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Bit 4 Bit Name FER Initial Value 0 R/W R/(W)* Description Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing the DTC to write data to TDR [Clearing conditions] * * 1 MPB 0 R Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Mar 21, 2006 page 367 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.3.8 Serial Interface Mode Register (SCMR) SCMR selects SCI functions and its format. Bit 7 to 4 3 SDIR 0 R/W Bit Name -- Initial Value All 1 R/W R Description Reserved These bits are always read as 1 and cannot be modified. Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Receive data is stored as MSB first in RDR. The SDIR bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. When the parity bit is inverted, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 0 -- SMIF 1 0 R R/W Reserved This bit is always read as 1 and cannot be modified. Serial Communication Interface Mode Select: 0: Normal asynchronous or clocked synchronous mode 1: Reserved mode Rev. 3.00 Mar 21, 2006 page 368 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 15.2 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous mode B= Bit Rate x 10 64 x 2 2n-1 6 Error x (N+1) Error (%) = { x 106 B x 64 x 2 2n-1 x (N+1) - 1 } x 100 Clocked synchronous mode B= x 106 64 x 2 2n-1 -- x (N+1) Legend: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n: Determined by the SMR settings shown in the following table. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate settable for each frequency. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Tables 15.5 and 15.7 show the maximum bit rates with external clock input. Rev. 3.00 Mar 21, 2006 page 369 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency (MHz) 2 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- n 1 1 0 0 0 0 0 0 -- -- -- 2.097152 N 148 108 217 108 54 26 13 6 -- -- -- Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- -- n 1 1 0 0 0 0 0 0 0 -- 0 2.4576 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- Operating Frequency (MHz) 3.6864 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 Legend: --: Can be set, but there will be a degree of error. Note: Make the settings so that the error does not exceed 1%. Rev. 3.00 Mar 21, 2006 page 370 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 -- 0 7.3728 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- Operating Frequency (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Legend: --: Can be set, but there will be a degree of error. Note: Make the settings so that the error does not exceed 1%. Rev. 3.00 Mar 21, 2006 page 371 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Operating Frequency (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 17.2032 N 75 223 111 223 111 223 111 55 27 16 16 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 166 233 166 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 Legend: --: Can be set, but there will be a degree of error. Note: Make the settings so that the error does not exceed 1%. Rev. 3.00 Mar 21, 2006 page 372 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 Maximum Bit Rate (bit/s) n 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 (MHz) 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) n 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 15.000 1.5360 1.8432 2.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 (MHz) 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 Rev. 3.00 Mar 21, 2006 page 373 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) Bit Rate (bit/s) n 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M Legend: Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer or reception is not possible. 3 2 1 1 0 0 0 0 0 0 0 0 2 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1* 0 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* n 8 N n 10 N n 16 N n 20 N Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 2 4 6 8 10 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 (MHz) 12 14 16 18 20 External Input Clock (MHz) 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 Rev. 3.00 Mar 21, 2006 page 374 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.3.10 Keyboard Comparator Control Register (KBCOMP) KBCOMP selects the functions of the SCI and A/D converter. Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Specifies SCI_2 I/O pins for either normal SCI or IrDA. 0: TxD2/IrTxD and RxD2/IrRxD pins function as TxD2 and RxD2 pins, respectively 1: TxD2/IrTxD and RxD2/IrRxD pins function as IrTxD and IrRxD pins, respectively 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select 2 to 0 These bits specify the high-level width of the clock pulse during IrTxD output pulse encoding when the IrDA function is enabled. 000: B x 3/16 (B: Bit rate) 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 3 2 1 0 KBADE KBCH2 KBCH1 KBCH0 0 0 0 0 R/W R/W R/W R/W Bits related to the A/D converter For details, refer to section 21.3.4, Keyboard Comparator Control Register (KBCOMP). Rev. 3.00 Mar 21, 2006 page 375 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 3.00 Mar 21, 2006 page 376 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.4.1 Data Transfer Format Table 15.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 15.5, Multiprocessor Communication Function. Table 15.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 3.00 Mar 21, 2006 page 377 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 15.3. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = } (0.5 - 1 2N )- D - 0.5 (1 + F) - (L - 0.5) F } x 100 N [%] ... Formula (1) M: Reception margin (%) N : Ratio of bit rate to clock (N = 16) D : Clock duty (D = 0.5 to 1.0) L : Frame length (L = 9 to 12) F : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875 % However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 3.00 Mar 21, 2006 page 378 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) Rev. 3.00 Mar 21, 2006 page 379 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR, or the contents of RDR. When an external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer/receive format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [1] Set data transfer/receive format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 15.5 Sample SCI Initialization Flowchart Rev. 3.00 Mar 21, 2006 page 380 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.4.5 Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 15.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8Bit Data, Parity, One Stop Bit) Rev. 3.00 Mar 21, 2006 page 381 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. [4] Clear TE bit in SCR to 0 Figure 15.7 Sample Serial Transmission Flowchart Rev. 3.00 Mar 21, 2006 page 382 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 15.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 3.00 Mar 21, 2006 page 383 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Table 15.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flow chart for serial data reception. Table 15.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. Rev. 3.00 Mar 21, 2006 page 384 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. Read ORER, PER, and FER flags in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DTC is initiated by an RXI interrupt and reads data from RDR. Legend: : Logical OR No All data received? Yes Clear RE bit in SCR to 0 Figure 15.9 Sample Serial Reception Flowchart (1) Rev. 3.00 Mar 21, 2006 page 385 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Flowchart (2) Rev. 3.00 Mar 21, 2006 page 386 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 3.00 Mar 21, 2006 page 387 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) ID transmission cycle = receiving station specification Legend: MPB: Multiprocessor bit Receiving station C (ID = 03) H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Receiving station D (ID = 04) Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Rev. 3.00 Mar 21, 2006 page 388 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set port DDR to 1, clear DR to 0, and then clear the TE bit in SCR to 0. No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 3.00 Mar 21, 2006 page 389 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 D0 D1 Data (ID2) D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data 2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data 2 MPIE bit set to 1 again (b) Data matches station's ID Figure 15.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 3.00 Mar 21, 2006 page 390 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value. Legend: : Logical OR Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR [2] FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes [3] FER ORER = 1 No Read RDRF flag in SSR Yes No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 3.00 Mar 21, 2006 page 391 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00 Mar 21, 2006 page 392 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling fullduplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer/reception Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 15.14 Data Format in Clocked Synchronous Communication (LSB-First) 15.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 3.00 Mar 21, 2006 page 393 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE to 0. [2] Set the data transfer/receive format in SMR and SCMR. [1] Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [3] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer/receive format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 15.15 Sample SCI Initialization Flowchart Rev. 3.00 Mar 21, 2006 page 394 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 15.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev. 3.00 Mar 21, 2006 page 395 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 15.16 Example of SCI Transmit Operation in Clocked Synchronous Mode Rev. 3.00 Mar 21, 2006 page 396 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 Figure 15.17 Sample Serial Transmission Flowchart Rev. 3.00 Mar 21, 2006 page 397 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart for serial data reception. Rev. 3.00 Mar 21, 2006 page 398 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DTC is initiated by a receive data full interrupt (RXI) and reads data from RDR. Read ORER flag in SSR [2] Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 15.19 Sample Serial Reception Flowchart Rev. 3.00 Mar 21, 2006 page 399 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, check that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0, and then set the TE and RE bits to 1 simultaneously with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, check that the SCI has finished reception, and clear the RE bit to 0. Then after checking that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, set the TE and RE bits to 1 simultaneously with a single instruction. Rev. 3.00 Mar 21, 2006 page 400 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] [3] Read ORER flag in SSR Yes [3] Error processing ORER = 1 No [4] Read RDRF flag in SSR No RDRF = 1 Yes [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ Read receive data in RDR, and reception, before the MSB (bit 7) of clear RDRF flag in SSR to 0 the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, No before the MSB (bit 7) of the current All data received? [5] frame is transmitted, read 1 from the TDRE flag to confirm that writing is Yes possible. Then write data to TDR and clear the TDRE flag to 0. However, the TDRE flag is checked Clear TE and RE bits in SCR to 0 and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev. 3.00 Mar 21, 2006 page 401 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.7 IrDA Operation IrDA operation can be used with SCI_2. Figure 15.21 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in KBCOMP, the TxD2 and RxD2 pins in SCI_2 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTxD and IrRxD pins). Connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the IrDA standard version 1.0. In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming. IrDA SCI2 TxD2/IrTxD Pulse encoder TxD RxD2/IrRxD Pulse decoder RxD KBCOMP Figure 15.21 IrDA Block Diagram Rev. 3.00 Mar 21, 2006 page 402 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Transmission: During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 15.22). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in KBCOMP. The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) + 1.08 s at maximum. For example, when the frequency of system clock is 20 MHz, a high-level pulse width of at least 1.4 s to 1.6 s can be specified. For serial data of level 1, no pulses are output. UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Transmission Reception IR frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Bit cycle Pulse width is 1.6 s to 3/16 bit cycle Figure 15.22 IrDA Transmission and Reception Reception: During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI_2. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the minimum width allowed, the pulse is recognized as level 0. Rev. 3.00 Mar 21, 2006 page 403 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) High-Level Pulse Width Selection: Table 15.10 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.10 IrCKS2 to IrCKS0 Bit Settings Bit Rate (bps) (Upper Row) / Bit Interval x 3/16 (s) (Lower Row) Operating Frequency (MHz) 2 2.097152 2.4576 3 3.6864 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 16.9344 17.2032 18 19.6608 20 2400 78.13 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 9600 19.53 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 19200 9.77 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 38400 4.88 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 57600 3.26 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 115200 1.63 -- -- -- -- 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 Legend: --: An SCI bit rate setting cannot be made. Rev. 3.00 Mar 21, 2006 page 404 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.8 Interrupt Sources Table 15.11 shows the interrupt sources in serial communication interface. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DTC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 15.11 SCI Interrupt Sources Channel 0 Name ERI0 RXI0 TXI0 TEI0 1 ERI1 RXI1 TXI1 TEI1 2 ERI2 RXI2 TXI2 TEI2 Interrupt Source Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority High Rev. 3.00 Mar 21, 2006 page 405 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.9 15.9.1 Usage Notes Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 26, Power-Down Modes. 15.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 15.9.3 Mark State and Break Detection When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to the mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 15.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 15.9.5 Relation between Writing to TDR and TDRE Flag Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. Rev. 3.00 Mar 21, 2006 page 406 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.9.6 Restrictions on Using DTC When an external clock source is used as a synchronization clock, update TDR by the DTC or RFU and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 15.23). When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC activation source. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: * When external clock is supplied, t must be more than four clock cycles. Figure 15.23 Example of Transmission Using DTC in Clocked Synchronous Mode 15.9.7 SCI Operations during Mode Transitions Transmission: Before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If a transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 15.24 shows a sample flowchart for mode transition during transmission. Figures 15.25 and 15.26 show the pin states during transmission. Before making a transition from the transmission mode using DTC transfer to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission using the DTC. Rev. 3.00 Mar 21, 2006 page 407 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Reception: Before making a transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If a transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 15.27 shows a sample flowchart for mode transition during reception. Transmission All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation; however, if the DTC has been initiated, the data remaining in DTC RAM will be transmitted when TE and TIE are set to 0. [2] Also clear TIE and TEIE to 0 when they are 1. Make transition to software standby mode etc. Cancel software standby mode etc. [3] [3] Module stop, watch, sub-active, and sub-sleep modes are included. Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 15.24 Sample Flowchart for Mode Transition during Transmission Rev. 3.00 Mar 21, 2006 page 408 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Transmission start Transition to Software standby Transmission end software standby mode cancelled mode TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Port Figure 15.25 Pin States during Transmission in Asynchronous Mode (Internal Clock) Transition to Software standby software standby mode cancelled mode Transmission start Transmission end TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output SCI TxD output Last TxD bit retained Port input/output Port High output* SCI TxD output Port Note: * Initialized in software standby mode Figure 15.26 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) Rev. 3.00 Mar 21, 2006 page 409 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. RE = 0 [2] [2] Module stop, watch, sub-active, and subsleep modes are included. Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? Yes Initialization No RE = 1 Start reception Figure 15.27 Sample Flowchart for Mode Transition during Reception Rev. 3.00 Mar 21, 2006 page 410 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) 15.9.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.28. Low pulse of half a cycle SCK/Port 1. Transmission end Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 3. C/A = 0 4. Low pulse output Figure 15.28 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins, specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1. 1. End serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 (switch to port output) 5. CKE1 bit = 0 High output SCK/Port 1. Transmission end Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 15.29 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins Rev. 3.00 Mar 21, 2006 page 411 of 788 REJ09B0300-0300 Section 15 Serial Communication Interface (SCI and IrDA) Rev. 3.00 Mar 21, 2006 page 412 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Section 16 I C Bus Interface (IIC) (Optional) The I C bus interface is provided as an optional function. Note the following point when using this optional function. * Although the product type name is identical, please contact Renesas before using this optional function on an F-ZTAT version product. This LSI has a two-channel I C bus interface. The I C bus interface conforms to and provides a 2 subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that 2 controls the I C bus differs partly from the Philips configuration, however. 2 2 2 2 16.1 2 Features * Selection of addressing format or non-addressing format I C bus format: addressing format with an acknowledge bit, for master/slave operation Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master operation only Formatless (for IIC_0 only): non-addressing format with a clock pin dedicated for formatless; for slave operation only * Conforms to Philips I C bus interface (I C bus format) 2 2 * Two ways of setting slave address (I C bus format) 2 * Start and stop conditions generated automatically in master mode (I C bus format) 2 * Selection of the acknowledge output level in reception (I C bus format) 2 * Automatic loading of an acknowledge bit in transmission (I C bus format) 2 * Wait function in master mode (I C bus format) 2 A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * Wait function (I C bus format) 2 A wait request can be generated by driving the SCL pin low after data transfer. The wait request is cleared when the next transfer becomes possible. * Interrupt sources Data transfer end (including when a transition to transmit mode with I C bus format occurs, when ICDR data is transferred, or during a wait state) 2 IFIIC60A_000020020700 Rev. 3.00 Mar 21, 2006 page 413 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Address match: When any slave address matches or the general call address is received in 2 slave receive mode with I C bus format (including address reception after loss of master arbitration) Start condition detection (in master mode) Stop condition detection (in slave mode) * Selection of 16 internal clocks (in master mode) * Direct bus drive (SCL/SDA pin) Four pins--P52/SCL0, P97/SDA0, P86/SCL1, and P42/SDA1 --(normally NMOS pushpull outputs) function as NMOS open-drain outputs when the bus drive function is selected. * Automatic switching from formatless mode to I C bus format (IIC_0 only) 2 Formatless operation (no start/stop conditions, non-addressing mode) in slave mode Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL) Automatic switching from formatless mode to I C bus format on the fall of the SCL pin 2 Rev. 3.00 Mar 21, 2006 page 414 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Figure 16.1 shows a block diagram of the I C bus interface. Figure 16.2 shows an example of I/O 2 pin connections to external circuits. Since I C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 28, Electrical Characteristics. Formatless dedicated clock (IIC_0 only) 2 ICXR SCL PS Clock control ICCR Noise canceler ICMR Bus state decision circuit Arbitration decision circuit SDA Output data control circuit ICSR ICDRT ICDRS ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register ICXR: I2C bus extended control register SAR: Slave address register SARX: Slave address register X PS: Prescaler 2 Interrupt generator Figure 16.1 Block Diagram of I C Bus Interface Rev. 3.00 Mar 21, 2006 page 415 of 788 REJ09B0300-0300 Internal data bus Interrupt request Section 16 I C Bus Interface (IIC) (Optional) 2 VDD VCC VCC SCL SCL in SCL out SDA SCL SDA SDA in SDA out (Master) This LSI SCL SDA SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) 2 SDA in SDA out (Slave 2) Figure 16.2 I C Bus Interface Connections (Example: This LSI as Master) 16.2 Input/Output Pins 2 Table 16.1 summarizes the input/output pins used by the I C bus interface. Table 16.1 Pin Configuration Channel 0 Symbol* SCL0 SDA0 VSYNCI 1 Note: * SCL1 SDA1 Input/Output Input/Output Input/Output Input Input/Output Input/Output Function Serial clock input/output pin of IIC_0 Serial data input/output pin of IIC_0 Formatless serial clock input pin of IIC_0 Serial clock input/output pin of IIC_1 Serial data input/output pin of IIC_1 In the text, the channel subscript is omitted, and only SCL and SDA are used. Rev. 3.00 Mar 21, 2006 page 416 of 788 REJ09B0300-0300 SCL SDA Section 16 I C Bus Interface (IIC) (Optional) 2 16.3 2 Register Descriptions The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR). * I C bus control register (ICCR) 2 2 2 2 * I C bus status register (ICSR) * I C bus data register (ICDR) * I C bus mode register (ICMR) * Slave address register (SAR) * Second slave address register (SARX) * I C bus extended control register (ICXR) 2 * DDC switch register (DDCSWR) (for IIC_0 only) 16.3.1 I C Bus Data Register (ICDR) 2 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among these three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF. In master transmit mode with the I C bus format, writing transmit data to ICDR should be performed after start condition detection. When the start condition is detected, previous write data is ignored. In slave transmit mode, writing should be performed after the slave addresses match and the TRS bit is automatically changed to 1. If the IIC is in transmit mode (TRS = 1) and ICDRT has the next transmit data (the ICDRE flag is 0) after successful transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If the IIC is in transmit mode (TRS = 1) and ICDRT has the next data (the ICDRE flag is 0), data is transferred automatically from ICDRT to ICDRS, following transmission of one frame of data using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is 2 transferred automatically from ICDRT to ICDRS by writing to ICDR. If I C is in receive mode (TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to ICDR in receive mode. Rev. 3.00 Mar 21, 2006 page 417 of 788 REJ09B0300-0300 2 Section 16 I C Bus Interface (IIC) (Optional) 2 Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR. If I C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from 2 ICDRS to ICDRR. Always set I C to receive mode before reading from ICDR. If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1. ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value of ICDR is undefined. 16.3.2 Slave Address Register (SAR) 2 SAR sets the slave address and selects the communication format. If the LSI is in slave mode with 2 the I C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Format Select Selects the communication format together with the FSX bit in SARX and the SW bit in DDCSWR. Refer to table 16.2. This bit should be set to 0 when general call address recognition is performed. Description Slave Address 6 to 0 Set a slave address. Rev. 3.00 Mar 21, 2006 page 418 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. In slave mode, transmit/receive operations by the DTC are possible when the received address matches the 2 second slave address. If the LSI is in slave mode with the I C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Initial Value R/W 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W Format Select X Selects the communication format together with the FS bit in SAR and the SW bit in DDCSWR. Refer to table 16.2. Description Second Slave Address 6 to 0 Set the second slave address. Rev. 3.00 Mar 21, 2006 page 419 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.2 Communication Format DDCSWR SW 0 SAR FS 0 SARX FSX 0 Operating Mode I C bus format * * 1 2 2 SAR and SARX slave addresses recognized General call address recognized SAR slave address recognized SARX slave address ignored General call address recognized SAR slave address ignored SARX slave address recognized General call address ignored SAR and SARX slave addresses ignored General call address ignored Acknowledge bit used I C bus format * * * 1 0 I C bus format * * * 2 1 Clocked synchronous serial format * * 1 0 0 1 Formatless mode (start/stop conditions not detected) * 1 0 1 Formatless mode (start/stop conditions not detected) * No acknowledge bit 2 Do not set this mode when automatic switching to the I C bus format is performed by means of the DDCSWR setting. * I C bus format: addressing format with an acknowledge bit 2 * Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master mode only * Formatless mode (for IIC_0 only): non-addressing format with or without an acknowledge bit, slave mode only, start/stop conditions not detected Rev. 3.00 Mar 21, 2006 page 420 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.3.4 I C Bus Mode Register (ICMR) 2 ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit 7 Bit Name MLS Initial Value R/W 0 R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit This bit is valid only in master mode with the I C bus format. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit (8 clock), the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. For details, refer to section 16.4.7, IRIC Setting Timing and SCL Control. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Transfer Clock Select 2 to 0 These bits are used only in master mode. These bits select the required transfer rate, together with the IICX1 (IIC_1) and IICX0 (IIC_0) bits in STCR. Refer to table 16.3. th 2 2 Rev. 3.00 Mar 21, 2006 page 421 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value R/W 0 0 0 R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 when a start condition is detected. The value returns to 000 at the end of a data transfer. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits 2 2 Clocked Synchronous Serial Mode 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits Rev. 3.00 Mar 21, 2006 page 422 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.3 I C Transfer Rate STCR Bits 5 and 6 IICX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 5 CKS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ICMR Bit 4 CKS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 3 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 2 Transfer Rate Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz = 16 MHz 517 kHz* 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz = 20 MHz 714 kHz* 500 kHz* 417 kHz* 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz Note: * Outside the I C bus interface specifications (standard mode: max. 100 kHz; high-speed mode: max. 400 kHz) Rev. 3.00 Mar 21, 2006 page 423 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.3.5 I C Bus Control Register (ICCR) 2 2 ICCR controls the I C bus interface and performs interrupt flag confirmation. Bit 7 Bit Name ICE Initial Value R/W 0 R/W Description I C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 1: I C bus interface modules can perform transfer operation, and the ports function as the SCL and SDA input/output pins. ICMR and ICDR can be accessed. 6 IEIC 0 R/W I C Bus Interface Interrupt Enable 0: Disables interrupts from the I C bus interface to the CPU 1: Enables interrupts from the I C bus interface to the CPU. 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they 2 lose in a bus contention in master mode with the I C bus 2 format. In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition sets these bits in receive mode or transmit mode automatically by hardware. Modification of the TRS bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer. 2 2 2 2 2 2 2 Rev. 3.00 Mar 21, 2006 page 424 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 5 4 Bit Name MST TRS Initial Value R/W 0 0 R/W Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (for TRS setting condition 3) 3 When lost in bus contention in I C bus format master mode 2 2 2 4. When the SW bit in DDCSWR is changed from 1 to 0 [TRS setting conditions] 1. When 1 is written by software (except for TRS clearing conditions 3 and 4) 2. When 1 is written in TRS after reading TRS = 0 (for TRS clearing conditions 3 and 4) 3. When 1 is received as the R/W bit after the first frame 2 address matching in I C bus format slave mode 3 ACKE 0 R/W Acknowledge Bit Decision and Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit in ICSR, which is always 0. 1: If the received acknowledge bit is 1, continuous transfer is halted. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Rev. 3.00 Mar 21, 2006 page 425 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 2 0 Bit Name BBSY SCP Initial Value R/W 0 1 R/W W Description Bus Busy Start Condition/Stop Condition Prohibit In master mode: * * Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued Writing to the BBSY flag is disabled. 2 In slave mode: * [BBSY setting condition] When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. [BBSY clearing condition] When the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. To issue a start/stop condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Set MST to 1 and TRS to 1 before writing 1 in BBSY and 0 in SCP. The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. The SCP bit is always read as 1. If 0 is written, the data is not stored. 2 2 Rev. 3.00 Mar 21, 2006 page 426 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 1 Bit Name IRIC Initial Value R/W 0 Description 2 2 2 R/(W)* I C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 16.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. [Setting conditions] I C bus format master mode: * When a start condition is detected in the bus line state after a start condition is issued (when the ICDRE flag is set to 1 because of first frame transmission) When a wait is inserted between the data and acknowledge bit when the WAIT bit is 1 (fall of the 8th transmit/receive clock) At the end of data transfer (rise of the 9th transmit/receive clock while no wait is inserted) When a slave address is received after bus arbitration is lost (the first frame after the start condition) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) when the ACKE bit is 1 When the AL flag is set to 1 after bus arbitration is lost while the ALIE bit is 1 When the slave address (SVA or SVAX) matches (when the AAS or AASX flag in ICSR is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (rise of the 9th transmit/receive clock) When the general call address is detected (when 0 is received as the R/W bit and the ADZ flag in ICSR is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (rise of the 9th receive clock) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) while the ACKE bit is 1 When a stop condition is detected (when the STOP or ESTP flag in ICSR is set to 1) while the STOPIM bit is 0 2 * * * * * 2 I C bus format slave mode: * * * * Rev. 3.00 Mar 21, 2006 page 427 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 1 Bit Name IRIC Initial Value R/W 0 Description * At the end of data transfer (rise of the 8th transmit/receive clock with serial format selected and rise of the 9th transmit/receive clock with formatless selected) When a start condition is detected with serial format selected When the SW bit in DDCSWR is set to 1 2 R/(W)* Clocked synchronous serial format and formatless modes: * * When the ICDRE or ICDRF flag is set to 1 in any operating mode: * When a start condition is detected in transmit mode (when a start condition is detected in transmit mode and the ICDRE flag is set to 1) When data is transferred among the ICDR register and buffer (when data is transferred from ICDRT to ICDRS in transmit mode and the ICDRE flag is set to 1, or when data is transferred from ICDRS to ICDRR in receive mode and the ICDRF flag is set to 1) When 0 is written in IRIC after reading IRIC = 1 When ICDR is read from or written to by the DTC (This may not function as a clearing condition depending on the situation. For details, see the description of the DTC operation given below.) * [Clearing conditions] * * Note: * Only 0 can be written, to clear the flag. When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission 2 start condition or stop condition after a slave address (SVA) or general call address match in I C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous 2 Rev. 3.00 Mar 21, 2006 page 428 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Tables 16.4 and 16.5 show the relationship between the flags and the transfer states. Table 16.4 Flags and Transfer States (Master Mode) MST 1 1 1 1 1 1 1 1 TRS 1 1 -- 1 1 1 1 1 BBSY ESTP STOP IRTR AASX AL 0 0 0 0 0 0 0 0 AAS 0 0 0 0 0 0 0 0 ADZ 0 0 0 0 0 0 0 0 ACKB ICDRF ICDRE State Idle state (flag clearing required) Start condition detected Wait state Transmission end (ACKE=1 and ACKB=1) Transmission end with ICDRE=0 ICDR write with the above state Transmission end with ICDRE=1 ICDR write with the above state or after start condition detected Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF=0 ICDR read with the above state Reception end with ICDRF=1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Arbitration lost Stop condition detected 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 -- -- 1 -- -- -- 0 0 0 0 0 0 0 0 0 0 -- 1 0 0 0 0 -- -- -- -- -- -- -- -- 0 1 -- -- 1 0 1 0 1 1 1 0 0 1 0 0 0 0 0 -- 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 -- -- -- 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- 1 0 1 0 1 -- -- -- -- -- 0 1 0 -- 1 0 0 0 0 0 -- -- 0 0 1 0 0 0 0 0 -- -- -- -- -- 0 Legend: 0: 1: 0-state retained 1-state retained --: Previous state retained 0: Cleared to 0 1: Set to 1 Rev. 3.00 Mar 21, 2006 page 429 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.5 Flags and Transfer States (Slave Mode) MST 0 0 0 0 TRS 0 0 BBSY ESTP STOP IRTR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 AASX AL 0 0 0 0 0 0 -- -- AAS 0 0 1 1 ADZ 0 0 0 1 ACKB ICDRF ICDRE State 0 0 0 0 -- -- 1 1 0 1 1 1 Idle state (flag clearing required) Start condition detected SAR match in first frame (SARX SAR) General call address match in first frame (SARX H'00) SARS match in first frame (SAR SARX) Transmission end (ACKE = 1 and ACKB =1 ) Transmission end with ICDRE = 0 ICDR write with the above state Transmission end with ICDRE = 1 ICDR write with the above state Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF=0 ICDR read with the above state Reception end with ICDRF = 1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Stop condition detected 1 1/0* 1 0 1 0 0 0 0 0 0 0 1 1/0* 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 -- 1 -- -- -- -- 0 -- 0 0 0 -- -- 0 -- 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 -- -- -- -- -- -- 1 -- 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1/0* -- -- -- -- -- -- -- 1/0*2 -- 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1/0*2 -- -- -- -- -- -- -- -- 0 -- 0 0 -- 0 -- 0 0 -- 0 -- 0 0 -- -- -- -- -- 1 0 1 0 1 -- -- -- -- -- 1/0*2 -- 0 -- 0 1/0*3 0/1*3 -- -- -- -- -- -- -- 0 Legend: 0: 0-state retained 1: 1-state retained --: Previous state retained 0: Cleared to 0 1: Set to 1 Notes: 1. Set to 1 when 1 is received as a R/W bit following an address. 2. Set to 1 when the AASX bit is set to 1. 3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0. Rev. 3.00 Mar 21, 2006 page 430 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.3.6 I C Bus Status Register (ICSR) 2 ICSR consists of status flags. Also see tables 16.4 and 16.5. Bit 7 Bit Name ESTP Initial Value R/W 0 Description 2 R/(W)* Error Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing conditions] * When 0 is written in ESTP after reading ESTP = 1 * When the IRIC flag in ICCR is cleared to 0 * Normal Stop Condition Detection Flag R/(W) This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected after frame transfer completion. [Clearing conditions] * * When 0 is written in STOP after reading STOP = 1 When the IRIC flag is cleared to 0 2 6 STOP 0 Rev. 3.00 Mar 21, 2006 page 431 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 5 Bit Name IRTR Initial Value R/W 0 Description 2 2 R/(W)* I C Bus Interface Continuous Transfer Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. [Setting conditions] I C bus format slave mode: * When the ICDRE or ICDRF flag in ICDR is set to 1 when AASX = 1 2 2 Master mode or clocked synchronous serial format mode 2 with I C bus format, or formatless mode: * * 4 AASX 0 When the ICDRE or ICDRF flag is set to 1 When 0 is written after reading IRTR = 1 [Clearing conditions] * When the IRIC flag is cleared to 0 while ICE is 1 * Second Slave Address Recognition Flag R/(W) In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. [Setting condition] When the second slave address is detected in slave receive mode and FSX = 0 in SARX [Clearing conditions] * * * When 0 is written in AASX after reading AASX = 1 When a start condition is detected In master mode 2 Rev. 3.00 Mar 21, 2006 page 432 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 3 Bit Name AL Initial Value R/W 0 Description 2 R/(W)* Arbitration Lost Flag Indicates that arbitration was lost in master mode. [Setting conditions] When ALSL = 0 * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master transmit mode If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the SDA pin is driven low by another device before 2 the I C bus interface drives the SDA pin low, after the start condition instruction was executed in master transmit mode When ICDR is written to (transmit mode) or read from (receive mode) When ALSL = 1 * * [Clearing conditions] * 2 AAS 0 * When 0 is written in AL after reading AL = 1 R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. [Setting condition] When the slave address or general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 in SAR [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode 2 Rev. 3.00 Mar 21, 2006 page 433 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 1 Bit Name ADZ Initial Value R/W 0 Description 2 2 R/(W)* General Call Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). [Setting condition] When the general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 or FSX = 0 [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in ADZ after reading ADZ = 1 In master mode If a general call address is detected while FS=1 and FSX=0, the ADZ flag is set to 1; however, the general call address is not recognized (AAS flag is not set to 1). Rev. 3.00 Mar 21, 2006 page 434 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 0 Bit Name ACKB Initial Value R/W 0 R/W Description Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] When 1 is received as the acknowledge bit when ACKE=1 in transmit mode [Clearing conditions] * * When 0 is received as the acknowledge bit when ACKE=1 in transmit mode When 0 is written to the ACKE bit 2 Receive mode: 0: Returns 0 as acknowledge data after data reception 1: Returns 1 as acknowledge data after data reception When this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when TRS = 1). In reception (when TRS = 0), the value set by internal software is read. When this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. If the ICSR register bit is written using bit-manipulation instructions, the acknowledge data should be re-set since the acknowledge data setting is rewritten by the ACKB bit reading value. Write the ACKE bit to 0 to clear the ACKB flag to 0, before transmission is ended and a stop condition is issued in master mode, or before transmission is ended and SDA is released to issue a stop condition by a master device. Note: * Only 0 can be written to clear the flag. Rev. 3.00 Mar 21, 2006 page 435 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.3.7 DDC Switch Register (DDCSWR) DDCSWR controls the IIC_0 automatic format switching function and IIC internal latch clearance. Bit 7 Bit Name Initial Value R/W SWE 0 R/W Description DDC Mode Switch Enable 0: Disables automatic switching of IIC channel 0 from 2 formatless mode to I C bus format 1: Enables automatic switching of IIC channel 0 from 2 formatless mode to I C bus format 6 SW 0 R/W DDC Mode Switch 0: Uses IIC channel 0 with the I C bus format 1: Uses IIC channel 0 in formatless mode [Setting condition] When 1 is written in SW after reading SW = 0 [Clearing conditions] * * 5 IE 0 R/W When 0 is written by software When a falling edge is detected on the SCL pin when SWE = 1 2 DDC Mode Switch Interrupt Enable Bit 0: Disables interrupts when automatic format switching is executed 1: Enables interrupts when automatic format switching is executed 4 IF 0 R/(W)* 1 DDC Mode Switch Interrupt Flag Indicates an interrupt request to the CPU is generated when automatic format switching is executed for IIC_0. [Setting condition] When a falling edge is detected on the SCL pin when SWE = 1 [Clearing condition] When 0 is written in IF after reading IF = 1 Rev. 3.00 Mar 21, 2006 page 436 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 3 2 1 0 Bit Name CLR3 CLR2 CLR1 CLR0 Initial Value R/W 1 1 1 1 2 W* 2 Description IIC Clear 3 to 0 Controls initialization of the internal state of IIC_0 and IIC_1. 00--: Setting prohibited 0100: Setting prohibited 0101: IIC_0 internal latch cleared 0110: IIC_1 internal latch cleared 0111: IIC_0 and IIC_1 internal latches cleared 1---: Invalid setting When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module, and the internal state of the IIC module is initialized. These bits can only be written to; they are always read as 1. Write data to this bit is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. If the function of these bits is not used, set all of the CLR3 to CLR0 bits to 1 when writing to DDCSWR. W* 2 W* 2 W* 2 Notes: 1. Only 0 can be written, to clear the flag. 2. This bit is always read as 1. Rev. 3.00 Mar 21, 2006 page 437 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.3.8 I C Bus Extended Control Register (ICXR) 2 2 ICXR enables or disables the I C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. Bit 7 Bit Name STOPIM Initial Value R/W 0 R/W Description Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode. 0: Enables IRIC flag setting and interrupt generation when the stop condition is detected (STOP = 1 or ESTP = 1) in slave mode. 1: Disables IRIC flag setting and interrupt generation when the stop condition is detected. 6 HNDS 0 R/W Handshake Receive Operation Select Enables or disables continuous receive operation in receive mode. 0: Enables continuous receive operation 1: Disables continuous receive operation When the HNDS bit is cleared to 0, receive operation is performed continuously after data has been received successfully while ICDRF flag is 0. When the HNDS bit is set to 1, SCL is fixed to the low level and the next data transfer is disabled after data has been received successfully while the ICDRF flag is 0. The bus line is released and next receive operation is enabled by reading the receive data in ICDR. Rev. 3.00 Mar 21, 2006 page 438 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 5 Bit Name ICDRF Initial Value R/W 0 R Description Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] * When data is received successfully and transferred from ICDRS to ICDRR. 2 (1) When data is received successfully while ICDRF = 0 (at the rise of the 9th clock pulse). (2) When ICDR is read successfully in receive mode after data was received while ICDRF = 1. [Clearing conditions] * * * When ICDR (ICDRR) is read. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR. When ICDRF is set due to the condition (2) above, ICDRF is temporarily cleared to 0 when ICDR (ICDRR) is read; however, since data is transferred from ICDRS to ICDRR immediately, ICDRF is set to 1 again. Note that ICDR cannot be read successfully in transmit mode (TRS = 1) because data is not transferred from ICDRS to ICDRR. Be sure to read data from ICDR in receive mode (TRS = 0). Rev. 3.00 Mar 21, 2006 page 439 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 4 Bit Name ICDRE Initial Value R/W 0 R Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to. [Setting conditions] * * * When the start condition is detected from the bus line 2 state with I C bus format or serial format. When I C bus mode is switched to formatless (when the SW bit in DDCSWR is set to 1). When data is transferred from ICDRT to ICDRS. 1. When data transmission completed while ICDRE = 0 (at the rise of the 9th clock pulse). 2. When data is written to ICDR in transmit mode after data transmission was completed while ICDRE = 1. [Clearing conditions] * * * * When data is written to ICDR (ICDRT). When the stop condition is detected with I C bus format or serial format. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR. 2 2 2 2 Note that if the ACKE bit is set to 1 with I C bus format thus enabling acknowledge bit decision, ICDRE is not set when data transmission is completed while the acknowledge bit is 1. When ICDRE is set due to the condition (2) above, ICDRE is temporarily cleared to 0 when data is written to ICDR (ICDRT); however, since data is transferred from ICDRT to ICDRS immediately, ICDRE is set to 1 again. Do not write data to ICDR when TRS = 0 because the ICDRE flag value is invalid during the time. Rev. 3.00 Mar 21, 2006 page 440 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Bit 3 Bit Name ALIE Initial Value R/W 0 R/W Description Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost. 0: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SCL pin is driven low by another device. 1: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SDA line is driven low by another device in idle state or after the start condition instruction was executed. 1 0 FNC1 FNC0 0 0 R/W R/W Function Bit Cancels some restrictions on usage. For details, refer to section 16.6, Usage Notes. 00: Restrictions on operation remaining in effect 01: Setting prohibited 10: Setting prohibited 11: Restrictions on operation canceled 2 Rev. 3.00 Mar 21, 2006 page 441 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.4 2 Operation 2 The I C bus interface has an I C bus format and a serial format. 16.4.1 2 I C Bus Data Format 2 The I C bus format is an addressing format with an acknowledge bit. This is shown in figure 16.3. The first frame following a start condition always consists of 9 bits. IIC_0 only is capable of formatless operation, as shown in figure 16.4. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 16.5. Figure 16.6 shows the I C bus timing. The symbols used in figures 16.3 to 16.6 are explained in table 16.6. (a) FS = 0 or FSX = 0 S 1 SLA 7 1 (b) Start condition retransmission FS = 0 or FSX = 0 S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 Upper row: Transfer bit count (n1, n2 = 1 to 8) Lower row: Transfer frame count (m1, m2 = from 1) A/A 1 P 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) 2 Figure 16.3 I C Bus Data Format (I C Bus Format) FS = 0 or FSX = 0 DATA 8 1 A 1 DATA n A 1 m A/A 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) 2 2 Note: This mode is applied to the PC monitor system standard DDC (Display Data Channel). Figure 16.4 I C Bus Data Format (Formatless) (IIC_0 Only) 2 Rev. 3.00 Mar 21, 2006 page 442 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 FS=1 and FSX=1 S 1 DATA 8 1 DATA n m P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) Figure 16.5 I C Bus Data Format (Serial Format) 2 SDA SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 2 8 9 A 1-7 DATA 8 9 A/A P Figure 16.6 I C Bus Timing Table 16.6 I C Bus Data Format Symbols Legend S SLA R/W A Start condition. The master device drives SDA from high to low while SCL is high Slave address. The master device selects the slave device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The slave device returns acknowledge in master transmit mode, and the master device returns acknowledge in master receive mode.) Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR. Stop condition. The master device drives SDA from low to high while SCL is high 2 DATA P Rev. 3.00 Mar 21, 2006 page 443 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.4.2 Initialization Initialize the IIC by the procedure shown in figure 16.7 before starting transmission/reception of data. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) (MSTPCRL) Set IICE = 1 in STCR Set DDCSWR Set ICE = 0 in ICCR Set SAR and SARX Set ICE = 1 in ICCR Set ICSR Set STCR Set ICMR Set ICXR Set ICCR Cancel module stop mode Enable the CPU accessing to the IIC control register and data register Set IIC communication format (SWE, SW, IE, and IF) Enable SAR and SARX to be accessed Set the first and second slave addresses and IIC communication format (SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX) Enable ICMR and ICDR to be accessed Use SCL/SDA pin as an IIC port Set acknowledge bit (ACKB) Set transfer rate (IICX) Set communication format, wait insertion, and transfer rate (MLS, WAIT, CKS2 to CKS0) Enable interrupt (STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0) Set interrupt enable, transfer mode, and acknowledge decision (IEIC, MST, TRS, and ACKE) << Start transmit/receive operation >> Figure 16.7 Sample Flowchart for IIC Initialization Note: Be sure to modify the ICMR register after transmit/receive operation has been completed. If the ICMR register is modified during transmit/receive operation, bit counter BC2 to BC0 will be modified erroneously, thus causing incorrect operation. 16.4.3 2 Master Transmit Operation In I C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. Figure 16.8 shows the sample flowchart for the operations in master transmit mode. Rev. 3.00 Mar 21, 2006 page 444 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Start Initialize IIC [1] Initialization Read BBSY flag in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Read IRIC flag in ICCR [5] Wait for a start condition generation No IRIC = 1? Yes Write transmit data in ICDR Clear IRIC flag in ICCR [6] Set transmit data for the first byte (slave address + R/W). (After writing to ICDR, clear IRIC flag continuously.) [7] Wait for 1 byte to be transmitted. [3] Select master transmit mode. [4] Start condition issuance Read IRIC flag in ICCR No IRIC = 1? Yes Read ACKB bit in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR No No [8] Test the acknowledge bit transferred from the slave device. Master receive mode [9] Set transmit data for the second and subsequent bytes. (After writing to ICDR, clear IRIC flag continuously.) [10] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB bit in ICSR [11] Determine end of tranfer No End of transmission? or ACKB = 1? Yes Clear IRIC flag in ICCR Set BBSY = 0 and SCP = 0 in ICCR End [12] Stop condition issuance Figure 16.8 Sample Flowchart for Operations in Master Transmit Mode Rev. 3.00 Mar 21, 2006 page 445 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3. Set bits MST and TRS to 1 in ICCR to select master transmit mode. 4. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (R/W). To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear IRIC continuously so no other interrupt handling routine is executed. If the time for transmission of one frame of data has passed before the IRIC clearing, the end of transmission cannot be determined. The master device sequentially sends the transmission clock and the data written to ICDR. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the transmit operation. 9. Write the transmit data to ICDR. As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data to be transmitted, go to step [9] to continue the next transmission operation. When the slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission. 2 Rev. 3.00 Mar 21, 2006 page 446 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Start condition generation SCL (master output) SDA (master output) SDA (slave output) ICDRE 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [7] A 9 1 Bit 7 2 Bit 6 Slave address [5] Data 1 IRIC Interrupt request Interrupt request IRTR ICDRT Address + R/W Data 1 ICDRS Address + R/W Data 1 Note:* Data write in ICDR prohibited User processing [4] BBSY set to 1 [6] ICDR write SCP cleared to 0 (start condition issuance) [6] IRIC clear [9] ICDR write [9] IRIC clear Figure 16.9 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 3.00 Mar 21, 2006 page 447 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Start condition issuance SCL (master output) 8 9 1 Bit 7 [7] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [10] A 9 SDA Bit 0 (master output) Data 1 SDA (slave output) ICDRE Data 2 IRIC IRTR ICDR Data 1 Data 2 User processing [9] ICDR write [9] IRIC clear [11] ACKB read [12] IRIC clear [12] Set BBSY=1and SCP=0 (Stop condition issuance) Figure 16.10 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) 16.4.4 2 Master Receive Operation In I C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. Rev. 3.00 Mar 21, 2006 page 448 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Receive Operation Using the HNDS Function (HNDS = 1): Figure 16.11 shows the sample flowchart for the operations in master receive mode (HNDS = 1). Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 1 in ICXR Clear IRIC flag in ICCR [1] Select receive mode. Last receive? No Read ICDR Yes [2] Start receiving. The first read is a dummy read. [5] Read the receive data (for the second and subsequent read) Read IRIC flag in ICCR No IRIC = 1? Yes Clear IRIC flag in ICCR [3] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock for the receive frame) [4] Clear IRIC flag. Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1? [6] Set acknowledge data for the last reception. [7] Read the receive data. Dummy read to start receiving if the first frame is the last receive data. [8] Wait for 1 byte to be received. Yes Clear IRIC flag in ICCR Set TRS = 1 in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR End [9] Clear IRIC flag. [10] Read the receive data. [11] Set stop condition issuance. Generate stop condition. Figure 16.11 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) Rev. 3.00 Mar 21, 2006 page 449 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 The reception procedure and operations using the HNDS function, by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception, are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception. Go to step [6] to halt reception operation if the first frame is the last receive data. 2. When ICDR is read (dummy data read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. (Data from the SDA pin is sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.) 3. The master device drives SDA low to return the acknowledge data at the 9th receive clock pulse. The receive data is transferred from ICDRS to ICDRR at the rise of the 9th clock pulse, setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data reading. 4. Clear the IRIC flag to clear the wait state. Go to step [6] to halt reception operation if the next frame is the last receive data. 5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock continuously to receive the next data. Data can be received continuously by repeating steps [3] to [5]. 6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception. 7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock to receive data. 8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the rise of the 9th receive clock pulse. 9. Clear the IRIC flag to 0. 10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0. 11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev. 3.00 Mar 21, 2006 page 450 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Master transmit mode Master receive mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR 9 A 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 Data 1 Data 2 Undefined value [2] ICDR read (Dummy read) Data 1 User processing [1] TRS = 0 clear [4] IRIC clear [5] ICDR read (Data 1) [1] IRIC clear Figure 16.12 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) SCL is fixed low until stop condition is issued 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [8] A 9 SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR Data 1 Data 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 Stop condition generation Data 2 Data 3 Data 3 [10] ICDR read (Data 3) User processing [4] IRIC clear [7] ICDR read (Data 2) [6] Set ACKB = 1 [9] IRIC clear [11] Set BBSY = 0 and SCP = 0 (Stop condition instruction issuance) Figure 16.13 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) Receive Operation Using the Wait Function: Figures 16.14 and 16.15 show the sample flowcharts for the operations in master receive mode (WAIT = 1). Rev. 3.00 Mar 21, 2006 page 451 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 1 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [1] Select receive mode. 2 Read IRIC flag in ICCR No IRIC = 1? Yes No [4] Determine end of reception IRTR = 1? Yes Last receive? No Read ICDR [5] Read the receive data. [6] Clear IRIC flag. (to end the wait insertion) Yes Clear IRIC flag in ICCR Set ACKB = 1 in ICSR Wait for one clock pulse Set TRS = 1 in ICCR Read ICDR Clear IRIC flag in ICCR [7] Set acknowledge data for the last reception. [8] Wait for TRS setting [9] Set TRS for stop condition issuance [10] Read the receive data. [11] Clear IRIC flag. (to end the wait insertion) Read IRIC flag in ICCR No IRIC=1? Yes IRTR=1? No Clear IRIC flag in ICCR Yes [12] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [13] Determine end of reception [14] Clear IRIC. (to end the wait insertion) Set WAIT = 0 in ICMR Clear IRIC flag in ICCR Read ICDR Set BBSY= 0 and SCP= 0 in ICCR End [15] Clear wait mode. Clear IRIC flag. ( IRIC flag should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data. [17] Generate stop condition Figure 16.14 Sample Flowchart for Operations in Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1) Rev. 3.00 Mar 21, 2006 page 452 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Slave receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 0 in ICMR [1] Select receive mode. Read ICDR [2] Start receiving. The first read is a dummy read. Read IRIC flag in ICCR No IRIC = 1? [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) Yes Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC flag in ICCR [7] Set acknowledge data for the last reception. [9] Set TRS for stop condition issuance [11] Clear IRIC flag. (to end the wait insertion) [12] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock) Read IRIC flag in ICCR No IRIC = 1? Yes Set WAIT = 0 in ICMR Clear IRIC flag in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR [15] Clear wait mode. Clear IRIC flag. (IRIC flag should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data [17] Generate stop condition End Figure 16.15 Sample Flowchart for Operations in Master Receive Mode (Receiving a Single Byte) (WAIT = 1) Rev. 3.00 Mar 21, 2006 page 453 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted. At this time, follow the procedure shown in figure 16.15. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 to set the acknowledge data. Clear the HNDS bit in ICXR to 0 to cancel the handshake function. Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1. 2. When ICDR is read (dummy data is read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. 3. The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 4. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt reception. 5. If IRTR flag is 1, read ICDR receive data. 6. Clear the IRIC flag. When the flag is set as the first case in step [3], the master device outputs the 9th clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal. Data can be received continuously by repeating steps [3] to [6]. 7. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception. 8. After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first clock pulse for the next receive data. 9. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit value becomes valid when the rising edge of the next 9th clock pulse is input. 10. Read the ICDR receive data. Rev. 3.00 Mar 21, 2006 page 454 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 11. Clear the IRIC flag to 0. 12. The IRIC flag is set to 1 in either of the following cases. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 13. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop condition. 14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state. Execute step [12] to read the IRIC flag to detect the end of reception. 15. Clear the WAIT bit in CMR to cancel the wait mode. Then, clear the IRIC flag. Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the stop condition may not be issued correctly.) 16. Read the last ICDR receive data. 17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev. 3.00 Mar 21, 2006 page 455 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Master tansmit mode Master receive mode SCL (master output) 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 SDA (slave output) SDA (master output) A Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 [3] A [3] Bit 7 Bit 6 Bit 5 Data 2 Bit 4 Bit 3 IRIC IRTR [4]IRTR=0 [4] IRTR=1 ICDR Data 1 User processing [1] TRS cleared to 0 IRIC cleard to 0 [2] ICDR read (dummy read) [6] IRIC clear [5] ICDR read [6] IRIC clear (to end wait insertion) (Data 1) Figure 16.16 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) [8] Wait for one clock pulse Stop condition generation SCL (master output) 8 9 1 Bit 7 [3] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [12] A [12] 9 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) IRIC IRTR ICDR [4] IRTR=0 Data 3 [4] IRTR=1 [13] IRTR=0 [13] IRTR=1 Data 1 Data 2 Data 3 [15] WAIT cleared to 0, IRIC clear [14] IRIC clear [17] Stop condition issuance [16] ICDR read (Data 3) User processing [6] IRIC clear [11] IRIC clear [10] ICDR read (Data 2) [9] Set TRS=1 [7] Set ACKB=1 Figure 16.17 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1) Rev. 3.00 Mar 21, 2006 page 456 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.4.5 2 Slave Receive Operation In I C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address. Receive Operation Using the HNDS Function (HNDS = 1): Figure 16.18 shows the sample flowchart for the operations in slave receive mode (HNDS = 1). Rev. 3.00 Mar 21, 2006 page 457 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR 2 [1] Initialization. Select slave receive mode. Read IRIC flag in ICCR ICDRF = 1? Yes No [2] Read the receive data remaining unread. Read ICDR, clear IRIC flag Read IRIC flag in ICCR No IRIC = 1? Yes [3] to [7] Wait for one byte to be received (slave address + R/W) Clear IRIC flag in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Yes [8] Clear IRIC General call address processing * Description omitted Read TRS in ICCR TRS = 1? No Yes Yes Slave transmit mode Last reception? No Read ICDR [10] Read the receive data. The first read is a dummy read. Read IRIC flag in ICCR No IRIC = 1? Yes [5] to [7] Wait for the reception to end. Clear IRIC flag in ICCR [8] Clear IRIC flag. Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1? Yes [9] Set acknowledge data for the last reception. [10] Read the receive data. [11] Detect stop condition [12] Clear IRIC flag. Clear IRIC in ICCR End Figure 16.18 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) Rev. 3.00 Mar 21, 2006 page 458 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 The reception procedure and operations using the HNDS bit function, by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W), in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit (R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive clock pulse until data is read from ICDR. 8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0. 9. If the next frame is the last receive frame, set the ACKB bit to 1. 10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the master device to transfer the next data. Receive operations can be performed continuously by repeating steps [5] to [10]. 11. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. 12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0. Rev. 3.00 Mar 21, 2006 page 459 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) IRIC 1 1 2 2 3 3 4 4 5 5 6 6 7 7 [7] SCL is fixed low until ICDR is read 8 8 9 9 1 1 2 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Bit 7 Bit 6 Data 1 Slave address [6] A Interrupt request occurrence ICDRF ICDRS Address+R/W ICDRR Undefined value Address+R/W User processing [2] ICDR read [8] IRIC clear [10] ICDR read (dummy read) Figure 16.19 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) Rev. 3.00 Mar 21, 2006 page 460 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 [7] SCL is fixed low until ICDR is read SCL (master output) SCL (slave output) SDA (master output) Data (n-1) SDA (slave output) IRIC Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 8 9 1 2 3 4 5 [7] SCL is fixed low until ICDR is read 6 7 8 9 Stop condition generation Bit 3 Bit 2 Bit 1 Bit 0 [6] Data (n) [6] [11] A A ICDRF ICDRS Data (n-1) Data (n) Data (n-1) Data (n) ICDRR Data (n-2) User processing [8] IRIC clear [5] ICDR read (Data (n-1)) [9] Set ACKB=1 [8] IRIC clear [10] ICDR read (Data (n)) [12] IRIC clear Figure 16.20 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) Continuous Receive Operation: Figure 16.21 shows the sample flowchart for the operations in slave receive mode (HNDS = 0). Rev. 3.00 Mar 21, 2006 page 461 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Slave receive mode Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? Yes Read ICDR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Read TRS in ICCR TRS = 1? No No Yes Yes No [1] Select slave receive mode. [2] Read the receive data remaining unread. [3] to [7] Wait for one byte to be received (slave address + R/W) (Set IRIC at the rise of the 9th clock) [8] Clear IRIC General call address processing * Description omitted Slave transmit mode * n: Address + total number of bytes received (n-2)th-byte reception? Wait for one frame Set ACKB = 1 in ICSR [9] Wait for ACKB setting and set acknowledge data for the last reception (after the rise of the 9th clock of (n-1)th byte data) No ICDRF = 1? Yes Read ICDR Read IRIC in ICCR No IRIC = 1? [10] Read the receive data. The first read is a dummy read. [11] Wait for one byte to be received (Set IRIC at the rise of the 9th clock) ESTP = 1 or STOP = 1? No Clear IRIC in ICCR Yes [12] Detect stop condition [13] Clear IRIC ICDRF = 1? Yes Read ICDR Clear IRIC in ICCR End No [14] Read the last receive data [15] Clear IRIC Figure 16.21 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) Rev. 3.00 Mar 21, 2006 page 462 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W) in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, the IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. 8. Confirm that the STOP bit is cleared to 0 and clear the ICIC flag to 0. 9. If the next read data is the third last receive frame, wait for at least one frame time to set the ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive frame. 10. Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0. 11. At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to ICDRR due to ICDR read operation, the IRIC and ICDRF flags are set to 1. 12. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. In this case, execute step [14] to read the last receive data. 13. Clear the IRIC flag to 0. Receive operations can be performed continuously by repeating steps [9] to [13]. 14. Confirm that the ICDRF flag is set to 1, and read ICDR. 15. Clear the IRIC flag. Rev. 3.00 Mar 21, 2006 page 463 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Start condition issuance SCL (master output) SDA (master output) SDA (slave output) IRIC 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [6] A 9 1 Bit 7 2 Bit 6 Data 1 3 Bit 5 4 Bit 4 Slave address ICDRF ICDRS Address+R/W [7] Data 1 ICDRR Address+R/W User processing [8] IRIC clear [10] ICDR read Figure 16.22 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0) Start condition detection SCL (master output) 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA (master output) Bit 0 Data n-2 SDA (slave output) IRIC ICDRF ICDRS ICDRR User processing Data n-2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [11] A Data n-1 [11] A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data n [11] A [11] Data n-1 Data n-2 [9] Wait for one frame [13] IRIC clear Data n-1 Data n Data n [13] IRIC clear [10] ICDR read [10] ICDR read (Data n-1) (Data n-2) [9] Set ACKB = 1 [13] IRIC clear [14] ICDR read (Data n) [15] IRIC clear Figure 16.23 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0) Rev. 3.00 Mar 21, 2006 page 464 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 16.24 shows the sample flowchart for the operations in slave transmit mode. Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR [1], [2] If the slave address matches to the address in the first frame following the start condition detection and the R/W bit is 1 in slave recieve mode, the mode changes to slave transmit mode. [3], [5] Set transmit data for the second and subsequent bytes. [3], [4] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB in ICSR [4] Determine end of transfer. No End of transmission (ACKB = 1)? Yes Clear IRIC in ICCR [6] Read IRIC in ICCR [7] Clear acknowledge bit data [8] Set slave receive mode. [9] Dummy read (to release the SCL line). [10] Wait for stop condition Clear ACKE to 0 in ICCR (ACKB=0 clear) Set TRS = 0 in ICCR Read ICDR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR End Figure 16.24 Sample Flowchart for Slave Transmit Mode Rev. 3.00 Mar 21, 2006 page 465 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the ICDRE flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written, to disable the master device to output the next transfer clock. 3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to 0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again. The slave device sequentially sends the data written into ICDRS in accordance with the clock output by the master device. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. 4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed successfully. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS, transmission starts, and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. 5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. Transmit operations can be performed continuously by repeating steps [4] and [5]. 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9. Dummy-read ICDR to release SDA on the slave side. Rev. 3.00 Mar 21, 2006 page 466 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0. Slave receive mode SCL (master output) SDA (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Bit 7 Bit 6 [2] Data 1 [4] Data 2 SDA (master output) R/W A IRIC ICDRE ICDR User processing [3] IRIC clear [3] ICDR write [3] IRIC clear Data 1 Data 2 [5] IRIC clear [5] ICDR write Figure 16.25 Example of Slave Transmit Mode Operation Timing (MLS = 0) Rev. 3.00 Mar 21, 2006 page 467 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock. Figures 16.26 to 16.28 show the IRIC set timing and SCL control. When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 2 3 SDA 7 8 A 1 2 3 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception SCL 7 8 9 1 SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception Figure 16.26 IRIC Setting Timing and SCL Control (1) Rev. 3.00 Mar 21, 2006 page 468 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 2 3 SDA 8 A 1 2 3 IRIC User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception SCL 8 9 1 SDA 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception Figure 16.27 IRIC Setting Timing and SCL Control (2) Rev. 3.00 Mar 21, 2006 page 469 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 When FS = 1 and FSX = 1 (clocked synchronous serial format) SCL 7 8 1 2 3 4 SDA 7 8 1 2 3 4 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception SCL 7 8 1 SDA 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception Figure 16.28 IRIC Setting Timing and SCL Control (3) 16.4.8 Automatic Switching from Formatless Mode to I C Bus Format 2 Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC_0 2 operating mode. Switching from formatless mode to the I C bus format (slave mode) is performed automatically when a falling edge is detected on the SCL pin. The following four preconditions are necessary for this operation: * A common data pin (SDA) for formatless and I C bus format operation 2 * Separate clock pins for formatless operation (VSYNCI) and I C bus format operation (SCL) 2 * A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low level) Rev. 3.00 Mar 21, 2006 page 470 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 * Settings of bits other than TRS in ICCR that allow I C bus format operation 2 Automatic switching is performed from formatless mode to the I C bus format when the SW bit in DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching 2 from the I C bus format to formatless mode is achieved by setting the SW bit in DDCSWR to 1 by software. In formatless mode, bits (such as MSL and TRS) that control the I C bus interface operating mode 2 must not be modified. When switching from the I C bus format to formatless mode, set the TRS bit to 1 or clear it to 0 according to the transfer direction (transmission or reception) in formatless 2 mode, then set the SW bit to 1. After automatic switching from formatless mode to the I C bus format (slave mode), the TRS bit is automatically cleared to 0 in order to wait for slave address reception. If a falling edge is detected on the SCL pin during formatless operation, the mode of the I C bus 2 interface is immediately switched to I C bus format before a stop condition is detected. 16.4.9 Operation Using DTC 2 2 2 This LSI provides the DTC to allow continuous data transfer. The DTC is initiated when the IRTR flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the acknowledge bit value. If the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set when data transmission is completed with the acknowledge bit value of 0, and if the ACKE bit is 1, only the IRIC flag is set when data transmission is completed with the acknowledge bit value of 1. When initiated, the DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, the DTC is not initiated, thus allowing an interrupt to be generated if enabled. The acknowledge bit may indicate specific events such as completion of receive data processing for some receiving devices, and for other receiving devices, the acknowledge bit may be fixed at 1, indicating no specific events. The I C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 16.7 shows some examples of processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode. Rev. 3.00 Mar 21, 2006 page 471 of 788 REJ09B0300-0300 2 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.7 Examples of Operation Using DTC Item Master Transmit Mode Master Receive Mode Transmission by CPU (ICDR write) Slave Transmit Mode Reception by CPU (ICDR read) Slave Receive Mode Reception by CPU (ICDR read) Slave address + Transmission by R/W bit DTC (ICDR write) transmission/ reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing Setting of number of DTC transfer data frames -- Transmission by DTC (ICDR write) -- Not necessary 1st time: Clearing by CPU 2nd time: Stop condition issuance by CPU Processing by CPU (ICDR read) Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Not necessary -- Transmission by DTC (ICDR write) Processing by DTC (ICDR write) Not necessary -- Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Automatic clearing Not necessary on detection of stop condition during transmission of dummy data (H'FF) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to dummy data (H'FF)) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to slave address + R/W bits) 16.4.10 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.29 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Rev. 3.00 Mar 21, 2006 page 472 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock cycle Sampling clock Figure 16.29 Block Diagram of Noise Canceler 16.4.11 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 16.3.7, DDC Switch Register (DDCSWR). Scope of Initialization: The initialization executed by this function covers the following items: * ICDRE and ICDRF internal flags * Transmit/receive sequencer and internal operating clock counter * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE and ICDRF flags), DDCSWR) * Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, ICSR, and DDCSWR * The value of the ICMR bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) Rev. 3.00 Mar 21, 2006 page 473 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Notes on Initialization: * Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * When initialization is executed by DDCSWR, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. * Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. * If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 4. Initialize (re-set) the IIC registers. Rev. 3.00 Mar 21, 2006 page 474 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 16.5 Interrupt Sources The IIC has interrupt sources IICI and DDCSWI. Table 16.8 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR and DDCSWR, and are sent to the interrupt controller independently. An IICI interrupt can activate the DTC to allow data transfer. Table 16.8 IIC Interrupt Sources Channel 0 Name IICI0 DDCSWI 1 IICI1 Enable Bit IEIC IE IEIC Interrupt Source I C bus interface interrupt request Format automatic switch interrupt I C bus interface interrupt request 2 2 Interrupt Flag IRIC IF IRIC DTC Activation Possible Not possible Possible Priority High Low 16.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction 2 to generate a stop condition is issued before the start condition is output to the I C bus, neither condition will be output correctly. To output the start condition followed by the stop condition, 2 after issuing the instruction that generates the start condition, read DR in each I C bus output pin, and check that SCL and SDA are both low. The pin states can be monitored by reading DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when accessing to ICDR. Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) 3. Table 16.9 shows the timing of SCL and SDA outputs in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Rev. 3.00 Mar 21, 2006 page 475 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.9 I C Bus Timing (SCL and SDA Outputs) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time Note: * tSDAHO 6tcyc when IICX is 0, 12tcyc when 1. Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28tcyc to 256tcyc 0.5tSCLO 0.5tSCLO 0.5tSCLO - 1tcyc 0.5tSCLO - 1tcyc 1tSCLO 0.5tSCLO + 2tcyc 1tSCLLO - 3tcyc 1tSCLL - (6tcyc or 12tcyc*) 3tcyc ns Unit ns ns ns ns ns ns ns ns Notes See figure 28.29. 2 4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in section 28, Electrical 2 Characteristics. Note that the I C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. 5. The I C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high2 speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds 2 the time determined by the input clock of the I C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 16.10. 2 Rev. 3.00 Mar 21, 2006 page 476 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.10 Permissible SCL Rise Time (tsr) Values Time Indication [ns] tcyc Indication 7.5 tcyc 17.5 tcyc Standard mode I C Bus Specification = (Max.) 5 MHz 1000 1000 300 100 300 2 = IICX 0 = = = 8 MHz 10 MHz 16 MHz 20 MHz 937 300 1000 300 750 300 1000 300 468 300 1000 300 375 300 875 300 High-speed mode 300 1 Standard mode 1000 High-speed mode 300 2 6. The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns 2 and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in 2 table 16.9. However, because of the rise and fall times, the I C bus interface specifications may not be satisfied at the maximum transfer rate. Table 16.11 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing 2 permits this output timing for use as slave devices connected to the I C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input 2 timing permits this output timing for use as slave devices connected to the I C bus. 2 2 Rev. 3.00 Mar 21, 2006 page 477 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.11 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] I2C Bus SpecifitSr/tSf Influence cation = = (Min.) 5 MHz 8 MHz (Max.) Standard mode -1000 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 4000 950 4750 4000 950 4750 2 Item tSCLHO tcyc Indication 0.5 tSCLO (-tSr) = = = 10 MHz 16 MHz 20 MHz 4000 950 4750 4000 950 4750 1000*1 3938*1 888* 1 4000 950 4750 1000*1 3950*1 900*1 4700 950 9000 2200 4100 1050 3550 850 3100 High-speed mode -300 tSCLLO 0.5 tSCLO (-tSf) Standard mode -250 High-speed mode -250 tBUFO 0.5 tSCLO -1 tcyc (-tSr) 0.5 tSCLO -1 tcyc (-tSf) 1 tSCLO (-tSr) Standard mode -1000 1000*1 1000*1 1000*1 3800*1 3875*1 3900*1 750* 1 High-speed mode -300 Standard mode -250 825* 1 850* 1 tSTAHO 4550 800 9000 2200 4400 1350 3100 400 1300 4625 875 9000 2200 4250 1200 3325 625 2200 4650 900 9000 2200 4200 1150 3400 700 2500 4688 938 9000 2200 4125 1075 3513 813 2950 High-speed mode -250 Standard mode -1000 tSTASO High-speed mode -300 tSTOSO 0.5 tSCLO + 2 tcyc Standard mode -1000 (-tSr) High-speed mode -300 *3 -3 t cyc tSDASO 1 tSCLLO (master) (-tSr) tSDASO (slave) Standard mode -1000 High-speed mode -300 3 1 tSCLL* Standard mode 2 -1000 -12 tcyc* (-tSr) 3 tcyc High-speed mode -300 Standard mode 0 100 0 0 -1400*1 -500*1 -200*1 600 600 375 375 300 300 250 188 188 400 150 150 tSDAHO High-speed mode 0 2 Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL - 6tcyc). 2 3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). Rev. 3.00 Mar 21, 2006 page 478 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR (ICDRR), and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been released, then read ICDR with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.30 (after confirming that the BBSY bit in ICCR has been cleared to 0). Stop condition (a) SDA SCL Internal clock BBSY bit Bit 0 8 A 9 Start condition Master receive mode ICDR read disabled period Execution of instruction for issuing stop condition (write 0 to BBSY and SCP) Confirmation of stop condition issuance (read BBSY = 0) Start condition issuance Figure 16.30 Notes on Reading Master Receive Data Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. Rev. 3.00 Mar 21, 2006 page 479 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 8. Notes on start condition issuance for retransmission Figure 16.31 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Write the transmit data to ICDR after the start condition for retransmission is issued and then the start condition is actually generated. Rev. 3.00 Mar 21, 2006 page 480 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 IRIC = 1? Yes Clear IRIC in ICSR Start condition issuance? Yes Read SCL pin SCL = Low? Yes Set BBSY = 1, SCP = 0 (ICSR) No [1] [1] Wait for end of 1-byte transfer [2] Determine whether SCL is low No Other processing [3] Issue start condition instruction for retransmission [4] Determine whether start condition is generated or not No [5] Set transmit data (slave address + R/W) [2] Note:* Program so that processing from [3] to [5] is executed continuously. [3] IRIC = 1? Yes Write transmit data to ICDR No [4] [5] Start condition generation (retransmission) SCL 9 SDA ACK bit7 IRIC [5] ICDR write (transmit data) [4] IRIC determination [1] IRIC determination [3] (Retransmission) Start condition instruction issuance [2] Determination of SCL = Low Figure 16.31 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. Rev. 3.00 Mar 21, 2006 page 481 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 9. Note on when I C bus interface stop condition instruction is issued In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low. 9th clock VIH Secures a high period 2 SCL SCL is detected as low because the rise of the waveform is delayed SDA Stop condition generation IRIC [1] SCL = low determination [2] Stop condition instruction issuance Figure 16.32 Stop Condition Issuance Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. Rev. 3.00 Mar 21, 2006 page 482 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 10. Notes on WAIT Function Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall. (1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode (2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock and the fall of the 8th clock. Error phenomenon Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the 7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally. Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall. Restrictions Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2 through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th clock. If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC counter is turned to 1 or 0, please confirm the SCL pins are in L' state after the counter value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 16.33.) Transmit/receive data 9 1 7 2 6 3 5 When BC2-0 2 IRIC clear ASD SCL BC2-BC0 IRIC (operation example) A 9 0 1 7 2 6 Transmit/receive data A 7 2 1 8 SCL = `L' confirm 0 IRIC clear 3 5 4 4 5 3 6 IRIC flag clear available IRIC flag clear available IRIC flag clear unavailable Figure 16.33 IRIC Flag Clear Timing on WAIT Operation Rev. 3.00 Mar 21, 2006 page 483 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 11. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be 2 inserted by driving the SCL pin low is used when the wait function is used in I C bust interface master mode, the IRIC flag should be cleared after determining that the SCL is low, as described below. If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time, the SDA level may change before the SCL goes low, which may generate a start or stop condition erroneously. Secures a high period SCL VIH SCL = low detected SDA IRIC [1] SCL = low determination [2] IRIC clear Figure 16.34 IRIC Flag Clearing Timing When WAIT = 1 Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. Rev. 3.00 Mar 21, 2006 page 484 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 12. Note on ICDR read and ICCR access in slave transmit mode In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 16.35. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling. To handle interrupts securely, be sure to keep either of the following conditions. Read ICDR data that has been received so far or read/write from/to ICCR before starting the receive operation of the next slave address. Monitor the BC2 to BC0 bit counter in ICMR; when the count is 000 (8th or 9th clock pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to ICCR during the time other than the shaded time. Waveform at problem occurrence ICDR write SDA R/W A Bit 7 2 SCL 8 9 TRS bit Address reception Data transmission ICDR read and ICCR read/write are disabled (6 system clock period) The rise of the 9th clock is detected Figure 16.35 ICDR Read and ICCR Access Timing in Slave Transmit Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. Rev. 3.00 Mar 21, 2006 page 485 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 13. Note on TRS bit setting in slave mode In I C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 16.36), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 16.36), the bit value is suspended and remains invalid until the rising edge of the 9th clock pulse or the stop condition is detected. Therefore, when the address is received after the restart condition is input without the stop condition, the effective TRS bit value remains 1 (transmit mode) internally and thus the acknowledge bit is not transmitted after the address has been received at the 9th clock pulse. To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in figure 16.36. To release the SCL low level that is held by means of the wait function in slave mode, clear the TRS bit to and then dummy-read ICDR. Restart condition (a) SDA (b) A 2 SCL 8 9 1 2 3 4 5 6 7 8 9 TRS Data transmission Address reception TRS bit setting is suspended in this period ICDR dummy read TRS bit setting The rise of the 9th clock is detected The rise of the 9th clock is detected Figure 16.36 TRS Bit Set Timing in Slave Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. Rev. 3.00 Mar 21, 2006 page 486 of 788 REJ09B0300-0300 Section 16 I C Bus Interface (IIC) (Optional) 2 14. Notes on Arbitration Lost in Master Mode The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX 2 register, the I C bus interface erroneously recognizes that the address call has occurred. (See figure 16.37.) In multi-master mode, a bus conflict could happen. When The I C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. * Arbitration is lost * The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data does not match DATA2 A DATA3 A 2 2 Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Data contention I2C bus interface (Slave receive mode) S SLA R/W A SLA R/W A DATA4 A * Receive address is ignored * Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device Figure 16.37 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. (a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. (b) Set the MST bit to 1. Rev. 3.00 Mar 21, 2006 page 487 of 788 REJ09B0300-0300 2 Section 16 I C Bus Interface (IIC) (Optional) 2 (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. 15. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode or write to ICDR after setting transmit mode. 16. Note on ACKE and TRS bits in slave mode In the I C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match. Similarly, if the start condition or address is transmitted from the master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt source even when the address does not match. To use the I C bus interface module in slave mode, be sure to follow the procedures below. A. When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB bit to 0. B. Set receive mode (TRS = 0) before the next start condition is input in slave mode. Complete transmit operation by the procedure shown in figure 16.24, in order to switch from slave transmit mode to slave receive mode. 16.6.1 Module Stop Mode Setting 2 2 The IIC operation can be enabled or disabled using the module stop control register. The initial setting is for the IIC operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 488 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller Section 17 Keyboard Buffer Controller This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is provided with functions conforming to the PS/2 interface specifications. Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc. Figure 17.1 shows a block diagram of the keyboard buffer controller. 17.1 Features * Conforms to PS/2 interface specifications * Direct bus drive (via the KCLK and KD pins) * Interrupt sources: on completion of data reception and on detection of clock edge * Error detection: parity error and stop bit monitoring IFKEY10A_000020020700 Rev. 3.00 Mar 21, 2006 page 489 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller Internal data bus KBBR KDI Control logic KCLKI Parity KDO KCLKO KBCRL KBCRH KCLK (PS2AC, PS2BC, PS2CC) Register counter value KBI interrupt Legend: KD: KCLK: KBBR: KBCRH: KBCRL: KBC data I/O pin KBC clock I/O pin Keyboard data buffer register Keyboard control register H Keyboard control register L Figure 17.1 Block Diagram of Keyboard Buffer Controller Rev. 3.00 Mar 21, 2006 page 490 of 788 REJ09B0300-0300 Module data bus Bus interface KD (PS2AD, PS2BD, PS2CD) Section 17 Keyboard Buffer Controller Figure 17.2 shows how the keyboard buffer controller is connected. Vcc Vcc System side KCLK in Clock KCLK out Keyboard side KCLK in KCLK out KD in KD out Data KD in KD out Keyboard buffer controller (This LSI) I/F Figure 17.2 Keyboard Buffer Controller Connection 17.2 Input/Output Pins Table 17.1 lists the input/output pins used by the keyboard buffer controller. Table 17.1 Pin Configuration Channel 0 1 2 Note: * Name KBC clock I/O pin (KCLK0) KBC data I/O pin (KD0) KBC clock I/O pin (KCLK1) KBC data I/O pin (KD1) KBC clock I/O pin (KCLK2) KBC data I/O pin (KD2) Abbreviation* PS2AC PS2AD PS2BC PS2BD PS2CC PS2CD I/O I/O I/O I/O I/O I/O I/O Function KBC clock input/output KBC data input/output KBC clock input/output KBC data input/output KBC clock input/output KBC data input/output These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK and data I/O pins as KD, omitting the channel designations. Rev. 3.00 Mar 21, 2006 page 491 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.3 Register Descriptions The keyboard buffer controller has the following registers for each channel. * Keyboard control register H (KBCRH) * Keyboard control register L (KBCRL) * Keyboard data buffer register (KBBR) 17.3.1 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer controller. Bit 7 Bit Name KBIOE Initial Value 0 R/W R/W Description Keyboard In/Out Enable Selects whether or not the keyboard buffer controller is used. 0: The keyboard buffer controller is non-operational (KCLK and KD signal pins have port functions) 1: The keyboard buffer controller is enabled for transmission and reception (KCLK and KD signal pins are in the bus drive state) 6 KCLKI 1 R Keyboard Clock In Monitors the KCLK I/O pin. This bit cannot be modified. 0: KCLK I/O pin is low 1: KCLK I/O pin is high 5 KDI 1 R Keyboard Data In Monitors the KDI I/O pin. This bit cannot be modified. 0: KD I/O pin is low 1: KD I/O pin is high 4 KBFSEL 1 R/W Keyboard Buffer Register Full Select Selects whether the KBF bit is used as the keyboard buffer register full flag or as the KCLK fall interrupt flag. When KBFSEL is cleared to 0, the KBE bit in KBCRL should be cleared to 0 to disable reception. 0: KBF bit is used as KCLK fall interrupt flag 1: KBF bit is used as keyboard buffer register full flag Rev. 3.00 Mar 21, 2006 page 492 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller Bit 3 Bit Name KBIE Initial Value 0 R/W R/W Description Keyboard Interrupt Enable Enables or disables interrupts from the keyboard buffer controller to the CPU. 0: Interrupt requests are disabled 1: Interrupt requests are enabled 2 KBF 0 R/(W)* Keyboard Buffer Register Full Indicates that data reception has been completed and the received data is in KBBR. 0: [Clearing condition] Read KBF when KBF =1, then write 0 in KBF 1: [Setting conditions] * When data has been received normally and has been transferred to KBBR while KBFSEL = 1 (keyboard buffer register full flag) When a KCLK falling edge is detected while KBFSEL = 0 (KCLK interrupt flag) * 1 PER 0 R/(W)* Parity Error Indicates that an odd parity error has occurred. 0: [Clearing condition] Read PER when PER =1, then write 0 in PER 1: [Setting condition] When an odd parity error occurs 0 KBS 0 R Keyboard Stop Indicates the receive data stop bit. Valid only when KBF = 1. 0: 0 stop bit received 1: 1 stop bit received Note: * Only 0 can be written for clearing the flag. Rev. 3.00 Mar 21, 2006 page 493 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.3.2 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer controller pin output. Bit 7 Bit Name KBE Initial Value 0 R/W R/W Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled 6 KCLKO 1 R/W Keyboard Clock Out Controls KBC clock I/O pin output. 0: KBC clock I/O pin is low 1: KBC clock I/O pin is high 5 KDO 1 R/W Keyboard Data Out Controls KBC data I/O pin output. 0: KBC data I/O pin is low 1: KBC data I/O pin is high 4 -- 1 -- Reserved This bit is always read as 1 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 494 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller Bit 3 2 1 0 Bit Name RXCR3 RXCR2 RXCR1 RXCR0 Initial Value 0 0 0 0 R/W R R R R Description Receive Counter These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized to 0000 by a reset and when 0 is written in KBE. Its value returns to 0000 after a stop bit is received. 0000: -- 0001: Start bit 0010: KB0 0011: KB1 0100: KB2 0101: KB3 0110: KB4 0111: KB5 1000: KB6 1001: KB7 1010: Parity bit 1011: -- 11- - : -- 17.3.3 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Bit 7 6 5 4 3 2 1 0 Bit Name KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Keyboard Data 7 to 0 8-bit read only data. Initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode, and when KBIOE is cleared to 0. Rev. 3.00 Mar 21, 2006 page 495 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.4 17.4.1 Operation Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4. Start Set KBIOE bit Read KBCRH KCLKI and KDI bits both 1? Yes Set KBE bit Receive enabled state [1] [2] No [1] Set the KBIOE bit to 1 in KBCRL. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, set the KBE bit (receive enabled state). [3] Detect the start bit output on the keyboard side and receive data in synchronization with the fall of KCLK. [4] When a stop bit is received, the keyboard buffer controller drives KCLK low to disable keyboard transmission (automatic I/O inhibit). If the KBIE bit is set to 1 in KBCRH, an interrupt request is sent to the CPU at the same time. [5] Perform receive data processing. [6] Clear the KBF flag to 0 in KBCRL. At the same time, the system automatically drives KCLK high, setting the receive enabled state. The receive operation can be continued by repeating steps [3] to [6]. Keyboard side in data transmission state. [3] Execute receive abort processing. KBF = 1? Yes PER = 0? Yes KBS = 1? Yes Read KBBR Receive data processing No [4] No No Error handling [5] Clear KBF flag (receive enabled state) [6] Figure 17.3 Sample Receive Processing Flowchart Rev. 3.00 Mar 21, 2006 page 496 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller Receive processing/ error handling KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KB7 to KB0 Previous data PER KBS KBF Flag cleared 1 2 0 3 1 9 7 10 11 Start bit Parity bit Stop bit Automatic I/O inhibit KB0 KB1 Receive data [1] [2] [3] [4] [5] [6] Figure 17.4 Receive Timing 17.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit processing flowchart is shown in figure 17.5, and the transmit timing in figure 17.6. Rev. 3.00 Mar 21, 2006 page 497 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller Start Set KBIOE bit Read KBCRH KCLKI and KDI bits both 1? Yes Set I/O inhibit (KCLKO = 0) KBE = 0 (KBBR reception prohibited) Wait Set start bit (KDO = 0) Set I/O inhibit (KCLKO = 1) i=0 [6] No [4] KCLKO remains at 0 [5] KDO remains at 0 [1] [2] No [3] Write 0 in the KBE bit (prohibit KBBR receive operation). 2 KDO remains at 1 (Continued on [4] Write 0 in the KDO bit (set start bit). next page) [1] Set the KBE bit to 1 in KBCRH. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, write 0 in the KCLKO bit (set I/O inhibit). [3] [5] Write 1 in the KCLKO bit (clear I/O inhibit). [6] Read KBCRH, and when KCLKI = 0, set the transmit data in the KDO bit (LSB-first). Next, set the parity bit and stop bit in the KDO bit. [7] After transmitting the stop bit, read KBCRL and confirm that KDI = 0 (receive completed notification from the keyboard). [8] Read KBCRH. Confirm that the KCLKI and KDI bits are both 1. The transmit operation can be continued by repeating steps [2] to [8]. Read KBCRH KCLKI = 0? Yes Set transmit data (KDO = D(i)) Read KBCRH KCLKI = 1? Yes i=i+1 i > 9? Yes Read KBCRH KCLKI = 1? No i = 0 to 7: Transmit data i = 8: Parity bit i = 9: Stop bit No No Yes 1 (Continued on next page) Figure 17.5 (1) Sample Transmit Processing Flowchart Rev. 3.00 Mar 21, 2006 page 498 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 1 Read KBCRH KCLKI = 0? Yes KDI = 0? * Yes [8] Read KBCRH KCLK = 1? Yes Transmit end state (KCLK = high, KD = high) No Error handling No [7] Keyboard side in data transmission state. Execute receive abort processing. No 2 To receive operation or transmit operation Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low. Figure 17.5 (2) Sample Transmit Processing Flowchart Rev. 3.00 Mar 21, 2006 page 499 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller KCLK (pin state) KD (pin state) KCLK (output) KD (output) KCLK (input) KD (input) Start bit 1 2 8 9 10 11 0 1 7 Parity bit Stop bit I/O inhibit Start bit 0 1 7 Parity bit Stop bit Receive completed notification [1] [2] [3] [4] [5] [6] [7] [8] Figure 17.6 Transmit Timing 17.4.3 Receive Abort This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds the clock low. During reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is an abort request from the system, and data transmission from the keyboard is aborted. Thus the system can abort reception by holding the clock low for a certain period. A sample receive abort processing flowchart is shown in figure 17.7, and the receive abort timing in figure 17.8. Rev. 3.00 Mar 21, 2006 page 500 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller Start [1] Read KBCRL, and if KBF = 1, perform processing 1. [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort reception. If the value of bits RXCR3 to RXCR0 is B'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation. [3] If the value of bits RXCR3 to RXCR0 is B'1001 or greater, the parity bit is being received. With the PS2 interface, a receive abort request following parity bit reception is disabled. Wait until stop bit reception is completed, perform receive data processing and clear the KBF flag, then proceed to the next operation. No Receive state Read KBCRL No KBF = 0? Yes Read KBCRH [1] Processing 1 RXCR3 to RXCR0 B'1001? Yes Disable receive abort requests [3] No [2] KCLKO = 0 (receive abort request) Retransmit command transmission (data)? Yes KBE = 0 (disable KBBR reception and clear receive counter) Set start bit (KDO = 0) Clear I/O inhibit (KCLKO = 1) Transmit data KBE = 0 (disable KBBR reception and clear receive counter) KBE = 1 (enable KB operation) Clear I/O inhibit (KCLKO = 1) To transmit operation To receive operation Figure 17.7 (1) Sample Receive Abort Processing Flowchart Rev. 3.00 Mar 21, 2006 page 501 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller Processing 1 Receive operation ends normally [1] [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 17.7 (2) Sample Receive Abort Processing Flowchart Keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period. Reception in progress KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KD (input) KD (output) Receive abort request Start bit Transmit operation Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing Rev. 3.00 Mar 21, 2006 page 502 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.4.4 KCLKI and KDI Read Timing Figure 17.9 shows the KCLKI and KDI read timing. T1 T2 * Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * The clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.9 KCLKI and KDI Read Timing Rev. 3.00 Mar 21, 2006 page 503 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.4.5 KCLKO and KDO Write Timing Figure 17.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states. T1 * Internal write signal KCLKO, KDO (register) KCLK, KD (pin state) Note: * The clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. T2 Figure 17.10 KCLKO and KDO Write Timing Rev. 3.00 Mar 21, 2006 page 504 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.4.6 KBF Setting Timing and KCLK Control Figure 17.11 shows the KBF setting timing and the KCLK pin states. * KCLK (pin) Internal KCLK Falling edge signal RXCR3 to RXCR0 KBF KCLK (output) 11th fall B'1010 B'0000 Automatic I/O inhibit Note: * The clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing Rev. 3.00 Mar 21, 2006 page 505 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.4.7 Receive Timing Figure 17.12 shows the receive timing. * KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 Internal KD (KDI) KBBR7 to KBBR0 N N+1 N+2 Note: * The clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.12 Receive Counter and KBBR Data Load Timing Rev. 3.00 Mar 21, 2006 page 506 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.4.8 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 17.13 shows the setting method and an example of operation. Start Set KBIOE KBE = 0 (KBBR reception disabled) KBFSEL = 0 KBIE = 1 (KCLK falling edge interrupts enabled) KCLK (pin state) KBF bit KCLK pin fall detected? Yes KBF = 1 (interrupt generated) Interrupt handling Clear KBF No Interrupt generated Cleared by software Interrupt generated Note: * The KBF setting timing is the same as the timing of KBF setting and KCLK automatic I/O inhibit bit generation in figure 17.11. When the KBF bit is used as the KCLK input fall interrupt flag, the automatic I/O inhibit function does not operate. Figure 17.13 Example of KCLK Input Fall Interrupt Operation Rev. 3.00 Mar 21, 2006 page 507 of 788 REJ09B0300-0300 Section 17 Keyboard Buffer Controller 17.5 17.5.1 Usage Notes KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.14 shows the timing of KBIOE setting and KCLK falling edge detection. T1 T2 KCLK (pin) Internal KCLK (KCLKI) KBIOE Falling edge signal KBFSEL KBE KBF Figure 17.14 KBIOE Setting and KCLK Falling Edge Detection Timing 17.5.2 Module Stop Mode Setting Keyboard buffer controller operation can be enabled or disabled using the module stop control register. The initial setting is for keyboard buffer controller operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 508 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Section 18 Host Interface X-Bus Interface (XBS) This LSI has an on-chip host interface (HIF) that enables connection to the ISA bus (X-BUS) and has an on-chip LPC interface. In the following text, these two host interfaces (HIFs) are referred to as XBS and LPC, respectively. The XBS provides a four-channel parallel interface between the chip's internal CPU and a host processor. Communication is carried out via seven control signals from the host processor (CS1, CS2 or ECS2, CS3, CS4, HA0, IOR, and IOW), six output signals to the host processor (GA20, HIRQ1, HIRQ11, HIRQ12, HIRQ3, and HIRQ4), and an 8-bit bidirectional command/data bus (HDB7 to HDB0). The CS1, CS2 (or ECS2), CS3 and CS4 signals select one of the four interface channels. 18.1 Features * Control of the fast GATE A20 function * Shutdown of the XBS module by the HIFSD pin * Five host interrupt requests IFHSTX0A_000020020700 Rev. 3.00 Mar 21, 2006 page 509 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Figure 18.1 shows a block diagram of the XBS. Internal interrupt signals IBF4 IBF3 IBF2 IBF1 HDB7 to HDB0 IDR_1 ODR_1 Control logic STR_1 IDR_2 ODR_2 STR_2 Host data bus CS1 CS2/ECS2 CS3 CS4 IOR IOW HA0 Host interrupt request Fast A20 gate control HICR IDR_3 ODR_3 STR_3 HIRQ1 HIRQ11 HIRQ12 HIRQ3 HIRQ4 GA20 HIFSD IDR_4 Port 4, port 8, port B ODR_4 STR_4 HICR2 Internal data bus Legend: IDR_1: IDR_2: ODR_1: ODR_2: STR_1: STR_2: HICR: Bus interface IDR_3: IDR_4: ODR_3: ODR_4: STR_3: STR_4: HICR2: Input data register_3 Input data register_4 Output data register_3 Output data register_4 Status register_3 Status register_4 Host interface control register 2 Input data register_1 Input data register_2 Output data register_1 Output data register_2 Status register_1 Status register_2 Host interface control register Figure 18.1 Block Diagram of XBS Rev. 3.00 Mar 21, 2006 page 510 of 788 REJ09B0300-0300 Module data bus Section 18 Host Interface X-Bus Interface (XBS) 18.2 Input/Output Pins Table 18.1 lists the input and output pins of the XBS module. Table 18.1 Pin Configuration Name I/O read I/O write Chip select 1 Chip select 2* Chip select 3 Chip select 4 Command/data Abbreviation IOR IOW CS1 CS2 ECS2 CS3 CS4 HA0 Port P93 P94 P95 P81 P90 PB2 PB3 P80 Input Input Input I/O Input Input Input Input Function Host interface read signal Host interface write signal Host interface chip select signal for IDR_1, ODR_1, STR_1 Host interface chip select signal for IDR_2, ODR_2, STR_2 Host interface chip select signal for IDR_3, ODR_3, STR_3 Host interface chip select signal for IDR_4, ODR_4, STR_4 Host interface address select signal In host read access, this signal selects the status registers (STR_1 to STR_4) or data registers (ODR_1 to ODR_4). In host write access to the data registers (IDR_1 to IDR_4), this signal indicates whether the host is writing a command or data. Data bus Host interrupt 11 Host interrupt 1 Host interrupt 12 Host interrupt 3 Host interrupt 4 Gate A20 HIF shutdown Note: * HDB7 to HDB0 P37 to I/O P30 HIRQ11 HIRQ1 HIRQ12 HIRQ3 HIRQ4 GA20 HIFSD P43 P44 P45 PB0 PB1 P81 P82 Output Output Output Output Output Output Input Host interface data bus Interrupt output 11 to host Interrupt output 1 to host Interrupt output 12 to host Interrupt output 3 to host Interrupt output 4 to host A20 gate control signal output Host interface shutdown control signal Selection of CS2 or ECS2 is by means of the CS2E bit in STCR and the FGA20E bit in HICR. XBS channel 2 and the CS2 pin can be used when CS2E = 1. When CS2E = 1, CS2 is used when FGA20E =0, and ECS2 is used when FGA20E = 1. In this manual, both are referred to as CS2. Rev. 3.00 Mar 21, 2006 page 511 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) 18.3 Register Descriptions XBS has the following registers. XBS registers HICR, IDR_1, IDR_2, ODR_1, ODR_2, STR_1, and STR_2 can only be accessed when the HIE bit is set to 1 in SYSCR. For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). * System control register 2 (SYSCR2) * Host interface control register (HICR) * Host interface control register 2 (HICR2) * Input data register (IDR) * Output data register (ODR) * Status register (STR) 18.3.1 System Control Register 2 (SYSCR2) SYSCR2 controls the operations of port 6 and host interface. Bit 7 6 Bit Name KWUL1 KWUL0 Initial Value 0 0 R/W R/W R/W Description Key Wakeup Level 1 and 0 Sets the port 6 input level. The input level of port-6 multiplexing pins is also changed by these settings. 00: Port 6 is in the standard input level 01: Port 6 is in input level 1 10: Port 6 is in input level 2 11: Port 6 is in input level 3 5 P6PUE 0 R/W Port 6 Input Pull-Up MOS Extra (P6PUE) Controls and selects the current specification for the port 6 input pull-up MOS. 0: Standard current specification 1: Current limited specification 4 0 Reserved Only 0 should be written to this bit. Rev. 3.00 Mar 21, 2006 page 512 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Bit 3 Bit Name SDE Initial Value 0 R/W R/W Description Shutdown Enable 0: Host interface pin shutdown function disabled 1: Host interface pin shutdown function enabled When the shutdown function is enabled, host interface pin functions can be halted, and the pins placed in the high-impedance state, according to the state of the HIFSD pin. 2 CS4E 0 R/W CS4 Enable 0: Channel 4 functions disabled 1: Channel 4 functions enabled (channel 4 pin is enabled) Enabling setting is valid when the HI12E bit is 1. 1 CS3E 0 R/W CS3 Enable 0: Channel 3 functions disabled 1: Channel 3 functions enabled (channel 3 pin is enabled) Enabling setting is valid when the HI12E bit is 1. 0 HI12E 0 R/W Host Interface Enable Bit 0: Host interface functions are disabled 1: Host interface functions are enabled (settings of bits CS2E to CS4E, FGA20E, and SDE are enabled) Enabling setting is valid in single-chip mode. Rev. 3.00 Mar 21, 2006 page 513 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) 18.3.2 Host Interface Control Register (HICR) Host Interface Control Register 2 (HICR2) HICR controls host interface channel 1 and 2 interrupts and the fast A20 gate function. HICR2 controls host interface channel 3 and 4 interrupts. * HICR Initial Value All 1 R/W Slave Host Description Reserved These bits are always read as 1 and cannot be modified. 2 IBFIE2 0 R/W Input Data Register Full Interrupt Enable 2 Enables or disables the IBF2 interrupt to the internal CPU. 0: Input data register (IDR_2) reception completed interrupt request disabled 1: Input data register (IDR_2) reception completed interrupt request enabled 1 IBFIE1 0 R/W Input Data Register Full Interrupt Enable 1 Enables or disables the IBF1 interrupt to the internal CPU. 0: Input data register (IDR_1) reception completed interrupt request disabled 1: Input data register (IDR_1) reception completed interrupt request enabled Bit Bit Name 7 to 3 Rev. 3.00 Mar 21, 2006 page 514 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Initial Value 0 R/W Slave R/W Host Description Fast A20 Gate Function Enable When P81DDR=0: 0: XBS fast A20 gate function disabled 1: Setting prohibited When P81DDR=1: 0: XBS fast A20 gate function disabled 1: XBS fast A20 gate function enabled When the fast A20 gate is disabled, the normal A20 gate can be implemented by the firmware operation of the P81 output. When the host interface (XBS) fast A20 gate function is enabled, the DDR bit for P81 must be set to 1. Therefore, the state of the P81/GA20 pin cannot be monitored by reading the DR bit for P81. A fast A20 gate function is also provided in the LPC. The state of the P81/GA20 pin can be monitored by reading the LPC's GA20 bit. Bit 0 Bit Name FGA20E Rev. 3.00 Mar 21, 2006 page 515 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) * HICR2 Initial Value All 1 R/W Slave Host Description Reserved These bits are always read as 1, and cannot be modified. 2 IBFIE4 0 R/W Input Data Register Full Interrupt Enable 4 Enables or disables the IBF4 interrupt to the internal CPU. 0: Input data register (IDR_4) reception completed interrupt request disabled 1: Input data register (IDR_4) reception completed interrupt request enabled 1 IBFIE3 0 R/W Input Data Register Full Interrupt Enable 3 Enables or disables the IBF3 interrupt to the internal CPU. 0: Input data register (IDR_3) reception completed interrupt request disabled 1: Input data register (IDR_3) reception completed interrupt request enabled 0 0 Reserved The initial value should not be changed. Bit Bit Name 7 to 3 Rev. 3.00 Mar 21, 2006 page 516 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) 18.3.3 Input Data Register (IDR) IDR is a register in which data to be input from the host processor to the slave processor (this LSI) is stored. Initial Value R/W Slave R R R R R R R R Host W W W W W W W W Description When CSn (n = 1 to 4) is low, information on the host data bus is written into IDR_n at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STR_n to indicate whether the written information is a command or data. Bit 7 6 5 4 3 2 1 0 Bit Name IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 18.3.4 Output Data Register 1 (ODR) ODR is a register in which data to be output from the slave processor (this LSI) to the host processor is stored. Initial Value R/W Slave R/W R/W R/W R/W R/W R/W R/W R/W Host R R R R R R R R Description The ODR_n contents are output on the host data bus when HA0 is low, CSn (n = 1 to 4) is low, and IOR is low. Bit 7 6 5 4 3 2 1 0 Bit Name ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Rev. 3.00 Mar 21, 2006 page 517 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) 18.3.5 Status Register (STR) STR indicates status information during host interface processing. Initial Value All 0 0 R/W Slave R/W R Host R R Description Defined by User The user can use these bits as necessary. 3 C/D Command/Data Receives the HA0 input when the host processor writes to IDR, and indicates whether IDR contains data or a command. 0: Contents of input data register (IDR) are data 1: Contents of input data register (IDR) are a command 2 1 DBU IBF 0 0 R/W R R R Defined by User The user can use these bits as necessary. Input Buffer Full This bit is an internal interrupt source to the slave processor (this LSI). The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 18.5. [Clearing Condition] 0: When the slave processor reads IDR [Setting Condition] 1: When the host processor writes to IDR 0 OBF 0 R/(W)* R Output Buffer Full [Clearing Condition] 0: When the host processor reads ODR or the slave writes 0 in the OBF bit [Setting Condition] 1: When the slave processor writes to ODR Note: * Only 0 can be written, to clear the flag. Bit Bit Name 7 to 4 DBU Rev. 3.00 Mar 21, 2006 page 518 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Table 18.2 shows the conditions for setting and clearing the STR flags. Table 18.2 Set/Clear Timing for STR Flags Flag C/D IBF* OBF Note: * Setting Condition Rising edge of host's write signal (IOW) when HA0 is high Rising edge of host's write signal (IOW) when writing to IDR1 Clearing Condition Rising edge of host's write signal (IOW) when HA0 is low Falling edge of slave's internal read signal when reading IDR1 Falling edge of slave's internal write Rising edge of host's read signal (IOR) when signal when writing to ODR1 reading ODR1 The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 18.5. 18.4 18.4.1 Operation Host Interface Activation The host interface is activated by setting the HI12E bit in SYSCR2 to 1 in single-chip mode. When the host interface is activated, all related I/O ports (data port 3, control ports 8 and 9, and host interrupt request port 4) become dedicated host interface ports. Setting the CS3E bit and CS4E bit to 1 enables the number of host interface channels to be extended to four, and makes the channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated host interface port. Rev. 3.00 Mar 21, 2006 page 519 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Table 18.3 shows HIF host interface channel selection and pin operation. Table 18.3 Host Interface Channel Selection and Pin Operation HI12E 0 1 CS2E -- 0 CS3E -- 0 CS4E -- 0 Operation Host interface functions halted Host interface channel 1 only operating Operation of channels 2 to 4 halted Pins P43, P81, P90, and PB0 to PB3 operate as I/O ports. CS2 or ECS2, CS3, and CS4 inputs do not operate. 1 Host interface channel 1 and 4 functions operating Operation of channels 2 and 3 halted Pins P43, P81, P90, PB0, and PB2 operate as I/O ports. CS2 or ECS2 and CS3 inputs do not operate. 1 0 Host interface channel 1 and 3 functions operating Operation of channels 2 and 4 halted Pins P43, P81, P90, PB1, and PB3 operate as I/O ports. CS2 or ECS2 and CS4 inputs do not operate. 1 Host interface channel 1, 3, and 4 functions operating Operation of channel 2 halted Pins P43, P81, and P90 operate as I/O ports. CS2 or ECS2 input does not operate. 1 0 0 Host interface channel 1 and 2 functions operating Operation of channels 3 and 4 halted Pins PB0 to PB3 operate as I/O ports. CS3 and CS4 inputs do not operate. 1 Host interface channel 1, 2, and 4 functions operating Operation of channel 3 halted Pins PB0 and PB2 operate as I/O ports. CS3 input does not operate. 1 0 Host interface channel 1 to 3 functions operating Operation of channel 4 halted Pins PB1 and PB3 operate as I/O ports. CS4 input does not operate. 1 Host interface channel 1 to 4 functions operating Rev. 3.00 Mar 21, 2006 page 520 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) 18.4.2 Control States Table 18.4 shows host interface operations from the HIF host, and slave (this LSI) operation. Table 18.4 Host Interface Operations from HIF Host, and Slave Operation Other than CSn 1 CSn 0 IOR 0 IOW 0 1 1 0 1 Note: n = 1 to 4 HA0 0 1 0 1 0 1 0 1 Operation Setting prohibited Setting prohibited Data read from output data register n (ODR_n) Status read from status register n (STR_n) Data written to input data register n (IDR_n) Command written to input data register n (IDR_n) Idle state Idle state 18.4.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under firmware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0). Note: * Intel microprocessor. Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor (this LSI) receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command, software copies bit 1 of the data and outputs it at the gate A20 pin. Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. When the DDR bit for P81 is set to 1, the state of the P81/GA20 pin cannot be monitored by reading the DR bit for P81. The state of the P81/GA20 pin can be monitored by reading the GA20 bit in the LPC's HICR2 register. The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host processor can manipulate the output from this pin by sending commands and data. This function is available only when register IDR1 is accessed using CS1. The slave processor (this LSI) decodes the commands input from the host processor. When an H'D1 host Rev. 3.00 Mar 21, 2006 page 521 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 18.5 lists the conditions that set and clear GA20 (P81). Figure 18.2 shows the GA20 output in flowchart form. Table 18.6 indicates the GA20 output signal values. Table 18.5 GA20 (P81) Set/Clear Timing Pin Name GA20 (P81) Setting Condition Rising edge of the host's write signal (IOW) when bit 1 of the written data is 1 and the data follows an H'D1 host command Clearing Condition Rising edge of the host's write signal (IOW) when bit 1 of the written data is 0 and the data follows an H'D1 host command Also, when bit FGA20E in HICR is cleared to 0 Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P81/GA20 Figure 18.2 GA20 Output Rev. 3.00 Mar 21, 2006 page 522 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Table 18.6 Fast A20 Gate Output Signal Internal CPU Interrupt Flag (IBF) 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 GA20 (P81) Q 1 Q (1) Q 0 Q (0) Q 1 Q (1) Q 0 Q (0) Q Q Q Q Q 1/0 Q (1/0) HA0 1 0 1 1 0 1 1 0 1/0 1 0 1/0 1 1 1 1 1 0 1 Data/Command H'D1 command 1 1 data* H'FF command H'D1 command 2 0 data* H'FF command H'D1 command 1 1 data* Command other than H'FF and H'D1 H'D1 command 2 0 data* Command other than H'FF and H'D1 H'D1 command Command other than H'D1 H'D1 command H'D1 command H'D1 command Any data H'D1 command Remarks Turn-on sequence Turn-off sequence Turn-on sequence (abbreviated form) Turn-off sequence (abbreviated form) Cancelled sequence Retriggered sequence Consecutively executed sequences Notes: 1. Arbitrary data with bit 1 set to 1. 2. Arbitrary data with bit 1 cleared to 0. 18.4.4 Host Interface Pin Shutdown Function Host interface output can be placed in the high-impedance state according to the state of the HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register when the HI12E bit is set to 1 enables the HIFSD pin. The HIF constantly monitors the HIFSD pin, and when this pin goes low, places the host interface output pins (HIRQ1, HIRQ11, HIRQ12, HIRQ3, HIRQ4, and GA20) in the high-impedance state. At the same time, the host interface input pins (CS1, CS2 or ECS2, CS3, CS4, IOW, IOR, and HA0) are disabled (fixed at the high input state internally) regardless of the pin states, and the signals of the multiplexed functions of these pins (input block) are similarly fixed internally. As a result, the host interface I/O pins (HDB7 to HDB0) also go to the highimpedance state. Rev. 3.00 Mar 21, 2006 page 523 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the highlevel state, the pins are restored to their normal operation as host interface pins. Table 18.7 shows the scope of HIF pin shutdown. Table 18.7 Scope of HIF Pin Shutdown Scope of Shutdown in Slave Mode I/O O O O O O -- Input Input Input Input Input Input Input Input I/O Output Output Output Output Output Output Input Abbreviation IOR IOW CS1 CS2 ECS2 CS3 CS4 HA0 HDB7 to HDB0 HIRQ11 HIRQ1 HIRQ12 HIRQ3 HIRQ4 GA20 HIFSD Port P93 P94 P95 P81 P90 PB2 PB3 P80 P37 to P30 P43 P44 P45 PB0 PB1 P81 P82 Selection Conditions HI12E = 1 HI12E = 1 HI12E = 1 HI12E = 1 and CS2E = 1 and FGA20E = 0 HI12E = 1 and CS2E = 1 and FGA20E = 1 HI12E = 1 and CS3E = 1 HI12E = 1 and CS4E = 1 HI12E = 1 HI12E = 1 HI12E = 1 and CS2E = 1 and P43DDR = 1 HI12E = 1 and P44DDR = 1 HI12E = 1 and P45DDR = 1 HI12E = 1 and CS3E = 1 and PB0DDR = 1 HI12E = 1 and CS4E = 1 and PB1DDR = 1 HI12E = 1 and FGA20E = 1 HI12E = 1 and SDE = 1 Legend: O: Pins shut down by shutdown function The IRQ2/ADTRG input signal is also fixed in the case of P90 shutdown, the TMCI1/HSYNCI signal in the case of P43 shutdown, and the TMRI/CSYNCI in the case of P45 shutdown. : Pins shut down only when the XBS function is selected by means of a register setting --: Pin not shut down Rev. 3.00 Mar 21, 2006 page 524 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) 18.5 18.5.1 Interrupt Sources IBF1, IBF2, IBF3, and IBF4 The host interface can issue four interrupt requests to the slave processor: IBF1 to IBF4. They are input buffer full interrupts for input data registers IDR_1 to IDR_4 respectively. Each interrupt is enabled when the corresponding enable bit is set. Table 18.8 Input Buffer Full Interrupts Interrupt IBF1 IBF2 IBF3 IBF4 Description Requested when IBFIE1 is set to 1 and IDR_1 is full Requested when IBFIE2 is set to 1 and IDR_2 is full Requested when IBFIE3 is set to 1 and IDR_3 is full Requested when IBFIE4 is set to 1 and IDR_4 is full 18.5.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 Bits P45DR to P43DR in the port 4 data register (P4DR) and bits PB1ODR and PB0ODR in the port B data register (PBODR) can be used as host interrupt request latches. When they are used as host interrupt request output, set each bit in the data direction register (DDR) of the pin to 1. The corresponding bits in P4DR are cleared to 0 by the host processor's read signal (IOR). If CS1 and HA0 are low, when IOR goes low and the host reads ODR_1, HIRQ1 and HIRQ12 are cleared to 0. If CS2 and HA0 are low, when IOR goes low and the host reads ODR_2, HIRQ11 is cleared to 0. The corresponding bit in PBODR is cleared to 0 by the host's read signal (IOR). If CS3 and HA0 are low, when IOR goes low and the host reads ODR_3, HIRQ3 is cleared to 0. If CS4 and HA0 are low, when IOR goes low and the host reads ODR_4, HIRQ4 is cleared to 0. To generate a host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In processing the interrupt, the host's interrupt handling routine reads the output data register (ODR_1, ODR_2, ODR_3, or ODR_4) and this clears the host interrupt latch to 0. Table 18.9 indicates how these bits are set and cleared. Figure 18.3 shows the processing in flowchart form. Rev. 3.00 Mar 21, 2006 page 525 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Table 18.9 HIRQ Setting/Clearing Conditions Host Interrupt Signal HIRQ11 (P43) HIRQ1 (P44) HIRQ12 (P45) HIRQ3 (PB0) HIRQ4 (PB1) Setting Condition Clearing Condition Internal CPU reads 0 from bit P43DR, then Internal CPU writes 0 in bit P43DR, or writes 1 host reads output data register_2 (ODR_2) Internal CPU reads 0 from bit P44DR, then Internal CPU writes 0 in bit P44DR, or writes 1 host reads output data register_1 (ODR_1) Internal CPU reads 0 from bit P45DR, then Internal CPU writes 0 in bit P45DR, or writes 1 host reads output data register_1 (ODR_1) Internal CPU reads 0 from bit PB0ODR, then writes 1 Internal CPU reads 0 from bit PB1ODR, then writes 1 Internal CPU writes 0 in bit PB0ODR, or host reads output data register_3 (ODR_3) Internal CPU writes 0 in bit PB1ODR, or host reads output data register_4 (ODR_4) Slave CPU Master CPU Write to ODR Write 1 to P4DR HIRQ output high HIRQ output low P4DR = 0? Yes All bytes transferred? Yes Interrupt initiation ODR read No No Hardware operations Software operations Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2) Rev. 3.00 Mar 21, 2006 page 526 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) HIRQ Setting/Clearing Conflict: If there is conflict between a P4DR or PBODR read/write by the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the host, clearing by the host is held pending during the P4DR or PBODR read/write by the CPU. P4DR or PBODR clearing is executed after completion of the read/write. 18.6 18.6.1 Usage Notes Note on Host Interface The host interface provides buffering of asynchronous data from the host processor and slave processor (this LSI), but an interface protocol must be followed to implement necessary functions and avoid data contention. For example, if the host and slave processors try to access the same input or output data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple and effective protocol. Also, if two or more of pins CS1 to CS4 are driven low simultaneously in attempting IDR or ODR access, signal contention will occur within the chip, and a through-current may result. This usage must therefore be avoided. 18.6.2 Module Stop Mode Setting XBS operation can be enabled or disabled using the module stop control register. The initial setting is for XBS operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 527 of 788 REJ09B0300-0300 Section 18 Host Interface X-Bus Interface (XBS) Rev. 3.00 Mar 21, 2006 page 528 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Section 19 Host Interface LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC module supports only I/O read cycle and I/O write cycle transfers. It is also provided with power-down functions that can control the PCI clock and shut down the host interface. 19.1 Features * Supports LPC interface I/O read cycles and I/O write cycles Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data. Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME). * Has three register sets comprising data and status registers The basic register set comprises three bytes: an input register (IDR), output register (ODR), and status register (STR). Channels 1 and 2 have fixed I/O addresses of H'60/H'64 and H'62/H'66, respectively. A fast A20 gate function is also provided. The I/O address can be set for channel 3. Sixteen bidirectional data register bytes can be manipulated in addition to the basic register set. * Supports SERIRQ Host interrupt requests are transferred serially on a single signal line (SERIRQ). On channel 1, HIRQ1 and HIRQ12 can be generated. On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated. Operation can be switched between quiet mode and continuous mode. The CLKRUN signal can be manipulated to restart the PCI clock (LCLK). * Eleven interrupt sources The LPC module can be shut down by inputting the LPCPD signal. Three pins, PME, LSMI, and LSCI, are provided for general input/output. IFHSTL0A_000020020700 Rev. 3.00 Mar 21, 2006 page 529 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Figure 19.1 shows a block diagram of the LPC. Module data bus TWR0MW TWR1-15 IDR3 IDR2 IDR1 SIRQCR0 Cycle detection SIRQCR1 CLKRUN Parallel serial conversion SERIRQ Serial parallel conversion Control logic HISEL LPCPD LFRAME Address match LRESET LCLK LAD0- LAD3 H'0060/64 H'0062/66 LADR3 LSCIE LSCIB LSCI input PB1 I/O LSMIE LSMIB LSMI input PB0 I/O PMEE PMEB PME input P80 I/O HICR0 LSCI Serial parallel conversion LSMI SYNC output TWR0SW TWR1-15 ODR3 ODR2 ODR1 STR3 STR2 STR1 PME HICR1 HICR2 HICR3 GA20 Internal interrupt control IBFI1 IBFI2 IBFI3 ERRI Two-way register 0MW Two-way register 0SW Two-way data registers 1 to 15 SERIEQ control registers 0 and 1 Host interface select register Legend: HICR0 to HICR3: LADR3H, 3L: IDR1 to IDR3: ODR1 to DOR3: STR1 to STR3: Host interface control registers 0 to 3 LPC channel 3 address register 3H and 3L Input data registers 1 to 3 Output data registers 1 to 3 Status registers 1 to 3 TWR0MW: TWR0SW: TWR1 to TWR15: SERIRQ0, 1: HISEL: Figure 19.1 Block Diagram of LPC Rev. 3.00 Mar 21, 2006 page 530 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.2 Input/Output Pins Table 19.1 lists the input and output pins of the LPC module. Table 19.1 Pin Configuration Name LPC address/ data 3 to 0 LPC frame LPC reset LPC clock Abbreviation Port I/O Function Serial (4-signal-line) transfer cycle type/address/data signals, synchronized with LCLK Transfer cycle start and forced termination signal LPC interface reset signal 33 MHz PCI clock signal Serialized host interrupt request signal, synchronized with LCLK (SMI, IRQ1, IRQ6, IRQ9 to IRQ12) General output General output General output A20 gate control signal output LCLK restart request signal in case of serial host interrupt request LPC module shutdown signal LAD3 to LAD0 P33 to P30 Input/ output LFRAME LRESET LCLK P34 P35 P36 P37 1 Input* 1 Input* Input Input/ 1 output* 12 Output* * Serialized interrupt SERIRQ request LSCI general output LSMI general output PME general output GATE A20 LPC clock run LPC power-down LSCI LSMI PME GA20 CLKRUN LPCPD PB1 PB0 P80 P81 P82 P83 12 Output* * 12 Output* * 12 Output* * Input/ 12 output* * 1 Input* Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control input/output function. 2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an external resistor is necessary to pull the signal up to VCC. Rev. 3.00 Mar 21, 2006 page 531 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.3 Register Descriptions The LPC has the following registers. The settings of XBS related bits do not affect the operation of this LSI's LPC. However, for reasons relating to the configuration of the program development tool (emulator), when the LPC is used, bit HI12E in SYSCR2 should not be set to 1. For details, see section 3.2.2, System Control Register (SYSCR), and section 18.3.1, System Control Register 2 (SYSCR2). * Host interface control register 0 (HICR0) * Host interface control register 1 (HICR1) * Host interface control register 2 (HICR2) * Host interface control register 3 (HICR3) * LPC channel 3 address registers (LADR3H, LADR3L) * Input data register 1 (IDR1) * Output data register 1 (ODR1) * Status register 1 (STR1) * Input data register 2 (IDR2) * Output data register 2 (ODR2) * Status register 2 (STR2) * Input data register 3 (IDR3) * Output data register 3 (ODR3) * Status register 3 (STR3) * Bidirectional data registers 0 to 15 (TWR0 to TWR15) * SERIRQ control register 0 (SIRQCR0) * SERIRQ control register 1 (SIRQCR1) * Host interface select register (HISEL) Rev. 3.00 Mar 21, 2006 page 532 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits that determine pin output and the internal state of the host interface, and status flags that monitor the internal state of the host interface. * HICR0 R/W Bit 7 6 5 Bit Name Initial Value Slave Host Description LPC3E LPC2E LPC1E 0 0 0 R/W R/W R/W -- -- -- LPC Enable 3 to 1 Enable or disable the host interface function in single-chip mode. When the host interface is enabled (one of the three bits is set to 1), processing for data transfer between the slave processor (this LSI) and the host processor is performed using pins LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD. * LPC3E 0: LPC channel 3 operation is disabled No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15 1: LPC channel 3 operation is enabled * LPC2E 0: LPC channel 2 operation is disabled No address (H'0062, 66) matches for IDR2, ODR2, or STR2 1: LPC channel 2 operation is enabled * LPC1E 0: LPC channel 1 operation is disabled No address (H'0060, 64) matches for IDR1, ODR1, or STR1 1: LPC channel 1 operation is enabled Rev. 3.00 Mar 21, 2006 page 533 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description FGA20E 0 R/W -- Fast A20 Gate Function Enable Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented by firmware operation of the P81 output. When the fast A20 gate function is enabled, the DDR bit for P81 must not be set to 1. 0: Fast A20 gate function disabled * * * 3 SDWNE 0 R/W -- Other function of pin P81 is enabled GA20 output internal state is initialized to 1 GA20 pin output is open-drain (external VCC pullup resistor required) 1: Fast A20 gate function enabled LPC Software Shutdown Enable Controls host interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 19.4.4, Host Interface Shutdown Function (LPCPD). 0: Normal state, LPC software shutdown setting enabled [Clearing conditions] * * * Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown release (rising edge of LPCPD signal) Hardware shutdown state when LPCPD signal is low Writing 1 after reading SDWNE = 0 1: LPC hardware shutdown state setting enabled * [Setting condition] * Rev. 3.00 Mar 21, 2006 page 534 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 2 Bit Name Initial Value Slave Host Description PMEE 0 R/W -- PME output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC When the PME output function is used, the DDR bit for P80 must not be set to 1. PMEE 0 1 1 1 LSMIE 0 R/W -- PMEB x: PME output disabled, other function of pin is enabled 0: PME output enabled, PME pin output goes to 0 level 1: PME output enabled, PME pin output is high-impedance LSMI output Enable Controls LSMI output in combination with the LSMIB bit in HICR1. LSMI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC When the LSMI output function is used, the DDR bit for PB0 must not be set to 1. LSMIE 0 1 1 LSMIB x: LSMI output disabled, other function of pin is enabled 0: LSMI output enabled, LSMI pin output goes to 0 level 1: LSMI output enabled, LSMI pin output is high-impedance Rev. 3.00 Mar 21, 2006 page 535 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description LSCIE 0 R/W -- LSCI output Enable Controls LSCI output in combination with the LSCIB bit in HICR1. LSCI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC When the LSCI output function is used, the DDR bit for PB1 must not be set to 1. LSCIE 0 1 1 Legend: X: Don't care LSCIB x: LSCI output disabled, other function of pin is enabled 0: LSCI output enabled, LSCI pin output goes to 0 level 1: LSCI output enabled, LSCI pin output is high-impedance Rev. 3.00 Mar 21, 2006 page 536 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) * HICR1 R/W Bit 7 Bit Name Initial Value Slave Host Description LPCBSY 0 R/W -- LPC Busy Indicates that the host interface is processing a transfer cycle. 0: Host interface is in transfer cycle wait state * * Bus idle, or transfer cycle not subject to processing is in progress Cycle type or address indeterminate during transfer cycle LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown Forced termination (abort) of transfer cycle subject to processing Normal termination of transfer cycle subject to processing [Clearing conditions] * * * * 1: Host interface is performing transfer cycle processing [Setting condition] Match of cycle type and address Rev. 3.00 Mar 21, 2006 page 537 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 6 Bit Name Initial Value Slave Host Description CLKREQ 0 R -- LCLK Request Indicates that the host interface's SERIRQ output is requesting a restart of LCLK. 0: No LCLK restart request [Clearing conditions] * * * * LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown SERIRQ is set to continuous mode There are no further interrupts for transfer to the host in quiet mode 1: LCLK restart request issued [Setting condition] In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped 5 IRQBSY 0 R -- SERIRQ Busy Indicates that the host interface's SERIRQ signal is engaged in transfer processing. 0: SERIRQ transfer frame wait state [Clearing conditions] * * * LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown End of SERIRQ transfer frame 1: SERIRQ transfer processing in progress [Setting condition] Start of SERIRQ transfer frame Rev. 3.00 Mar 21, 2006 page 538 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description LRSTB 0 -- -- LPC Software Reset Bit Resets the host interface. For the scope of initialization by an LPC reset, see section 19.4.4, Host Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] * * Writing 0 LPC hardware reset 1: LPC software reset state [Setting condition] Writing 1 after reading LRSTB = 0 3 SDWNB 0 R/W -- LPC Software Shutdown Bit Controls host interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 19.4.4, Host Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] * * * * Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown LPC hardware shutdown release (rising edge of LPCPD signal when SDWNE = 0) 1: LPC software shutdown state [Setting condition] Writing 1 after reading SDWNB = 0 2 PMEB 0 R/W -- PME Output Bit Controls PME output in combination with the PMEE bit. For details, refer to description on the PMEE bit in HICR0. Rev. 3.00 Mar 21, 2006 page 539 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 1 Bit Name Initial Value Slave Host Description LSMIB 0 R/W -- LSMI Output Bit Controls LSMI output in combination with the LSMIE bit. For details, refer to description on the LSMIE bit in HICR0. 0 LSCIB 0 R/W -- LSCI output Bit Controls LSCI output in combination with the LSCIE bit. For details, refer to description on the LSCIE bit in HICR0. 19.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) Bits 6 to 0 in HICR2 control interrupts from the host interface (LPC) module to the slave processor (this LSI). Bit 7 in HICR2 and HICR3 monitor host interface pin states. The pin states can be monitored regardless of the host interface operating state or the operating state of the functions that use pin multiplexing. * HICR2 R/W Bit 7 6 Bit Name Initial Value Slave Host Description GA20 LRST Undefined 0 R -- GA20 Pin Monitor LPC Reset Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware reset occurs. 0: [Clearing condition] Writing 0 after reading LRST = 1 1: [Setting condition] LRESET pin falling edge detection R/(W)* -- Rev. 3.00 Mar 21, 2006 page 540 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 5 Bit Name Initial Value Slave Host Description SDWN 0 R/(W)* -- LPC Shutdown Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware shutdown request is generated. 0: [Clearing conditions] * * Writing 0 after reading SDWN = 1 LPC hardware reset and LPC software reset 1: [Setting condition] LPCPD pin falling edge detection 4 ABRT 0 R/(W)* -- LPC Abort Interrupt Flag This bit is a flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs. 0: [Clearing conditions] * * * Writing 0 after reading ABRT = 1 LPC hardware reset and LPC software reset LPC hardware shutdown and LPC software shutdown 1: [Setting condition] LFRAME pin falling edge detection during LPC transfer cycle 3 IBFIE3 0 R/W -- IDR3 and TWR Receive Completion Interrupt Enable Enables or disables IBFI3 interrupt to the slave processor (this LSI). 0: Input data register IDR3 and TWR receive completed interrupt requests disabled 1: [When TWRIE = 0 in LADR3] Input data register (IDR3) receive completed interrupt requests enabled [When TWRIE = 1 in LADR3] Input data register (IDR3) and TWR receive completed interrupt requests enabled Rev. 3.00 Mar 21, 2006 page 541 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 2 Bit Name Initial Value Slave Host Description IBFIE2 0 R/W -- IDR2 Receive Completion Interrupt Enable Enables or disables IBFI2 interrupt to the slave processor (this LSI). 0: Input data register (IDR2) receive completed interrupt requests disabled 1: Input data register (IDR2) receive completed interrupt requests enabled 1 IBFIE1 0 R/W -- IDR1 Receive Completion Interrupt Enable Enables or disables IBFI1 interrupt to the slave processor (this LSI). 0: Input data register (IDR1) receive completed interrupt requests disabled 1: Input data register (IDR1) receive completed interrupt requests enabled 0 ERRIE 0 R/W -- Error Interrupt Enable Enables or disables ERRI interrupt to the slave processor (this LSI). 0: Error interrupt requests disabled 1: Error interrupt requests enabled Note: * Only 0 can be written to bits 6 to 4, to clear the flag. * HICR3 R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description LFRAME Undefined CLKRUN Undefined SERIRQ LRESET LPCPD PME LSMI LSCI Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R -- -- -- -- -- -- -- -- LFRAME Pin Monitor CLKRUN Pin Monitor SERIRQ Pin Monitor LRESET Pin Monitor LPCPD Pin Monitor PME Pin Monitor LSMI Pin Monitor LSCI Pin Monitor Rev. 3.00 Mar 21, 2006 page 542 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.3.3 LPC Channel 3 Address Register (LADR3) LADR3 comprises two 8-bit readable/writable registers that perform LPC channel-3 host address setting and control the operation of the bidirectional data registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1). * LADR3H Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Channel 3 Address Bits 15 to 8: When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 of LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 of LADR3 is inverted, and the values of bits 3 to 0 are ignored. Register selection according to the bits ignored in address match determination is as shown in table 19.2. * LADR3L Bit 7 6 5 4 3 2 Bit Name Initial Value R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Reserved This bit is readable/writable, however, only 0 should be written to this bit. 1 0 Bit 1 TWRE 0 0 R/W R/W Channel 3 Address Bit 1 Bidirectional Data Register Enable Enables or disables bidirectional data register operation. 0: TWR operation is disabled TWR-related I/O address match determination is halted 1: TWR operation is enabled Description Channel 3 Address Bits 7 to 3 Rev. 3.00 Mar 21, 2006 page 543 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Table 19.2 Register Selection I/O Address Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 0 0 1 Bit 4 Bit 4 0 0 1 Bit 2 0 1 0 1 0 0 1 0 0 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 0 0 1 0 0 1 Bit 0 0 0 0 0 0 1 1 0 1 1 I/O read I/O read TWR0SW read TWR1 to TWR15 read Transfer Cycle I/O write I/O write I/O read I/O read I/O write I/O write Host Register Selection IDR3 write, C/D3 0 IDR3 write, C/D3 1 ODR3 read STR3 read TWR0MW write TWR1 to TWR15 write 19.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) The IDR registers are 8-bit read-only registers for the slave processor (this LSI), and 8-bit writeonly registers for the host processor. The registers selected from the host according to the I/O address are shown in the following table. For information on IDR3 selection, see section 19.3.3, LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether the written information is a command or data. The initial values of IDR1 to IDR3 are undefined. I/O Address Bits 15 to 4 0000 0000 0110 0000 0000 0110 0000 0000 0110 0000 0000 0110 Bit 3 0 0 0 0 Bit 2 0 1 0 1 Bit 1 0 0 1 1 Bit 0 0 0 0 0 Transfer Cycle I/O write I/O write I/O write I/O write Host Register Selection IDR1 write, C/D1 0 IDR1 write, C/D1 1 IDR2 write, C/D2 0 IDR2 write, C/D2 1 Rev. 3.00 Mar 21, 2006 page 544 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) The ODR registers are 8-bit readable/writable registers for the slave processor (this LSI), and 8-bit read-only registers for the host processor. The registers selected from the host according to the I/O address are shown in the following table. For information on ODR3 selection, see section 19.3.3, LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of ODR1 to ODR3 are undefined. I/O Address Bits 15 to 4 0000 0000 0110 0000 0000 0110 Bit 3 0 0 Bit 2 0 0 Bit 1 0 1 Bit 0 0 0 Transfer Cycle I/O read I/O read Host Register Selection ODR1 read ODR2 read 19.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) The TWR registers are sixteen 8-bit readable/writable registers to both the slave processor (this LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host address and the slave address. TWR0MW is a write-only register for the host processor, and a read-only register for the slave processor, while TWR0SW is a write-only register for the slave processor and a read-only register for the host processor. When the host and slave processors begin a write, after the respective TWR0 registers have been written to, access right arbitration for simultaneous access is performed by checking the status flags to see if those writes were valid. For the registers selected from the host according to the I/O address, see section 19.3.3, LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to TWR15 are undefined. 19.3.7 Status Registers 1 to 3 (STR1 to STR3) The STR registers are 8-bit registers that indicate status information during host interface processing. Bits 3, 1, and 0 of STR1 to STR3, and bits 7 to 4 of STR3, are read-only bits for both the host processor and the slave processor (this LSI). However, only 0 can be written to bit 0 of STR1 to STR3 and bits 6 and 4 of STR3, from the slave processor (this LSI), in order to clear the flags to 0. The registers selected from the host processor according to the I/O address are shown in the following table. For information on STR3 selection, see section 19.3.3, LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host processor. The initial values of STR1 to STR3 are H'00. Rev. 3.00 Mar 21, 2006 page 545 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) I/O Address Bits 15 to 4 0000 0000 0110 0000 0000 0110 Bit 3 0 0 Bit 2 1 1 Bit 1 0 1 Bit 0 0 0 Transfer Cycle I/O read I/O read Host Register Selection STR1 read STR2 read * STR1 R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU17 DBU16 DBU15 DBU14 C/D1 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 1 DBU12 IBF1 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 19.3. 0: [Clearing condition] When the slave processor reads IDR 1: [Setting condition] When the host processor writes to IDR using I/O write cycle Defined by User The user can use these bits as necessary. Rev. 3.00 Mar 21, 2006 page 546 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description OBF1 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. Cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag. * STR2 R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU27 DBU26 DBU25 DBU24 C/D2 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 DBU22 0 R/W R Defined by User The user can use this bit as necessary. Defined by User The user can use these bits as necessary. Rev. 3.00 Mar 21, 2006 page 547 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 1 Bit Name Initial Value Slave Host Description IBF2 0 R R Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 19.3. 0: [Clearing condition] When the slave processor reads IDR 1: [Setting condition] When the host processor writes to IDR using I/O write cycle 0 OBF2 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. Cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag. Rev. 3.00 Mar 21, 2006 page 548 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) * STR3 (TWRE = 1 or SELSTR3 = 0) R/W Bit 7 Bit Name Initial Value Slave Host Description IBF3B 0 R R Bidirectional Data Register Input Buffer Full Set to 1 when the host processor writes to TWR15. This is an internal interrupt source to the slave processor (this LSI). IBF3B is cleared to 0 when the slave processor reads TWR15. 0: [Clearing condition] When the slave processor reads TWR15 1: [Setting condition] When the host processor writes to TWR15 using I/O write cycle 6 OBF3B 0 R/(W)* R Bidirectional Data Register Output Buffer Full Set to 1 when the slave processor (this LSI) writes to TWR15. OBF3B is cleared to 0 when the host processor reads TWR15. 0: [Clearing condition] When the host processor reads TWR15 using I/O read cycle, or the slave processor writes 0 to the OBF3B bit 1: [Setting condition] When the slave processor writes to TWR15 5 MWMF 0 R R Master Write Mode Flag Set to 1 when the host processor writes to TWR0. MWMF is cleared to 0 when the slave processor (this LSI) reads TWR15. 0: [Clearing condition] When the slave processor reads TWR15 1: [Setting condition] When the host processor writes to TWR0 using I/O write cycle while SWMF = 0 Rev. 3.00 Mar 21, 2006 page 549 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description SWMF 0 R/(W)* R Slave Write Mode Flag Set to 1 when the slave processor (this LSI) writes to TWR0. In the event of simultaneous writes by the master and the slave, the master write has priority. SWMF is cleared to 0 when the host reads TWR15 0: [Clearing condition] When the host processor reads TWR15 using I/O read cycle, or the slave processor writes 0 to the SWMF bit 1: [Setting condition] When the slave processor writes to TWR0 while MWMF = 0 3 C/D3 0 R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 1 DBU32 IBF3A 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 19.3. 0: [Clearing condition] When the slave processor reads IDR 1: [Setting condition] When the host processor writes to IDR using I/O write cycle Rev. 3.00 Mar 21, 2006 page 550 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description OBF3A 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. OBF3A is cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag. * STR3 (TWRE = 0 and SELSTR3 = 1) R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU37 DBU36 DBU35 DBU34 C/D3 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 DBU32 0 R/W R Defined by User The user can use this bit as necessary. Defined by User The user can use these bits as necessary. Rev. 3.00 Mar 21, 2006 page 551 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 1 Bit Name Initial Value Slave Host Description IBF3A 0 R R Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 19.3. 0: [Clearing condition] When the slave processor reads IDR 1: [Setting condition] When the host processor writes to IDR using I/O write cycle 0 OBF3A 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. OBF3A is cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag. 19.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. Rev. 3.00 Mar 21, 2006 page 552 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) * SIRQCR0 R/W Bit 7 Bit Name Initial Value Slave Host Description Q/C 0 R -- Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame). 0: Continuous mode [Clearing conditions] * * LPC hardware reset, LPC software reset Specification by SERIRQ transfer cycle stop frame 1: Quiet mode [Setting condition] Specification by SERIRQ transfer cycle stop frame. 6 SELREQ 0 R/W -- Start Frame Initiation Request Select Selects whether start frame initiation is requested when one or more interrupt requests are cleared, or when all interrupt requests are cleared, in quiet mode. 0: Start frame initiation is requested when all interrupt requests are cleared in quiet mode. 1: Start frame initiation is requested when one or more interrupt requests are cleared in quiet mode. 5 IEDIR 0 R/W -- Interrupt Enable Direct Mode Specifies whether LPC channel 2 and channel 3 SERIRQ interrupt source (SMI, IRQ6, IRQ9 to IRQ11) generation is conditional upon OBF, or is controlled only by the host interrupt enable bit. 0: Host interrupt is requested when host interrupt enable bit and corresponding OBF are both set to 1 1: Host interrupt is requested when host interrupt enable bit is set to 1 Rev. 3.00 Mar 21, 2006 page 553 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description SMIE3B 0 R/W -- Host SMI Interrupt Enable 3B Enables or disables a host SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled [Clearing conditions] * * * Writing 0 to SMIE3B LPC hardware reset, LPC software reset Clearing OBF3B to 0 (when IEDIR = 0) Host SMI interrupt request by setting OBF3B to 1 is enabled [When IEDIR = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE3B = 0 3 SMIE3A 0 R/W -- Host SMI Interrupt Enable 3A Enables or disables a host SMI interrupt request when OBF3A is set by an ODR3 write. 0: Host SMI interrupt request by OBF3A and SMIE3A is disabled [Clearing conditions] * * * Writing 0 to SMIE3A LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR = 0) Host SMI interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE3A = 0 1: [When IEDIR = 0] 1: [When IEDIR = 0] Rev. 3.00 Mar 21, 2006 page 554 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 2 Bit Name Initial Value Slave Host Description SMIE2 0 R/W -- Host SMI Interrupt Enable 2 Enables or disables a host SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled [Clearing conditions] * * * Writing 0 to SMIE2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) Host SMI interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE2 = 0 1 IRQ12E1 0 R/W -- Host IRQ12 Interrupt Enable 1 Enables or disables a host IRQ12 interrupt request when OBF1 is set by an ODR1 write. 0: Host IRQ12 interrupt request by OBF1 and IRQ12E1 is disabled [Clearing conditions] * * * Writing 0 to IRQ12E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0 1: [When IEDIR = 0] 1: Host IRQ12 interrupt request by setting OBF1 to 1 is enabled [Setting condition] Writing 1 after reading IRQ12E1 = 0 Rev. 3.00 Mar 21, 2006 page 555 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description IRQ1E1 0 R/W -- Host IRQ1 Interrupt Enable 1 Enables or disables a host IRQ1 interrupt request when OBF1 is set by an ODR1 write. 0: Host IRQ1 interrupt request by OBF1 and IRQ1E1 is disabled [Clearing conditions] * * * Writing 0 to IRQ1E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0 1: Host IRQ1 interrupt request by setting OBF1 to 1 is enabled [Setting condition] Writing 1 after reading IRQ1E1 = 0 * SIRQCR1 R/W Bit 7 Bit Name Initial Value Slave Host Description IRQ11E3 0 R/W -- Host IRQ11 Interrupt Enable 3 Enables or disables a host IRQ11 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ11 interrupt request by OBF3A and IRQ11E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR = 0) Host IRQ11 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host IRQ11 interrupt is requested. [Setting condition] Writing 1 after reading IRQ11E3 = 0 1: [When IEDIR = 0] Rev. 3.00 Mar 21, 2006 page 556 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 6 Bit Name Initial Value Slave Host Description IRQ10E3 0 R/W -- Host IRQ10 Interrupt Enable 3 Enables or disables a host IRQ10 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ10 interrupt request by OBF3A and IRQ10E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E3 LPC hardware reset, LPC software reset Clearing OB3FA to 0 (when IEDIR = 0) Host IRQ10 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host IRQ10 interrupt is requested. [Setting condition] Writing 1 after reading IRQ10E3 = 0 5 IRQ9E3 0 R/W -- Host IRQ9 Interrupt Enable 3 Enables or disables a host IRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ9 interrupt request by OBF3A and IRQ9E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR = 0) Host IRQ9 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host IRQ9 interrupt is requested. [Setting condition] Writing 1 after reading IRQ9E3 = 0 1: [When IEDIR = 0] 1: [When IEDIR = 0] Rev. 3.00 Mar 21, 2006 page 557 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description IRQ6E3 0 R/W -- Host IRQ6 Interrupt Enable 3 Enables or disables a host IRQ6 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ6 interrupt request by OBF3A and IRQ6E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR = 0) Host IRQ6 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host IRQ6 interrupt is requested. [Setting condition] Writing 1 after reading IRQ6E3 = 0 3 IRQ11E2 0 R/W -- Host IRQ11 Interrupt Enable 2 Enables or disables a host IRQ11 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ11 interrupt request by OBF2 and IRQ11E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) Host IRQ11 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host IRQ11 interrupt is requested. [Setting condition] Writing 1 after reading IRQ11E2 = 0 1: [When IEDIR = 0] 1: [When IEDIR = 0] Rev. 3.00 Mar 21, 2006 page 558 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 2 Bit Name Initial Value Slave Host Description IRQ10E2 0 R/W -- Host IRQ10 Interrupt Enable 2 Enables or disables a host IRQ10 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ10 interrupt request by OBF2 and IRQ10E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) Host IRQ10 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host IRQ10 interrupt is requested. [Setting condition] Writing 1 after reading IRQ10E2 = 0 1 IRQ9E2 0 R/W -- Host IRQ9 Interrupt Enable 2 Enables or disables a host IRQ9 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ9 interrupt request by OBF2 and IRQ9E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) Host IRQ9 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host IRQ9 interrupt is requested. [Setting condition] Writing 1 after reading IRQ9E2 = 0 1: [When IEDIR = 0] 1: [When IEDIR = 0] Rev. 3.00 Mar 21, 2006 page 559 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description IRQ6E2 0 R/W -- Host IRQ6 Interrupt Enable 2 Enables or disables a host IRQ6 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ6 interrupt request by OBF2 and IRQ6E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) 1: [When IEDIR = 0] Host IRQ6 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host IRQ6 interrupt is requested. [Setting condition] Writing 1 after reading IRQ6E2 = 0 Rev. 3.00 Mar 21, 2006 page 560 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.3.9 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and specifies the output of the host interrupt request signal of each frame. R/W Bit 7 Bit Name Initial Value Slave Host Description SELSTR3 0 W STR3 Register Function Select 3 Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. See description on STR3 in section 19.3.7, Status Registers 1 to 3 (STR1 to STR3), for details. 0: Bits 7 to 4 in STR3 are status bits of the host interface. 1: [When TWRE = 1] Bits 7 to 4 in STR3 are status bits of the host interface. [When TWRE = 0] Bits 7 to 4 in STR3 are user bits. 6 5 4 3 2 1 0 SELIRQ11 0 SELIRQ10 0 SELIRQ9 0 SELIRQ6 0 SELSMI 0 SELIRQ12 1 SELIRQ1 1 W W W W W W W -- -- -- -- -- -- -- SERIRQ Output Select Selects the pin output status of host interrupt requests (HIRQ11, HIRQ10, HIRQ9, HIRQ6, SMI, HIRQ12, and HIRQ1) of the LPC. 0: [When host interrupt request is cleared] SERIRQ pin output is in the high-impedance state. [When host interrupt request is set] SERIRQ pin output is 0. 1: [When host interrupt request is cleared] SERIRQ pin output is 0. [When host interrupt request is set] SERIRQ pin output is in the high-impedance state. Rev. 3.00 Mar 21, 2006 page 561 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.4 19.4.1 Operation Host Interface Activation The host interface is activated by setting one of bits LPC3E to LPC1E in HICR0 to 1 in singlechip mode. When the host interface is activated, the related I/O ports (ports 37 to 30, ports 83 and 82) function as dedicated host interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports 81 and 80, ports B0 and B1) to the host interface's input/output pins. Use the following procedure to activate the host interface after a reset release. 1. Read the signal line status and confirm that the LPC module can be connected. Also check that the LPC module is initialized internally. 2. When using channel 3, set LADR3 to determine the channel 3 I/O address and whether bidirectional data registers are to be used. 3. Set the enable bit (LPC3E to LPC1E) for the channel to be used. 4. Set the enable bits (GA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be used. 5. Set the selection bits for other functions (SDWNE, IEDIR). 6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF). Read IDR or TWR15 to clear IBF. 7. Set interrupt enable bits (IBFIE3 to IBFIE1, ERRIE) as necessary. 19.4.2 LPC I/O Cycles There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and bus master I/O write. Of these, the chip's LPC supports only I/O read and I/O write cycles. An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of the LPC transfer cycle has been requested. In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK. The host can be made to wait by sending back a value other than B0000 in the slave's synchronization return cycle, but with the chip's LPC a value of B0000 is always returned. Rev. 3.00 Mar 21, 2006 page 562 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) If the received address matches the host address in an LPC register (IDR, ODR, STR, TWR), the host interface enters the busy state; it returns to the idle state by output of a state count 12 turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle forced termination (abort) before state #12, registers and flags are not changed. I/O Read Cycle State Count 1 2 3 4 5 6 7 8 9 10 11 12 13 Contents Start Drive Source Host Value (3 to 0) 0000 0000 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 1111 ZZZZ 0000 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ Contents Start I/O Write Cycle Drive Source Host Value (3 to 0) 0000 0010 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ 0000 1111 ZZZZ Cycle type/direction Host Address 1 Address 2 Address 3 Address 4 Turnaround (recovery) Turnaround Synchronization Data 1 Data 2 Turnaround (recovery) Turnaround Host Host Host Host Host None Slave Slave Slave Slave None Cycle type/direction Host Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 Turnaround (recovery) Turnaround Synchronization Turnaround (recovery) Turnaround Host Host Host Host Host Host Host None Slave Slave None The timing of the LFRAME, LCLK, and LAD signals is shown in figures 19.2 and 19.3. Rev. 3.00 Mar 21, 2006 page 563 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) LCLK LFRAME LAD3-LAD0 Start Cycle type, direction, and size ADDR TAR Sync Data TAR Start Number of clocks 1 1 4 2 1 2 2 1 Figure 19.2 Typical LFRAME Timing LCLK LFRAME LAD3-LAD0 Start Cycle type, direction, and size ADDR TAR Sync Slave must stop driving Master will drive high Too many Syncs cause timeout Figure 19.3 Abort Mechanism Rev. 3.00 Mar 21, 2006 page 564 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.4.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under firmware control. The fast A20 gate function that is speeded up by hardware is enabled by setting the FGA20E bit to 1 in HICR0. Note: An Intel microprocessor Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor (this LSI) receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. At this time, firmware copies bit 1 of data following an H'D1 command and outputs it at the gate A20 pin. Fast A20 Gate Operation: The internal state of GA20 output is initialized to 1 when FGA20E = 0. When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. The state of the P81/GA20 pin can be monitored by reading the GA20 bit in HICR2. The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host processor can manipulate the output from this pin by sending commands and data. This function is only available via the IDR1 register. The host interface decodes commands input from the host. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 19.3 shows the conditions that set and clear GA20 (P81). Figure 19.4 shows the GA20 output in flowchart form. Table 19.4 indicates the GA20 output signal values. Table 19.3 GA20 (P81) Set/Clear Timing Pin Name GA20 (P81) Setting Condition When bit 1 of the data that follows an H'D1 host command is 1 Clearing Condition When bit 1 of the data that follows an H'D1 host command is 0 Rev. 3.00 Mar 21, 2006 page 565 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P81/GA20 Figure 19.4 GA20 Output Rev. 3.00 Mar 21, 2006 page 566 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Table 19.4 Fast A20 Gate Output Signals Internal CPU Interrupt Flag (IBF) 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 GA20 (P81) Q 1 Q (1) Q 0 Q (0) Q 1 Q (1) Q 0 Q (0) Q Q Q Q Q 1/0 Q (1/0) Consecutively executed sequences Retriggered sequence Cancelled sequence Turn-off sequence (abbreviated form) Turn-on sequence (abbreviated form) Turn-off sequence HA0 1 0 1 1 0 1 1 0 1/0 1 0 1/0 1 1 1 1 1 0 1 Data/Command H'D1 command 1 1 data* H'FF command H'D1 command 0 data* 2 Remarks Turn-on sequence H'FF command H'D1 command 1 1 data* Command other than H'FF and H'D1 H'D1 command 2 0 data* Command other than H'FF and H'D1 H'D1 command Command other than H'D1 H'D1 command H'D1 command H'D1 command Any data H'D1 command Notes: 1. Arbitrary data with bit 1 set to 1. 2. Arbitrary data with bit 1 cleared to 0. Rev. 3.00 Mar 21, 2006 page 567 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.4.4 Host Interface Shutdown Function (LPCPD) The host interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the software shutdown state is controlled by the SDWNB bit. In both states, the host interface enters the reset state by itself, and is no longer affected by external signals other than the LRESET and LPCPD signals. Placing the slave processor in sleep mode or software standby mode is effective in reducing current dissipation in the shutdown state. If software standby mode is set, some means must be provided for exiting software standby mode before clearing the shutdown state with the LPCPD signal. If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown state cannot be cleared at the same time as the rise of the LPCPD signal. Taking these points into consideration, the following operating procedure uses a combination of LPC software shutdown and LPC hardware shutdown. 1. Clear the SDWNE bit to 0. 2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag. 3. When an ERRI interrupt is generated by the SDWN flag, check the host interface internal status flags and perform any necessary processing. 4. Set the SDWNB bit to 1 to set LPC software standby mode. 5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB bit is cleared automatically. 6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1. 7. Place the slave processor in sleep mode or software standby mode as necessary. 8. If software standby mode has been set, exit software standby mode by some means independent of the LPC. 9. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared to 0. If the slave processor has been placed in sleep mode, the mode is exited by means of LRESET signal input, on completion of the LPC transfer cycle, or by some other means. Rev. 3.00 Mar 21, 2006 page 568 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Table 19.5 shows the scope of the host interface pin shutdown. Table 19.5 Scope of Host Interface Pin Shutdown Abbreviation LAD3 to LAD0 LFRAME LRESET LCLK SERIRQ LSCI LSMI PME GA20 CLKRUN LPCPD Port P33-P30 P34 P35 P36 P37 PB1 PB0 P80 P81 P82 P83 Scope of Shutdown O O x O O O x I/O I/O Input Input Input I/O I/O I/O I/O I/O Input Input Notes Hi-Z Hi-Z LPC hardware reset function is active Hi-Z Hi-Z Hi-Z, only when LSCIE = 1 Hi-Z, only when LSMIE = 1 Hi-Z, only when PMEE = 1 Hi-Z, only when FGA20E = 1 Hi-Z Needed to clear shutdown state Legend: O: Pin that is shutdown by the shutdown function : Pin that is shutdown only when the LPC function is selected by register setting x: Pin that is not shutdown In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order of priority of LPC shutdown and reset states is as follows. 1. System reset (reset by STBY or RES pin input, or WDT0 overflow) All register bits, including bits LPC3E to LPC1E, are initialized. 2. LPC hardware reset (reset by LRESET pin input) LRSTB, SDWNE, and SDWNB bits are cleared to 0. 3. LPC software reset (reset by LRSTB) SDWNE and SDWNB bits are cleared to 0. 4. LPC hardware shutdown SDWNB bit is cleared to 0. 5. LPC software shutdown Rev. 3.00 Mar 21, 2006 page 569 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) The scope of the initialization in each mode is shown in table 19.6. Table 19.6 Scope of Initialization in Each Host Interface Mode Items Initialized LPC transfer cycle sequencer (internal state), LPCBSY and ABRT flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and IRQBSY flags System Reset Initialized Initialized LPC Reset Initialized Initialized Initialized LPC Shutdown Initialized Initialized Retained Host interface flags Initialized (IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1 to C/D3, OBF1, OBF2, OBF3A, OBF3B, SWMF, DBU), GA20 (internal state) Host interrupt enable bits (IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3), Q/C flag, SELREQ bit LRST flag SDWN flag LRSTB bit SDWNB bit SDWNE bit Host interface operation control bits (LPC3E to LPC1E, FGA20E, LADR3, IBFIE1 to IBFIE3, PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3, SELIRQ1, SELSMI, SELIRQ6, SELIRQ9 to SELIRQ12) LRESET signal LPCPD signal LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals PME, LSMI, LSCI, GA20 signals (when function is selected) PME, LSMI, LSCI, GA20 signals (when function is not selected) Initialized Initialized Retained Initialized (0) Initialized (0) Initialized (0) Initialized (0) Initialized (0) Initialized Can be set/cleared Initialized (0) HR: 0 SR: 1 Initialized (0) Initialized (0) Retained Can be set/cleared Can be set/cleared 0 (can be set) HS: 0 SS: 1 HS: 1 SS: 0 or 1 Retained Input (port function Input Input Input Output Port function Input Input Hi-Z Hi-Z Port function Note: System reset: Reset by STBY input, RES input, or WDT overflow LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR) LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS) Rev. 3.00 Mar 21, 2006 page 570 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Figure 19.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3-LAD0 LFRAME At least 30 s At least 100 s At least 60 s LRESET Figure 19.5 Power-Down State Termination Timing Rev. 3.00 Mar 21, 2006 page 571 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 19.6. SL or H LCLK SERIRQ Drive source IRQ1 START Host controller None IRQ1 None Start frame H R T IRQ0 frame S R T IRQ1 frame S R T IRQ2 frame S R T IRQ14 frame S LCLK SERIRQ Driver None R T IRQ15 frame S R T IOCHCK frame S R T I Stop frame H R T Next cycle STOP IRQ15 None Host controller START Legend: H: Host control SL: Slave control R: Recovery T: S: I: Turnaround Sample Idle Figure 19.6 SERIRQ Timing The serialized interrupt transfer cycle frame configuration is as follows. Two of the states comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The recover state must be driven by the host or slave processor that was driving the preceding state. Rev. 3.00 Mar 21, 2006 page 572 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Serial Interrupt Transfer Cycle Frame Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Contents Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK Stop Drive Source Slave Host Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Host Number of States 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Undefined First, 1 or more idle states, then 2 or 3 states 0-driven by host 2 states: Quiet mode next 3 states: Continuous mode next Drive possible in LPC channels 2 and 3 Drive possible in LPC channels 2 and 3 Drive possible in LPC channels 2 and 3 Drive possible in LPC channel 1 Drive possible in LPC channels 2 and 3 Drive possible in LPC channel 1 Drive possible in LPC channels 2 and 3 Notes In quiet mode only, slave drive possible in first state, then next 3 states 0-driven by host There are two modes--continuous mode and quiet mode--for serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave processor with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the powerdown state. In order for a slave to transfer an interrupt request in this case, a request to restart the Rev. 3.00 Mar 21, 2006 page 573 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) clock must first be issued to the host. For details see section 19.4.6, Host Interface Clock Start Request (CLKRUN). 19.4.6 Host Interface Clock Start Request (CLKRUN) A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to the host. The timing for this operation is shown in figure 19.7. CLK 1 CLKRUN 2 3 4 5 6 Pull-up enable Drive by the slave processor Drive by the host processor Figure 19.7 Clock Start Request Timing Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a different protocol, using the PME signal, etc. Rev. 3.00 Mar 21, 2006 page 574 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) 19.5 19.5.1 Interrupt Sources IBFI1 to IBFI3, and ERRI The host interface has four interrupt requests for the slave processor (this LSI): IBF1 to IBF3, and ERRI. IBFI1 to IBFI3 are IDR receive complete interrupts for IDR1 to IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort. An interrupt request is enabled by setting the corresponding enable bit. Table 19.7 Receive Complete Interrupts and Error Interrupt Interrupt IBFI1 IBFI2 IBFI3 ERRI Description When IBFIE1 is set to 1 and IDR1 reception is completed When IBFIE2 is set to 1 and IDR2 reception is completed When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15 When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1 19.5.2 SMI, HIRQ1, HIRQ6, HIRQ9 to HIRQ12 The host interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9 to HIRQ11 can be requested from LPC channel 2 or 3. There are two ways of clearing a host interrupt request. When the IEDIR bit is cleared to 0 in SIRQCR0, host interrupt sources and LPC channels are all linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request is cleared. When the IEDIR bit is set to 1 in SIRQCR0, LPC channel 2 and 3 interrupt requests are dependent only upon the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF for channel 2 or 3 is cleared. Therefore, SMIE2, SMIE3A and SMIE3B, IRQ6E2 and IRQ6E3, IRQ9E2 and IRQ9E3, IRQ10E2 and IRQ10E3, and IRQ11E2 and IRQ11E3 lose their respective functional differences. In order to clear a host interrupt request, it is necessary to clear the host interrupt enable bit. Rev. 3.00 Mar 21, 2006 page 575 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Table 19.8 summarizes the methods of setting and clearing these bits, and figure 19.8 shows the processing flowchart. Table 19.8 HIRQ Setting and Clearing Conditions Host Interrupt HIRQ1 (independent from IEDIR) HIRQ12 (independent from IEDIR) SMI (IEDIR = 0) Setting Condition Internal CPU writes to ODR1, then reads 0 from bit IRQ1E1 and writes 1 Internal CPU writes to ODR1, then reads 0 from bit IRQ12E1 and writes 1 Internal CPU * writes to ODR2, then reads 0 from bit SMIE2 and writes 1 * writes to ODR3, then reads 0 from bit SMIE3A and writes 1 Clearing Condition Internal CPU writes 0 to bit IRQ1E1, or host reads ODR1 Internal CPU writes 0 to bit IRQ12E1, or host reads ODR1 Internal CPU * writes 0 to bit SMIE2, or host reads ODR2 * writes 0 to bit SMIE3A, or host reads ODR3 * writes to TWR15, then reads 0 from bit * writes 0 to bit SMIE3B, or host SMIE3B and writes 1 reads TWR15 SMI (IEDIR = 1) Internal CPU * reads 0 from bit SMIE2, then writes 1 Internal CPU * writes 0 to bit SMIE2 * reads 0 from bit SMIE3A, then writes 1 * writes 0 to bit SMIE3A * reads 0 from bit SMIE3B, then writes 1 * writes 0 to bit SMIE3B HIRQi (i = 6, 9 to 11) (IEDIR = 0) Internal CPU * writes to ODR2, then reads 0 from bit IRQiE2 and writes 1 * writes to ODR3, then reads 0 from bit IRQiE3 and writes 1 HIRQi (i = 6, 9 to 11) (IEDIR = 1) Internal CPU * reads 0 from bit IRQiE2, then writes 1 * reads 0 from bit IRQiE3, then writes 1 Internal CPU * writes 0 to bit IRQiE2, or host reads ODR2 * CPU writes 0 to bit IRQiE3, or host reads ODR3 Internal CPU * writes 0 to bit IRQiE2 * writes 0 to bit IRQiE3 Rev. 3.00 Mar 21, 2006 page 576 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Slave CPU Master CPU ODR1 write Interrupt initiation ODR1 read Write 1 to IRQ1E1 SERIRQ IRQ1 output SERIRQ IRQ1 source clearance No OBF1 = 0? Yes All bytes transferred? Hardware operation Yes Software operation No Figure 19.8 HIRQ Flowchart (Example of Channel 1) 19.6 19.6.1 Usage Notes Module Stop Mode Setting LPC operation can be enabled or disabled using the module stop control register. The initial setting is for LPC operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 26, Power-Down Modes. 19.6.2 Notes on Using Host Interface The host interface provides buffering of asynchronous data from the host processor and slave processor (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data contention. For example, if the host and slave processor both try to access IDR or ODR at the same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to data for which writing has finished. Rev. 3.00 Mar 21, 2006 page 577 of 788 REJ09B0300-0300 Section 19 Host Interface LPC Interface (LPC) Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to TWR15 has been obtained. Table 19.9 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3, TWR0MW, TWR0SW, and TWR1 to TWR15 when LADR3 = H'A24F and LADR3 = H'3FD0. Table 19.9 Host Address Example Register IDR3 ODR3 STR3 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 Host Address when LADR3 = H'A24F H'A24A and H'A24E H'A24A H'A24E H'A250 H'A250 H'A251 H'A252 H'A253 H'A254 H'A255 H'A256 H'A257 H'A258 H'A259 H'A25A H'A25B H'A25C H'A25D H'A25E H'A25F Host Address when LADR3 = H'3FD0 H'3FD0 and H'3FD4 H'3FD0 H'3FD4 H'3FC0 H'3FC0 H'3FC1 H'3FC2 H'3FC3 H'3FC4 H'3FC5 H'3FC6 H'3FC7 H'3FC8 H'3FC9 H'3FCA H'3FCB H'3FCC H'3FCD H'3FCE H'3FCF Rev. 3.00 Mar 21, 2006 page 578 of 788 REJ09B0300-0300 Section 20 D/A Converter Section 20 D/A Converter 20.1 Features * 8-bit resolution * Two output channels * Conversion time: Max. 10 s (when load capacitance is 20 pF) * Output voltage: 0 V to AVref * D/A output retaining function in software standby mode Module data bus Bus interface Internal data bus AVref AVCC DA1 DA0 AVSS 8-bit D/A D A D R 0 D A D R 1 D A C R Control circuit Legend: DACR : D/A control register DADR0 : D/A data register 0 DADR1 : D/A data register 1 Figure 20.1 Block Diagram of D/A Converter DAC0002A_010020020700 Rev. 3.00 Mar 21, 2006 page 579 of 788 REJ09B0300-0300 Section 20 D/A Converter 20.2 Input/Output Pins Table 20.1 summarizes the input/output pins used by the D/A converter. Table 20.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Symbol AVCC AVSS DA0 DA1 I/O Input Input Output Output Input Function Analog block power supply Analog block ground and reference voltage Channel 0 analog output Channel 1 analog output Analog block reference voltage Reference power supply pin AVref 20.3 Register Descriptions The D/A converter has the following registers. * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register (DACR) 20.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion. When analog output is permitted, D/A data register contents are converted and output to analog output pins. DADR0 and DADR1 are initialized to H'00. Rev. 3.00 Mar 21, 2006 page 580 of 788 REJ09B0300-0300 Section 20 D/A Converter 20.3.2 D/A Control Register (DACR) DACR controls D/A converter operation. Bit 7 Bit Name DAOE1 Initial Value 0 R/W R/W Description D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output DA1 is disabled 1: D/A conversion for channel 1 and analog output DA1 are enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output. 0: Analog output DA0 is disabled 1: D/A conversion for channel 0 and analog output DA0 are enabled 5 DAE 0 R/W D/A Enable Controls D/A conversion in conjunction with the DAOE0 and DAOE1 bits. When the DAE bit is cleared to 0, D/A conversion for channels 0 and 1 is controlled individually. When the DAE bit is set to 1, D/A conversion for channels 0 and 1 are controlled as one. Conversion result output is controlled by the DAOE0 and DAOE1 bits. For details, see table 20.2 below. 4 to 0 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 581 of 788 REJ09B0300-0300 Section 20 D/A Converter Table 20.2 D/A Channel Enable Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE -- 0 1 1 0 0 1 1 -- Description Disables D/A conversion Enables D/A conversion for channel 0 Disables D/A conversion for channel 1 Enables D/A conversion for channels 0 and 1 Disables D/A conversion for channel 0 Enables D/A conversion for channel 1 Enables D/A conversion for channels 0 and 1 Enables D/A conversion for channels 0 and 1 20.4 Operation The D/A converter incorporates two channels of the D/A circuits and can be converted individually. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and conversion results are output. An example of D/A conversion of channel 0 is shown below. The operation timing is shown in figure 20.2. 1. Write conversion data to DADR0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of tDCONV, conversion results are output from the analog output pin DA0. The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0. The output value is calculated by the following formula: DADR contents/256 x AVref 3. Conversion starts immediately after DADR0 is modified. After the interval of tDCONV, conversion results are output. 4. When the DAOE0 bit is cleared to 0, analog output is disabled. Rev. 3.00 Mar 21, 2006 page 582 of 788 REJ09B0300-0300 Section 20 D/A Converter DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address DADR0 Conversion data (1) Conversion data (2) DAOE0 Conversion result (2) tDCONV DA0 High impedance state tDCONV Conversion result (1) Legend: tDCONV: D/A conversion time Figure 20.2 D/A Converter Operation Example 20.5 Usage Note When this LSI enters software standby mode with D/A conversion enabled, the D/A output is retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE1, DAOE0, and DAE bits all to 0 to disable D/A output. 20.5.1 Module Stop Mode Setting D/A converter operation can be enabled or disabled using the module stop control register. The initial setting is for D/A converter operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 583 of 788 REJ09B0300-0300 Section 20 D/A Converter Rev. 3.00 Mar 21, 2006 page 584 of 788 REJ09B0300-0300 Section 21 A/D Converter Section 21 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight analog input channels and up to 16 digital input to be selected. A/D conversion for digital input is effective as a comparator in multiple input testing. 21.1 * Features * 10-bit resolution nput channels: eight analog input channels and 16 digital input channels * Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref) as an analog reference voltage. * Conversion time: 13.4 s per channel (at 10-MHz operation) * Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Software, 8-bit timer (TMR) conversion start trigger, or external trigger signal. * Interrupt request A/D conversion end interrupt (ADI) request can be generated ADCMS33A_010020020700 Rev. 3.00 Mar 21, 2006 page 585 of 788 REJ09B0300-0300 Section 21 A/D Converter A block diagram of the A/D converter is shown in figure 21.1. Module data bus Internal data bus Bus interface Successive approximations register AVCC AVref AVSS 10-bit D/A A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN0 AN1 AN2 AN3 AN4 AN5 AN6/CIN0 to CIN7 AN7/CIN8 to CIN15 ADI interrupt signal Conversion start trigger from 8-bit timer ADTRG Legend: ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D + /8 Control circuit /16 Rev. 3.00 Mar 21, 2006 page 586 of 788 REJ09B0300-0300 Multiplexer Comparator Sample-and-hold circuit Figure 21.1 Block Diagram of A/D Converter Section 21 A/D Converter 21.2 Input/Output Pins Table 21.1 summarizes the pins used by the A/D converter. The 8 analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. Expanded A/D conversion input pins (CIN0 to CIN15) can be selected with the AN6 and AN7 pins. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. Table 21.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Reference power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Expanded A/D conversion input pins 0 to 15 Symbol AVCC AVSS AVref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG CIN0 to CIN15 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion Expanded A/D conversion input (digital input) channels 0 to 15 Can be used as digital input pins Group 1 analog input pins Function Analog block power supply and reference voltage Analog block ground and reference voltage Reference voltage for A/D conversion Group 0 analog input pins Rev. 3.00 Mar 21, 2006 page 587 of 788 REJ09B0300-0300 Section 21 A/D Converter 21.3 Register Descriptions The A/D converter has the following registers. * A/D data register A (ADDRA) * A/D data register B (ADDRB) * A/D data register C (ADDRC) * A/D data register D (ADDRD) * A/D control/status register (ADCSR) * A/D control register (ADCR) * Keyboard comparator control register (KBCOMP) 21.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 21.2. The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter is 8-bit width. The upper byte can be read directly from the CPU, but the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the upper byte before lower byte or in word units. Table 21.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 AN0 An1 AN2 AN3 Group 1 AN4 AN5 AN6, or CIN0 to CIN7 AN7, or CIN8 to CIN15 A/D Data Register to Store A/D Conversion Results ADDRA ADDRB ADDRC ADDRD Rev. 3.00 Mar 21, 2006 page 588 of 788 REJ09B0300-0300 Section 21 A/D Converter 21.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W R/(W)* Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all channels specified in scan mode When 0 is written after reading ADF = 1 When DTC starts by an ADI interrupt and ADDR is read [Clearing conditions] * * 6 5 ADIE ADST 0 0 R/W R/W A/D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1 A/D Start Setting this bit to 1 starts A/D conversion. Clearing this bit to 0 stops A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. 4 SCAN 0 R/W Scan Mode Selects the A/D conversion operating mode. The setting of this bit must be made when conversion is halted (ADST = 0). 0: Single mode 1: Scan mode 3 CKS 0 R/W Clock Select Sets A/D conversion time. The input channel setting must be made when conversion is halted (ADST = 0). 0: Conversion time is 266 states (max) 1: Conversion time is 134 states (max) Switch conversion time while ADST is 0. Rev. 3.00 Mar 21, 2006 page 589 of 788 REJ09B0300-0300 Section 21 A/D Converter Bit 2 1 0 Bit Name CH2 CH1 CH0 Initial Value 0 0 0 R/W R/W R/W R/W Description Channel Select 2 to 0 Select analog input channels. The input channel setting must be made when conversion is halted (ADST = 0). When SCAN = 0: 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6, or CIN0 to CIN7 111: AN7, or CIN8 to CIN15 When SCAN = 1: 000: AN0 001: AN0 and AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4 and AN5 110: AN4 to AN6 or CIN0 to CIN7 111: AN4 to AN6 or CIN0 to CIN7, or AN7 or CIN8 to CIN15 Note: * Only 0 can be written for clearing the flag. 21.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 Enable the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 when conversion is halted (ADST = 0). 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger is disabled 10: A/D conversion start by conversion trigger from TMR is enabled 11: A/D conversion start by ADTRG pin is enabled 5 to 0 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 590 of 788 REJ09B0300-0300 Section 21 A/D Converter 21.3.4 Keyboard Comparator Control Register (KBCOMP) KBCOMP selects the CIN input channel for which A/D conversion is performed and enables or disables the comparator scan function of CIN7 to CIN0. Bit 7 6 5 4 3 Bit Name IrE IrCKS2 IrCKS1 IrCKS0 KBADE Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Keyboard A/D Enable (AN6, AN7) Selects whether channels 6 and 7 of the A/D converter are used as analog pins or digital pins, in combination with the KBCH2 to KBCH0 bits. For details, refer to description for bits 2 to 0. Analog pins of the A/D converter are set to digital pins (CIN0 to CIN7 and CIN8 to CIN15). 2 1 0 KBCH2 KBCH1 KBCH0 0 0 0 R/W R/W R/W Keyboard A/D Channel Select 2 to 0 These bits select a channel of digital input pins for A/D conversion, in combination with the KBADE bit. The input channel setting must be made while conversion is halted. Channel 6 0xxx: Selects AN6 1000: Selects CIN0 1001: Selects CIN1 1010: Selects CIN2 1011: Selects CIN3 1100: Selects CIN4 1101: Selects CIN5 1110: Selects CIN6 1111: Selects CIN7 Legend: x: Don't care Channel 7 AN7 CIN8 CIN9 CIN10 CIN11 CIN12 CIN13 CIN14 CIN15 Description These bits are related to the SCI. For details, refer to section 15.3.10, Keyboard Comparator Control Register (KBCOMP). Rev. 3.00 Mar 21, 2006 page 591 of 788 REJ09B0300-0300 Section 21 A/D Converter 21.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 21.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1, by software or an external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is automatically cleared to 0, and the A/D converter enters wait state. 21.4.2 Scan Mode Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described below. Rev. 3.00 Mar 21, 2006 page 592 of 788 REJ09B0300-0300 Section 21 A/D Converter Figure 21.2 shows the operation timing. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Figure 21.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev. 3.00 Mar 21, 2006 page 593 of 788 REJ09B0300-0300 Section 21 A/D Converter 21.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 21.3 shows the A/D conversion timing. Table 21.3 indicates the A/D conversion time. As indicated in figure 21.3, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 21.3. In scan mode, the values given in table 21.3 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 256 state (fixed) when CKS = 0 and 128 states (fixed) when CKS = 1. (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1) : ADCSR write cycle (2) : ADCSR address : A/D conversion start delay tD tSPL : Input sampling time tCONV : A/D conversion time Figure 21.3 A/D Conversion Timing Rev. 3.00 Mar 21, 2006 page 594 of 788 REJ09B0300-0300 Section 21 A/D Converter Table 21.3 A/D Conversion Time (Single Mode) CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Note: * Symbol tD tSPL tCONV min 10 -- 259 typ -- 63 -- max 17 -- 266 min 6 -- 131 CKS = 1 typ -- 31 -- max 9 -- 134 Values in the table indicate the number of states. 21.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 21.4 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 21.4 External Trigger Input Timing Rev. 3.00 Mar 21, 2006 page 595 of 788 REJ09B0300-0300 Section 21 A/D Converter 21.5 Interrupt Sources The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1 after A/D conversion is completed. 21.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 21.5). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 21.6). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 21.6). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 21.6). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 3.00 Mar 21, 2006 page 596 of 788 REJ09B0300-0300 Section 21 A/D Converter Digital output H'3FF H'3FE H'3FD H'004 H'003 H'002 H'001 H'000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 21.5 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 21.6 A/D Conversion Accuracy Definitions Rev. 3.00 Mar 21, 2006 page 597 of 788 REJ09B0300-0300 Section 21 A/D Converter 21.7 21.7.1 Usage Notes Permissible Signal Source Impedance This LSI's analog input (3-V version) is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., voltage fluctuation ratio of 5 mV/s or greater) (see figure 21.7). When converting a high-speed analog signal or converting in scan mode, a lowimpedance buffer should be inserted. For details on the 5-V version, refer to section 28, Electrical Characteristics. 21.7.2 Influences on Absolute Accuracy Adding capacitance results in coupling with ground, and therefore noise in ground may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable ground such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. This LSI Sensor output impedance to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Figure 21.7 Example of Analog Input Circuit Rev. 3.00 Mar 21, 2006 page 598 of 788 REJ09B0300-0300 Section 21 A/D Converter 21.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ANn AVref (n = 0 to 7). * Digital input voltage range The voltage applied to digital input pin CINn should be in the range AVss CINn AVref and Vss CINn Vcc (n = 0 to 15). * Relation between AVcc, AVss and Vcc, Vss For the relationship between AVcc, AVss and Vcc, Vss, set AVss = Vss. If the A/D converter is not used, the AVcc and AVss pins must on no account be left open. * AVref pin reference voltage specification range The reference voltage of the AVref pin should be in the range AVref AVcc. 21.7.4 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. 21.7.5 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference voltage (AVref) should be connected between AVcc and AVss as shown in figure 21.8. Also, the bypass capacitors connected to AVcc and AVref, and the filter capacitor connected to AN2 to AN7, must be connected to AVSS. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. Rev. 3.00 Mar 21, 2006 page 599 of 788 REJ09B0300-0300 Section 21 A/D Converter AVCC AVref *1 *1 Rin*2 100 AN0 to AN7 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 21.8 Example of Analog Input Protection Circuit 10 k AN0 to AN7 20 pF To A/D converter Note: Values are reference values. Figure 21.9 Equivalent Circuit of Analog Input Pin 21.7.6 Module Stop Mode Setting A/D converter operation can be enabled or disabled using the module stop control register. The initial setting is for A/D converter operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.00 Mar 21, 2006 page 600 of 788 REJ09B0300-0300 Section 22 RAM Section 22 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). Product Classification Flash memory version H8S/2161B H8S/2160B H8S/2141B H8S/2140B H8S/2145B H8S/2148B RAM Capacitance 4 kbytes 4 kbytes 4 kbytes 4 kbytes 8 kbytes 4 kbytes RAM Address H'E080-H'EFFF, H'FF00-H'FF7F H'E080-H'EFFF, H'FF00-H'FF7F H'E080-H'EFFF, H'FF00-H'FF7F H'E080-H'EFFF, H'FF00-H'FF7F H'D080-H'EFFF, H'FF00-H'FF7F H'E080-H'EFFF, H'FF00-H'FF7F Rev. 3.00 Mar 21, 2006 page 601 of 788 REJ09B0300-0300 Section 22 RAM Rev. 3.00 Mar 21, 2006 page 602 of 788 REJ09B0300-0300 Section 23 ROM Section 23 ROM This LSI has an on-chip flash memory. The features of the flash memory are summarized below. A block diagram of the flash memory is shown in figure 23.1. 23.1 * Size Features Product Classification H8S/2161B H8S/2160B H8S/2141B H8S/2140B H8S/2145B H8S/2148B RAM Capacitance 128 kbytes 64 kbytes 128 kbytes 64 kbytes 256 kbytes 128 kbytes RAM Address H'000000-H'01FFFF (mode 2) H'0000-H'DFFF (mode 3) H'000000-H'00FFFF (mode 2) H'0000-H'DFFF (mode 3) H'000000-H'01FFFF (mode 2) H'0000-H'DFFF (mode 3) H'000000-H'00FFFF (mode 2) H'0000-H'DFFF (mode 3) H'000000-H'03FFFF (mode 2) H'0000-H'DFFF (mode 3) H'000000-H'01FFFF (mode 2) H'0000-H'DFFF (mode 3) * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 64-kbyte version: 8 kbytes x 2 blocks, 16 kbytes x 1 block, 28 kbytes x 1 block, and 1 kbyte x 4 blocks 128-kbyte version: 32 kbytes x 2 blocks, 8 kbytes x 2 blocks, 16 kbytes x 1 block, 28 kbytes x 1 block, and 1 kbyte x 4 blocks 256-kbyte version: 64 kbytes x 3 blocks, 32 kbytes x 1 block, and 4 kbytes x 8 blocks. To erase the entire flash memory, each block must be erased in turn. * Programming/erase time It takes 10 ms (typ.) to program the flash memory 128 bytes at a time; 80 s (typ.) per 1 byte. Erasing one block takes 100 ms (typ.). ROMF254A_010020020700 Rev. 3.00 Mar 21, 2006 page 603 of 788 REJ09B0300-0300 Section 23 ROM * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * Two flash memory on-board programming modes Boot mode User program mode On-board programming/erasing can be done in boot mode in which the boot program built into the chip is started for erase or programming of the entire flash memory. In user program mode, individual blocks can be erased or programmed. * Automatic bit rate adjustment With data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. * Programmer mode In addition to on-board programming mode, programmer mode is supported to program or erase the flash memory using a PROM programmer. Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Module bus EBR1 EBR2 Bus interface/controller Operating mode Mode pin Flash memory (64/128/256 kbytes) Legend: FLMCR1 FLMCR2 EBR1 EBR2 : Flash memory control register 1 : Flash memory control register 2 : Erase block register 1 : Erase block register 2 Figure 23.1 Block Diagram of Flash Memory Rev. 3.00 Mar 21, 2006 page 604 of 788 REJ09B0300-0300 Section 23 ROM 23.2 Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 23.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 23.1. Figure 23.3 shows the boot mode and figure 23.4 shows the user program mode. MD1 =1 Reset state 0 User mode (on-chip ROM enabled) FLSHE = 0 SWE = 0 = RES RES = 0 *2 = 0 FLSHE = 1 SWE = 1 RE *1 RES = 0 S Programmer mode User program mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. MD1 = MD0 = 0, P92 = P91 = P90 = 1 2. MD1 = MD0 = 0, P92 = 0, P91 = P90 = 1 Boot mode On-board programming mode Figure 23.2 Flash Memory State Transitions Table 23.1 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Note: * Yes No Program/program-verify User Program Mode Yes Yes Program/program-verify Erase/erase-verify Should be provided by the user, in accordance with the recommended algorithm. Rev. 3.00 Mar 21, 2006 page 605 of 788 REJ09B0300-0300 Section 23 ROM 1. Initial state The flash memory is erased at shipment. The following describes how to write over an old-version application program or data in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. SCI communication check When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and SCI communication is checked. Then the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. New application program Boot program area Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. 4. Writing new application program The programming control program transferred from the host to RAM via SCI communication is executed, and the new application program in the host is written into the flash memory. New application program Boot program area Flash memory erase Programming control program Boot program area Programming control program Program execution state Figure 23.3 Boot Mode Rev. 3.00 Mar 21, 2006 page 606 of 788 REJ09B0300-0300 Section 23 ROM 1. Initial state (1) The program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer The transfer program in the flash memory is executed and the programming/erase control program is transferred to RAM. New application program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. New application program Program execution state Figure 23.4 User Program Mode (Example) Rev. 3.00 Mar 21, 2006 page 607 of 788 REJ09B0300-0300 Section 23 ROM 23.3 23.3.1 Block Configuration Block Configuration of 64-Kbyte Flash Memory Figure 23.5 shows the block configuration of 64-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 8 kbytes (2 blocks), 16 kbytes (1 block), 28 kbytes (1 block), and 1 kbyte (4 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower bits are H'00 or H'80. EB0 Erase unit: 1 kbyte H'000000 H'000380 H'000001 H'000381 H'000401 H'000002 H'000382 H'000402 Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- H'00007F H'0003FF H'00047F H'0007FF H'00087F EB1 Erase unit: 1 kbyte H'000400 H'000780 EB2 Erase unit: 1 kbyte H'000800 H'000781 H'000801 H'000782 H'000802 H'000B80 EB3 Erase unit: 1 kbyte H'000F80 EB4 Erase unit: 28 kbytes H'007F80 EB5 Erase unit: 16 kbytes H'00BF80 EB6 Erase unit: 8 kbytes H'00DF80 EB7 Erase unit: 8 kbytes H'00FF80 H'00E000 H'00C000 H'008000 H'001000 H'000C00 H'000B81 H'000C01 H'000B82 H'000C02 H'000BFF H'000C7F H'000FFF H'00107F H'007FFF H'00807F H'00BFFF H'00C07F H'00DFFF H'00E07F H'000F81 H'001001 H'007F81 H'008001 H'00BF81 H'00C001 H'00DF81 H'00E001 H'00FF81 H'000F82 H'001002 H'007F82 H'008002 H'00BF82 H'00C002 H'00DF82 H'00E002 H'00FF82 H'00FFFF Figure 23.5 64-Kbyte Flash Memory Block Configuration Rev. 3.00 Mar 21, 2006 page 608 of 788 REJ09B0300-0300 Section 23 ROM 23.3.2 Block Configuration of 128-Kbyte Flash Memory Figure 23.6 shows the block configuration of 128-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 32 kbytes (2 blocks), 8 kbytes (2 blocks), 16 kbytes (1 block), 28 kbytes (1 block), and 1 kbyte (4 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower bits are H'00 or H'80. EB0 Erase unit: 1 kbyte H'000000 H'000380 H'000001 H'000381 H'000401 H'000002 H'000382 H'000402 Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- H'00007F H'0003FF H'00407F H'0007FF H'00087F EB1 Erase unit: 1 kbyte H'000400 H'000780 EB2 Erase unit: 1 kbyte H'000800 H'000781 H'000801 H'000782 H'000802 H'000B80 EB3 Erase unit: 1 kbyte H'000F80 EB4 Erase unit: 28 kbytes H'007F80 EB5 Erase unit: 16 kbytes H'00BF80 EB6 Erase unit: 8 kbytes H'00DF80 EB7 Erase unit: 8 kbytes H'00FF80 EB8 Erase unit: 32 kbytes H'017F80 EB9 Erase unit: 32 kbytes H'01FF80 H'018000 H'010000 H'00E000 H'00C000 H'008000 H'001000 H'000C00 H'000B81 H'000C01 H'000B82 H'000C02 H'000BFF H'000C7F H'000FFF H'00107F H'007FFF H'00807F H'00BFFF H'00C07F H'00DFFF H'00E07F H'000F81 H'001001 H'007F81 H'008001 H'00BF81 H'00C001 H'00DF81 H'00E001 H'00FF81 H'010001 H'017F81 H'018001 H'01FF81 H'000F82 H'001002 H'007F82 H'008002 H'00BF82 H'00C002 H'00DF82 H'00E002 H'00FF82 H'010002 H'017F82 H'018002 H'01FF82 H'00FFFF H'01007F H'017FFF H'01807F H'01FFFF Figure 23.6 128-Kbyte Flash Memory Block Configuration Rev. 3.00 Mar 21, 2006 page 609 of 788 REJ09B0300-0300 Section 23 ROM 23.3.3 Block Configuration of 256-Kbyte Flash Memory Figure 23.7 shows the block configuration of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower bits are H'00 or H'80. EB0 Erase unit: 4 kbytes H'000F80 EB1 Erase unit: 4 kbytes H'001000 H'000F81 H'001001 H'000F82 H'001002 -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- H'000FFF H'00107F H'001FFF H'00207F H'000000 H'000001 H'000002 Programming unit: 128 bytes H'00007F H'001F80 EB2 Erase unit: 4 kbytes H'002000 H'001F81 H'002001 H'001F82 H'002002 H'002F80 EB3 Erase unit: 4 kbytes H'003F80 EB4 Erase unit: 32 kbytes H'00BF80 EB5 Erase unit: 4 kbytes H'00CF80 EB6 Erase unit: 4 kbytes H'00DF80 EB7 Erase unit: 4 kbytes H'00EF80 EB8 Erase unit: 4 kbytes H'00FF80 EB9 Erase unit: 64 kbytes H'01FF80 EB10 Erase unit: 64 kbytes H'02FF80 EB11 Erase unit: 64 kbytes H'03FF80 H'030000 H'020000 H'010000 H'00F000 H'00E000 H'00D000 H'00C000 H'004000 H'003000 H'002F81 H'003001 H'002F82 H'003002 H'002FFF H'00307F H'003FFF H'00407F H'00BFFF H'00C07F H'00CFFF H'00D07F H'00DFFF H'00E07F H'003F81 H'004001 H'00BF81 H'00C001 H'00CF81 H'00D001 H'00DF81 H'00E001 H'00EF81 H'00F001 H'00FF81 H'010001 H'01FF81 H'020001 H'02FF81 H'030001 H'03FF81 H'003F82 H'004002 H'00BF82 H'00C002 H'00CF82 H'00D002 H'00DF82 H'00E002 H'00EF82 H'00F002 H'00FF82 H'010002 H'01FF82 H'020002 H'02FF82 H'030002 H'03FF82 H'00EFFF H'00F07F H'00FFFF H'01007F H'01FFFF H'02007F H'02FFFF H'03007F H'03FFFF Figure 23.7 256-Kbyte Flash Memory Block Configuration Rev. 3.00 Mar 21, 2006 page 610 of 788 REJ09B0300-0300 Section 23 ROM 23.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 23.2. Table 23.2 Pin Configuration Pin Name RES MD1 MD0 P92 P91 P90 TxD1 RxD1 I/O Input Input Input Input Input Input Output Input Function Reset Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Serial transmit data output Serial receive data input 23.5 Register Descriptions The flash memory has the following registers. To access FLMCR1, FLMCR2, EBR1, or EBR2, the FLSHE bit in the serial/timer control register (STCR) should be set to 1. For details on the serial/timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR). * Flash memory control register 1 (FLMCR1) * Flash memory control register 2 (FLMCR2) * Erase block register 1 (EBR1) * Erase block register 2 (EBR2) 23.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1, used together with FLMCR2, makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 23.8, Flash Memory Programming/Erasing. FLMCR1 is initialized to H'80 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode. Rev. 3.00 Mar 21, 2006 page 611 of 788 REJ09B0300-0300 Section 23 ROM Bit 7 Bit Name FWE Initial Value 1 R/W R Description Flash Write Enable Controls programming/erasing of on-chip flash memory. This bit is always read as 0, and cannot be modified. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, the EV, PV, E, and P bits in this register, the ESU and PSU bits in FLMCR2, and all EBR1 and EBR2 bits cannot be set to 1. Do not clear these bits and SWE to 0 simultaneously. 5, 4 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. 3 EV 0 R/W Erase-Verify When this bit is set to 1 while SWE = 1, the flash memory transits to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1 while SWE = 1, the flash memory transits to program-verify mode. When it is cleared to 0, program-verify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory transits to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE = 1 and PSU = 1, the flash memory transits to program mode. When it is cleared to 0, program mode is cancelled. Rev. 3.00 Mar 21, 2006 page 612 of 788 REJ09B0300-0300 Section 23 ROM 23.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash memory error Indicates that an error has occurred during flash memory programming/erasing. When this bit is set to 1, flash memory goes to the error-protection state. For details, see section 23.9.3, Error Protection. 6 to 2 -- 1 ESU All 0 0 R/(W) R/W Reserved The initial values should not be modified. Erase Setup When this bit is set to 1 while SWE = 1, the flash memory transits to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit in FLMCR1 to 1. 0 PSU 0 R/W Program Setup When this bit is set to 1 while SWE = 1, the flash memory transits to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1 to 1. Rev. 3.00 Mar 21, 2006 page 613 of 788 REJ09B0300-0300 Section 23 ROM 23.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only one bit to 1 at a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0. * EBR1 (64-kbyte version) Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R/(W) Description Reserved The initial values should not be modified. * EBR2 (64-kbyte version) Bit 7 6 5 4 3 2 1 0 Note: * Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W* R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to H'00FFFF) are to be erased. When this bit is set to 1, 8 kbytes of EB6 (H'00C000 to H'00DFFF) are to be erased. When this bit is set to 1, 16 kbytes of EB5 (H'008000 to H'00BFFF) are to be erased. When this bit is set to 1, 28 kbytes of EB4 (H'001000 to H'007FFF) are to be erased. When this bit is set to 1, 1 kbyte of EB3 (H'000C00 to H'000FFF) is to be erased. When this bit is set to 1, 1 kbyte of EB2 (H'000800 to H'000BFF) is to be erased. When this bit is set to 1, 1 kbyte of EB1 (H'000400 to H'0007FF) is to be erased. When this bit is set to 1, 1 kbyte of EB0 (H'000000 to H'0003FF) is to be erased. In normal mode, this bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 614 of 788 REJ09B0300-0300 Section 23 ROM * EBR1 (128-kbyte version) Bit 7 to 2 1 0 Bit Name -- EB9 EB8 Initial Value All 0 0 0 R/W R/(W) R/W* R/W* Description Reserved The initial values should not be modified. When this bit is set to 1, 32 kbytes of EB9 (H'018000 to H'01FFFF) are to be erased. When this bit is set to 1, 32 kbytes of EB8 (H'010000 to H'017FFF) are to be erased. * EBR2 (128-kbyte version) Bit 7 6 5 4 3 2 1 0 Note: * Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W* R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to H'00FFFF) are to be erased. When this bit is set to 1, 8 kbytes of EB6 (H'00C000 to H'00DFFF) are to be erased. When this bit is set to 1, 16 kbytes of EB5 (H'008000 to H'00BFFF) are to be erased. When this bit is set to 1, 28 kbytes of EB4 (H'001000 to H'007FFF) are to be erased. When this bit is set to 1, 1 kbyte of EB3 (H'000C00 to H'000FFF) is to be erased. When this bit is set to 1, 1 kbyte of EB2 (H'000800 to H'000BFF) is to be erased. When this bit is set to 1, 1 kbyte of EB1 (H'000400 to H'0007FF) is to be erased. When this bit is set to 1, 1 kbyte of EB0 (H'000000 to H'0003FF) is to be erased. In normal mode, this bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 615 of 788 REJ09B0300-0300 Section 23 ROM * EBR1 (256-kbyte version) Bit 7 to 4 3 2 1 0 Bit Name -- EB11 EB10 EB9 EB8 Initial Value All 0 0 0 0 0 R/W R/(W) R/W* R/W* R/W* R/W* Description Reserved The initial values should not be modified. When this bit is set to 1, 64 kbytes of EB11 (H'030000 to H'03FFFF) are to be erased. When this bit is set to 1, 64 kbytes of EB10 (H'020000 to H'02FFFF) are to be erased. When this bit is set to 1, 64 kbytes of EB9 (H'010000 to H'01FFFF) are to be erased. When this bit is set to 1, 4 kbytes of EB8 (H'00F000 to H'00FFFF) are to be erased. * EBR2 (256-kbyte version) Bit 7 6 5 4 3 2 1 0 Note: * Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W* R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 4 kbytes of EB7 (H'00E000 to H'00EFFF) are to be erased. When this bit is set to 1, 4 kbytes of EB6 (H'00D000 to H'00DFFF) are to be erased. When this bit is set to 1, 4 kbytes of EB5 (H'00C000 to H'00CFFF) are to be erased. When this bit is set to 1, 32 kbytes of EB4 (H'004000 to H'00BFFF) are to be erased. When this bit is set to 1, 4 kbytes of EB3 (H'003000 to H'003FFF) is to be erased. When this bit is set to 1, 4 kbytes of EB2 (H'002000 to H'002FFF) is to be erased. When this bit is set to 1, 4 kbytes of EB1 (H'001000 to H'001FFF) is to be erased. When this bit is set to 1, 4 kbytes of EB0 (H'000000 to H'000FFF) is to be erased. In normal mode, this bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 21, 2006 page 616 of 788 REJ09B0300-0300 Section 23 ROM 23.6 Operating Modes The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits. Note that word data must start from an even address. On-chip ROM is enabled or disabled by the mode select pins (MD1 and MD0) and the EXPE bit in MDCR, as summarized in table 23.3. In normal mode (mode 3), up to 56 kbytes of ROM can be used. Table 23.3 Operating Modes and ROM Operating Modes MCU Operating Mode Mode 1 Mode 2 CPU Operating Mode Normal Advanced Advanced Mode 3 Normal Normal Mode Pins MDCR On-Chip ROM Disabled Enabled (64/128/25 6 kbytes) Enabled (56 kbytes) Mode Expanded mode with on-chip ROM disabled Single-chip mode Expanded mode with on-chip ROM enabled Single-chip mode Expanded mode with on-chip ROM enabled MD1 0 1 1 1 1 MD0 1 0 0 1 1 EXPE 1 0 1 0 1 23.7 On-Board Programming Modes An on-board programming mode is used to perform on-chip flash memory programming, erasing, and verification. This LSI has two on-board programming modes: boot mode and user program mode. Table 23.4 shows pin settings for boot mode. In user program mode, operation by software is enabled by setting control bits. For details on flash memory mode transitions, see figure 23.2. Rev. 3.00 Mar 21, 2006 page 617 of 788 REJ09B0300-0300 Section 23 ROM Table 23.4 On-Board Programming Mode Settings Mode Setting Boot mode User program mode Note: * Mode 2 (advanced mode) Mode 3 (normal mode) MD1 0 1 1 MD0 0 0 1 P92 1* P91 1* P90 1* Can be used as an I/O port after the boot mode activation. 23.7.1 Boot Mode Table 23.5 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 23.8, Flash Memory Programming/Erasing. In boot mode, if any data exists in the flash memory (except in the case that all data are 1), all blocks in the flash memory are erased. Use boot mode at initial writing in the on-board state, or forced recovery when user program mode cannot be executed because the program to be initiated in user program mode was mistakenly erased. 2. The SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, this LSI measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. This LSI then calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match that of the host. The reset should end with the RxD1 pin high. The RxD1 and TxD1 pins should be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states before this LSI is ready to measure the low-level period. 4. After matching the bit rates, this LSI transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to this LSI. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and this LSI. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 23.6. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses 1 H'FFE080 to H'FFE87F* is the area to which the programming control program is transferred from the host. Note, however, that ID codes are assigned to addresses H'FFE080 to 2 H'FFE087* . The boot program area cannot be used until the execution state in boot mode Rev. 3.00 Mar 21, 2006 page 618 of 788 REJ09B0300-0300 Section 23 ROM switches to the programming control program. Figure 23.8 shows the on-chip RAM area in boot mode. 3 6. Before branching to the programming control program (H'FFE088* in the RAM area), this LSI terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD1 pin is in high-level output state. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 4 7. Boot mode can be cleared by a reset. Cancel the reset* after driving the reset pin low, waiting at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the mode pin input levels in boot mode. If mode pin input levels are changed from low to high during reset, operating modes are switched and the state of ports that are also 5 used for address output and bus control output signals (AS, RD, and HWR) are changed* . Therefore, set these pins carefully not to be output signals during reset or not to conflict with LSI external signals. 9. All interrupts are disabled during programming or erasing of the flash memory. Notes: 1. Address area for the H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, and H8S/2161B. On the H8S/2145B, the address area is from H'FFD080 to H'FFD87F. 2. Address area for the H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, and H8S/2161B. On the H8S/2145B, the address area is from H'FFD080 to H'FFD087. 3. RAM address for the H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, and H8S/2161B. On the H8S/2145B, the address is H'FFD088. 4. After reset is cancelled, mode pin input settings must satisfy the mode programming setup time (tMDS = 4 states). 5. The ports that also have address output functions output low as address output when the mode pins are set to mode 1 during a reset. In modes other than mode 1, it enters the high impedance state. Bus control output signals output high when the mode pins are set to mode 1 during a reset. In modes other than mode 1, it enters the high impedance state. Rev. 3.00 Mar 21, 2006 page 619 of 788 REJ09B0300-0300 Section 23 ROM Table 23.5 Boot Mode Operation Item Host Operation Processing Contents Communications Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot mode start Boot program start Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 Transmits data H'55 when data H'00 is received error-free. H'00 H'55 * Measures low-level period of receive data H'00. * Calculates bit rate and sets it in BRR of SCI_1. * Transmits data H'00 to host as adjustment end indication. Receives data H'AA. Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte). H'AA After receiving data H'55, transmits data H'AA to host. Transfer of programming control program High-order byte and low-order byte Echoback H'XX Echobacks the 2-byte data received to host. Transmits 1-byte of programming control program (repeated for N times). Echoback Echobacks received data to host and also transfers it to RAM (repeated for N times). Flash memory erase Boot program erase error H'FF Receives data H'AA. H'AA Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution. Rev. 3.00 Mar 21, 2006 page 620 of 788 REJ09B0300-0300 Section 23 ROM Table 23.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate 19200 bps 9600 bps 4800 bps System Clock Frequency Range of LSI (3-V Version) 8 to 10 MHz 4 to 10 MHz 2 to 10 MHz System Clock Frequency Range of LSI (5-V Version) 8 to 20 MHz 4 to 20 MHz 2 to 18 MHz H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, and H8S/2161B H'FFE080 ID code area H'FFE088 Programming control program area (2040 bytes) H'FFE880 Boot program area* (1920 bytes) H'FFE880 H'FFD088 H'FFD080 H8S/2145B ID code area Programming control program area (6136 bytes) Boot program area* (1920 bytes) H'FFEFFF H'FFFF00 Boot program area* (128 bytes) H'FFFF7F H'FFEFFF H'FFFF00 Boot program area* (128 bytes) H'FFFF7F Note: * The boot program area and area which is not used cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the contents of the boot program area in RAM are remained after a branch is made to the programming control program. Figure 23.8 On-Chip RAM Area in Boot Mode In boot mode, this LSI checks the contents of the 8-byte ID code area as shown below to confirm that the programming control program corresponds with this LSI. To originally write a programming control program to be used in boot mode, the above 8-byte ID code must be added at the beginning of the program. Rev. 3.00 Mar 21, 2006 page 621 of 788 REJ09B0300-0300 Section 23 ROM H'FFE080 40 FE 64 66 32 31 34 39 H'FFE088 H'FFD080 H'FFD088 (Product ID) H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, or H8S/2161B Instruction codes of the programming control program 40 FE 64 66 32 31 34 35 (Product ID) H8S/2145B Instruction codes of the programming control program Figure 23.9 ID Code Area 23.7.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program which provides the user program/erase control program from external memory. Because the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as like in boot mode. Figure 23.10 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 23.8, Flash Memory Programming/Erasing. Rev. 3.00 Mar 21, 2006 page 622 of 788 REJ09B0300-0300 Section 23 ROM Reset-start No Program/erase? Yes Transfer user program/ erase control program to RAM Branch to flash memory application program Branch to user program/ erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 23.10 Programming/Erasing Flowchart Example in User Program Mode 23.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 23.8.1, Program/Program-Verify and section 23.8.2, Erase/Erase-Verify, respectively. Rev. 3.00 Mar 21, 2006 page 623 of 788 REJ09B0300-0300 Section 23 ROM 23.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 23.11 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting this LSI to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 23.11. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Figure 23.11 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. The overflow cycle should be longer than (y + z2 + + ) s. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words from the address to which a dummy write was performed. 8. The maximum number of repetitions of the program/program-verify sequence to the same bit is (N). Rev. 3.00 Mar 21, 2006 page 624 of 788 REJ09B0300-0300 Section 23 ROM Write pulse application subroutine Start of programming START Set SWE bit in FLMCR1 Wait (x) s Store 128-byte program data in program data area and reprogram data area Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR2 Wait () s Set P bit in FLMCR1 Wait (z1) s, (z2) s or (z3) s Clear P bit in FLMCR1 Wait () s Clear PSU bit in FLMCR2 Wait () s Disable WDT Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *6 *4 *6 *5 *6 n=1 m=0 Write 128-byte data in RAM reprogram data area consecutively to flash memory *1 Sub-Routine-Call *6 Apply write pulse z1 s or z2 s Set PV bit in FLMCR1 Wait () s See note 7 for pulse width *6 *6 *6 H'FF dummy write to verify address nn+1 Wait () s Read verify data Increment address *6 *2 NG m=1 NG End Sub Note: 7. Write Pulse Width Number of Writes n Write Time (z) s*6 Write data = verify data? 1 2 3 4 5 6 7 8 9 10 11 12 13 z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 OK 6n? OK Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 Transfer reprogram data to reprogram data area *4 128-byte data verification completed? 998 999 1000 z2 z2 z2 NG OK Clear PV bit in FLMCR1 Wait () s 6 n? NG Note: Use a z3 s write pulse for additional programming. *6 RAM Program data storage area (128 bytes) OK Successively write 128-byte data from additional1 programming data area in RAM to flash memory * Apply write pulse (Additional programming) z3 s *3 *6 NG NG Reprogram data storage area (128 bytes) Additional-programming data storage area (128 bytes) m=0? OK Clear SWE bit in FLMCR1 n (N)? OK Clear SWE bit in FLMCR1 Wait () s Wait () s *6 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing End of programming Programming failure fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of z1 s or z2 s is applied according to the progress of the programming operation. See note 7 for details of the pulse widths. When writing of additional-programming data is executed, a z3 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 6. The values of x, y, z1, z2, z3, , , , , , , and N are shown in sections 28.1.6 and 28.2.6, Flash Memory Characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Comments (D) (V) (X) 0 0 Programming completed 1 0 1 1 1 0 1 0 1 1 Still in erased state; no action Programming incomplete; reprogram *6 Additional-Programming Data Computation Table Reprogram Verify Data AdditionalComments Data (X') (V) Programming Data (Y) 0 0 0 Additional programming to be executed 0 1 1 1 0 1 1 1 1 Additional programming not to be executed Additional programming not to be executed Figure 23.11 Program/Program-Verify Flowchart Rev. 3.00 Mar 21, 2006 page 625 of 788 REJ09B0300-0300 Section 23 ROM 23.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 23.12 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-block specification in erase block registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately (y + z + + ) ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is N. Rev. 3.00 Mar 21, 2006 page 626 of 788 REJ09B0300-0300 Section 23 ROM START *1 Set SWE bit in FLMCR1 Wait (x) s n=1 Set EBR1 and EBR2 *2 *4 Enable WDT Set ESU bit in FLMCR2 Wait (y) s Set E bit in FLMCR1 *2 Start of erasing Wait (z) ms Clear E bit in FLMCR1 *2 End of erasing Wait () s Clear ESU bit in FLMCR2 *2 Wait () s Disable WDT Set EV bit in FLMCR1 *2 Wait () s Set block start address as verify address H'FF dummy write to verify address *2 nn+1 Wait () s Read verify data Increment address Verify data = all "1"? *2 *3 NG OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait () s Clear EV bit in FLMCR1 Wait () s *2 NG *2 *2 n (N) ? OK Clear SWE bit in FLMCR1 Wait () s NG *5 All erase blocks erased? OK Clear SWE bit in FLMCR1 Wait () s *2 End of erasing Notes: 1. 2. 3. 4. 5. Erase failure *2 Prewriting (writing 0 to all data in erased block) is not necessary. The values of x, y, z, , , , , , , and N are shown in sections 28.1.6 and 28.2.6, Flash Memory Characteristics. Verify data is read in 16-bit (word) units. Set only a single bit in EBR1 and EBR2. Do not set more than one bit. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. Figure 23.12 Erase/Erase-Verify Flowchart Rev. 3.00 Mar 21, 2006 page 627 of 788 REJ09B0300-0300 Section 23 ROM 23.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 23.9.1 Hardware Protection Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, sub-sleep mode or watch mode. Flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and erase block registers 1 and 2 (EBR1 and EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 23.9.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1 to 0. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block registers 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. 23.9.3 Error Protection In error protection, an error is detected when the CPU's runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed (transits to software standby mode, sleep mode, subactive mode, sub-sleep mode, or watch mode) during programming/erasing * When the bus ownership is released during programming/erasing Rev. 3.00 Mar 21, 2006 page 628 of 788 REJ09B0300-0300 Section 23 ROM The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be entered by setting the P or E bit to 1. However, because the PV and EV bit settings are retained, a transition to verify mode can be made. The error protection state can be cancelled by a reset or in hardware standby mode. 23.10 Interrupts during Flash Memory Programming/Erasing In order to give the highest priority to programming/erasing operations, disable all interrupts including NMI input during flash memory programming/erasing (the P or E bit in FlMCR1 is set 1 to 1) or boot program execution* . 1. If an interrupt is generated during programming/erasing, operation in accordance with the program/erase algorithm is not guaranteed. 2. CPU runaway may occur because normal vector reading cannot be performed in interrupt 2 exception handling during programming/erasing* . 3. If an interrupt occurs during boot program execution, the normal boot mode sequence cannot be executed. Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming control program has completed programming. 2. The vector may not be read correctly for the following two reasons: If flash memory is read while being programmed or erased (while the P or E bit in FLMCR1 is set to 1), correct read data will not be obtained (undefined values will be returned). If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev. 3.00 Mar 21, 2006 page 629 of 788 REJ09B0300-0300 Section 23 ROM 23.11 Programmer Mode In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports the Renesas 64/128/256-kbyte flash memory on-chip MCU device*. Figure 23.13 shows a memory map in programmer mode. Note: * For 3-V and 5-V version products, set the programming voltage of the PROM programmer to 3.3V. MCU mode H'000000 H8S/2140B and H8S/2160B Programmer mode H'00000 H8S/2141B, H8S/2148B, and H8S/2161B Programmer mode MCU mode H'000000 H'00000 On-chip ROM area On-chip ROM area H'00FFFF H'0FFFF H'01FFFF H'1FFFF Undefined value output MCU mode H'000000 H'1FFFF On-chip ROM area H8S/2145B Programmer mode H'00000 H'03FFFF H'3FFFF Figure 23.13 Memory Map in Programmer Mode Rev. 3.00 Mar 21, 2006 page 630 of 788 REJ09B0300-0300 Section 23 ROM 23.12 Usage Notes The following lists notes on the use of on-board programming modes and programmer mode. 1. Perform programming/erasing with the specified voltage and timing. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. For 3-V and 5-V version products, use a PROM programmer that supports the Renesas 64/128/256-kbyte flash memory on-chip MCU device at 3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. 2. Notes on power on/off At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 3. Perform flash memory programming/erasing in accordance with the recommended algorithm In the recommended algorithm, flash memory programming/erasing can be performed without subjecting this LSI to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1 to 1, set the watchdog timer against program runaway. 4. Do not set/clear the SWE bit during program execution in the flash memory. Do not set/clear the SWE bit during program execution in the flash memory. An interval of at least 100 s is necessary between program execution or data reading in flash memory and SWE bit clearing. When the SWE bit is set to 1, flash memory data can be modified, however, flash memory data can be read only in program-verify or erase-verify mode. Do not access the flash memory for a purpose other than verification during programming/erasing. Do not clear the SWE bit during programming, erasing, or verifying. 5. Do not use interrupts during flash memory programming/erasing In order to give the highest priority to programming/erasing operation, disable all interrupts including NMI input when the flash memory is programmed or erased. 6. Do not perform additional programming. Programming must be performed in the erased state. Program the area with 128-byte programming-unit blocks in on-board programming or programmer mode only once. Perform programming in the state where the programming-unit block is fully erased. 7. Ensure that the PROM programmer is correctly attached before programming. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 8. Do not touch the socket adapter or LSI while programming. Touching either of these can cause contact faults and write errors. Rev. 3.00 Mar 21, 2006 page 631 of 788 REJ09B0300-0300 Section 23 ROM Rev. 3.00 Mar 21, 2006 page 632 of 788 REJ09B0300-0300 Section 24 Clock Pulse Generator Section 24 Clock Pulse Generator This LSI incorporates a clock pulse generator, which generates the system clock (), bus master clock, and internal clock. The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit. Figure 24.1 shows a block diagram of the clock pulse generator. EXTAL Oscillator XTAL Duty correction circuit Clock select circuit SUB Mediumspeed clock divider /2 to /32 Bus master clock select circuit EXCL Subclock input circuit Waveform forming circuit System clock to pin WDT_1 count clock Internal clock to peripheral modules Bus master clock to CPU and DTC Figure 24.1 Block Diagram of Clock Pulse Generator The bus master clock is selected as either high-speed mode or medium-speed mode by software according to the settings of the SCK2 to SCK0 bits in the standby control register. For details on the standby control register, refer to section 26.1.1, Standby Control Register (SBYCR). The subclock input is controlled by software according to the EXCLE bit setting in the low power control register. For details on the low power control register, refer to section 26.1.2, Low-Power Control Register (LPWRCR). Rev. 3.00 Mar 21, 2006 page 633 of 788 REJ09B0300-0300 Section 24 Clock Pulse Generator 24.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator, or by providing external clock input. 24.1.1 Connecting Crystal Resonator Figure 24.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 24.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 24.3 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 24.2 should be used. A crystal resonator with frequency identical to that of the system clock () should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 24.2 Typical Connection to Crystal Resonator Table 24.1 Damping Resistance Values Frequency (MHz) Rd () 2 1k 4 500 8 200 10 0 12 0 16 0 20 0 CL L XTAL Rs EXTAL AT-cut parallel-resonance crystal resonator C0 Figure 24.3 Equivalent Circuit of Crystal Resonator Rev. 3.00 Mar 21, 2006 page 634 of 788 REJ09B0300-0300 Section 24 Clock Pulse Generator Table 24.2 Crystal Resonator Parameters Frequency (MHz) RS (max) () C0 (max) (pF) 2 500 7 4 120 7 8 80 7 10 70 7 12 60 7 16 50 7 20 40 7 24.1.2 External Clock Input Method Figure 24.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode. External clock input conditions are shown in table 24.3. The frequency of the external clock should be the same as that of the system clock (). EXTAL XTAL Open External clock input (a) Example of external clock input when XTAL pin left open EXTAL XTAL External clock input (b) Example of external clock input when an inverted clock is input to XTAL pin Figure 24.4 Example of External Clock Input Rev. 3.00 Mar 21, 2006 page 635 of 788 REJ09B0300-0300 Section 24 Clock Pulse Generator Table 24.3 External Clock Input Conditions VCC = 2.7 to 3.6 V Item External clock input pulse width low level External clock input pulse width high level External clock rising time External clock falling time Clock pulse width low level Clock pulse width high level Symbol Min tEXL 40 Max -- VCC = 5.0 V 10 % Min 20 Max -- Unit ns Test Conditions Figure 24.5 tEXH 40 -- 20 -- ns tEXr tEXf tCL tCH -- -- 0.4 80 0.4 80 10 10 0.6 -- 0.6 -- -- -- 0.4 80 0.4 80 5 5 0.6 -- 0.6 -- ns ns tcyc ns tcyc ns 5 MHz < 5 MHz 5 MHz < 5 MHz Figure 28.6 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 24.5 External Clock Input Timing The oscillator and duty correction circuit have a function to adjust the waveform of the external clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset signal should be set to low to hold it in reset state. Table 24.4 shows the external clock output stabilization delay time. Figure 24.6 shows the timing of the external clock output stabilization delay time. Rev. 3.00 Mar 21, 2006 page 636 of 788 REJ09B0300-0300 Section 24 Clock Pulse Generator Table 24.4 External Clock Output Stabilization Delay Time Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V Item External clock output stabilization delay time Note: * Symbol tDEXT* Min. 500 Max. -- Unit s Remarks Figure 24.6 tDEXT includes a RES pulse width (tRESW). VCC 2.7 V STBY VIH EXTAL (Internal and external) RES tDEXT* Note: * The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 24.6 Timing of External Clock Output Stabilization Delay Time 24.2 Duty Correction Circuit The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects the duty of a clock that is output from the oscillator, and generates the system clock (). 24.3 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock (), and generates /2, /4, /8, /16, and /32 clocks. Rev. 3.00 Mar 21, 2006 page 637 of 788 REJ09B0300-0300 Section 24 Clock Pulse Generator 24.4 Bus Master Clock Select Circuit The bus master clock select circuit selects a clock to supply the bus master with either the system clock () or medium-speed clock (/2, /4, /8, /16, or /32) by the SCK2 to SCK0 bits in SBYCR. 24.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL pin. Inputting the Subclock: To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1. Subclock input conditions are shown in table 24.5. When the subclock is not used, subclock input should not be enabled. Table 24.5 Subclock Input Conditions Vcc = 2.7 to 5.5 V Item Subclock input pulse width low level Subclock input pulse width high level Subclock input rising time Subclock input falling time Symbol tEXCLL tEXCLH tEXCLr tEXCLf Min -- -- -- -- Typ 15.26 15.26 -- -- Max -- -- 10 10 Unit s s ns ns Measurement Condition Figure 24.7 tEXCLH tEXCLL EXCL VCC x 0.5 tEXCLr tEXCLf Figure 24.7 Subclock Input Timing Rev. 3.00 Mar 21, 2006 page 638 of 788 REJ09B0300-0300 Section 24 Clock Pulse Generator When Subclock Is Not Needed: Do not enable subclock input when the subclock is not needed. Note on Subclock Usage: In transiting to power-down mode, if at least two cycles of the 32-kHz clock are not input after the 32-kHz clock input is enabled (EXCLE = 1) until the SLEEP instruction is executed (power-down mode transition), the subclock input circuit is not initialized and an error may occur in the microcomputer. Before power-down mode is entered with using the subclock, at least two cycle of the 32-kHz clock should be input after the 32-kHz clock input is enabled (EXCLE = 1). As described in the hardware manual (clock pulse generator/subclock input circuit), when the subclock is not used, the subclock input should not be enabled (EXCLE = 0). 24.6 Subclock Waveform Forming Circuit To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided clock. The sampling frequency is set by the NESEL bit in LPWRCR. The subclock is not sampled in subactive mode, subsleep mode, or watch mode. 24.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a system clock when returning from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode. A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep mode, or watch mode. At this time, modules such as the CPU, TMR_0, TMR_1, WDT_0, WDT_1, ports, and interrupt controller and their functions operate depending on the SUB. The count clock and sampling clock for each timer are divided SUB clocks. Rev. 3.00 Mar 21, 2006 page 639 of 788 REJ09B0300-0300 Section 24 Clock Pulse Generator 24.8 Processing for X1 and X2 Pins The X1 and X2 pins should be open as shown in figure 24.8. X1 Open X2 Open Figure 24.8 Processing for X1 and X2 Pins 24.9 24.9.1 Usage Notes Note on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of the resonator and installation circuit. Make sure the voltage applied to the oscillator pins does not exceed the maximum rating. 24.9.2 Notes on Board Design When using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit to prevent inductive interference with the correct oscillation as shown in figure 24.9. Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 24.9 Note on Board Design of Oscillator Circuit Section Rev. 3.00 Mar 21, 2006 page 640 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Section 25 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power dissipation is significantly reduced. In addition, there is also module stop mode in which reduced power dissipation can be achieved by individually stopping on-chip peripheral modules. * Medium-speed mode System clock frequency for the CPU operation can be selected as /2, /4, /8, /16,or /32. * Subactive mode The CPU operates based on the subclock and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 stop operating. * Sleep mode The CPU stops but on-chip peripheral modules continue operating. * Subsleep mode The CPU and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 stop operating. * Watch mode The CPU and on-chip peripheral modules other than WDT_1 stop operating. * Software standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating. * Hardware standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state. * Module stop mode Independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually. 25.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * Standby control register (SBYCR) * Low power control register (LPWRCR) * Module stop control register H (MSTPCRH) * Module stop control register L (MSTPCRL) Rev. 3.00 Mar 21, 2006 page 641 of 788 REJ09B0300-0300 Section 25 Power-Down Modes 25.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Bit 7 Bit Name Initial Value R/W SSBY 0 R/W Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode, subactive mode, or watch mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode 1: Shifts to watch mode or high-speed mode Note that the SSBY bit is not changed even if a mode transition occurs by an interrupt. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 Selects the wait time for clock stabilization from clock oscillation start when canceling software standby mode, watch mode, or subactive mode. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. Table 25.1 shows the relationship between the STS2 to STS0 values and wait time. With an external clock, there are no specific wait requirements. Normally the minimum value is recommended. 3 0 R Reserved This bit is always read as 0, and cannot be modified. Rev. 3.00 Mar 21, 2006 page 642 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Bit 2 1 0 Bit Name Initial Value R/W SCK2 SCK1 SCK0 0 0 0 R/W R/W R/W Description System Clock Select 2 to 0 Selects a clock for the bus master in high-speed mode or medium-speed mode. When making a transition to subactive mode or watch mode, SCK2 to SCK0 must be cleared to B'000. 000: High-speed mode 001: Medium-speed clock: /2 010: Medium-speed clock: /4 011: Medium-speed clock: /8 100: Medium-speed clock: /16 101: Medium-speed clock: /32 11X: -- Legend: X: Don't care Table 25.1 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8192 states 16384 states 32768 states 65536 states 20 MHz 10 MHz 8 MHz 0.4 0.8 2.0 4.1 0.8 1.6 3.3 6.6 13.1 26.2 1.6 1.0 2.0 4.1 8.2 16.4 32.8 2.0 6 MHz 1.3 2.7 5.5 10.9 21.8 43.6 2.7 4 MHz 2.0 4.1 8.2 16.4 32.8 65.6 4.0 2 MHz 4.1 8.2 16.4 32.8 65.5 131.2 8.0 s Unit ms 131072 states 8.2 262144 states 16.4 Reserved 16 states* 0.8 Shaded cells indicate the recommended specification. Note: * This setting cannot be made in the flash-memory version of this LSI. Rev. 3.00 Mar 21, 2006 page 643 of 788 REJ09B0300-0300 Section 25 Power-Down Modes 25.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit 7 Bit Name Initial Value R/W DTON 0 R/W Description Direct Transfer On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts directly to subactive mode, or shifts to sleep mode or software standby mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode or watch mode 1: Shifts directly to high-speed mode, or shifts to subsleep mode 6 LSON 0 R/W Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts to watch mode or subactive mode When the SLEEP instruction is executed in subactive mode: 0: Shifts directly to watch mode or high-speed mode 1: Shifts to subsleep mode or watch mode When watch mode is cancelled: 0: Shifts to high-speed mode 1: Shifts to subactive mode Rev. 3.00 Mar 21, 2006 page 644 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Bit 5 Bit Name Initial Value R/W NESEL 0 R/W Description Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (SUB) input from the EXCL pin is sampled using the clock () generated by the system clock pulse generator. Clear this bit to 0 when is 5 MHz or more. 0: Sampling using /32 clock 1: Sampling using /4 clock 4 EXCLE 0 R/W Subclock Input Enable Enables/disables subclock input from the EXCL pin. 0: Disables subclock input from the EXCL pin 1: Enables subclock input from the EXCL pin 3 0 R/W Reserved An undefined value is read from this bit. This bit should not be set to 1. 2 to 0 All 0 R Reserved These bits are always read as 0 and cannot be modified. 25.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCRH and MSTPCRL specify on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. * MSTPCRH Bit 7 6 5 4 3 2 1 0 Note: Bit Name MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 * Initial Value 0* 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Data transfer controller (DTC) 16-bit free-running timer (FRT) 8-bit timers (TMR_0, TMR_1) 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX) D/A converter A/D converter 8-bit timers (TMR_X, TMR_Y), timer connection Corresponding Module Do not set this bit to 1. Rev. 3.00 Mar 21, 2006 page 645 of 788 REJ09B0300-0300 Section 25 Power-Down Modes * MSTPCRL Bit 7 6 5 4 3 2 Bit Name MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 Initial Value 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W Corresponding Module Serial communication interface_0 (SCI_0) Serial communication interface_1 (SCI_1) Serial communication interface_2 (SCI_2) I C bus interface_0 (IIC_0) I C bus interface_1 (IIC_1) Host interface (XBS), keyboard buffer controller, keyboard matrix interrupt mask register (KMIMR), keyboard matrix interrupt mask register A (KMIMRA), port 6 pull-up MOS control register (KMPCR) Host interface (LPC), wake-up event interrupt mask register B (WUEMRB) 2 2 1 0 Note: MSTP1 MSTP0 * 1* 1 R/W R/W This bit can be read from or written to, however, operation is not affected. 25.2 Mode Transitions and LSI States Figure 25.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 25.2 shows the LSI internal states in each operating mode. Rev. 3.00 Mar 21, 2006 page 646 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Program halt state STBY pin = Low Reset state STBY pin = High RES pin = Low Program execution state RES pin = High SSBY = 0, LSON = 0 SLEEP instruction High-speed mode (main clock) Any interrupt SLEEP instruction External interrupt*3 SLEEP instruction Interrupt*1 LSON bit = 0 SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to STS0), clock switching exception handling SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception handling SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SSBY = 1, PSS = 0, LSON = 0 Software standby mode Sleep mode (main clock) Hardware standby mode SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0 Medium-speed mode (main clock) SLEEP instruction Interrupt*1 LSON bit = 1 SLEEP instruction Interrupt*2 SSBY = 0, PSS = 1, LSON = 1 Subsleep mode (subclock) Subactive mode (subclock) : Transition after exception processing : Power-down mode Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. Always select high-speed mode before making a transition to watch mode or sub-active mode. 1. NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts 2. NMI, IRQ0 to IRQ7, WDT0, WDT1, TMR0, and TMR1 interrupts 3. NMI, IRQ0 to IRQ2, IRQ6, and IRQ7 interrupts Figure 25.1 Mode Transition Diagram Rev. 3.00 Mar 21, 2006 page 647 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Table 25.2 LSI Internal States in Each Mode Function System clock pulse generator Subclock pulse generator CPU Instruction execution Registers HighSpeed Functioning Functioning Functioning Functioning Functioning MediumSpeed Sleep Function- Functioning ing Function- Functioning ing Medium- Halted speed operation Medium- Retained speed operation Function- Functioning ing Module Stop Functioning Functioning Functioning Watch Halted SubActive Halted SubSleep Halted Software Hardware Standby Standby Halted Halted Halted Halted Function- Function- Function- Halted ing ing ing Halted Subclock Halted Halted operation Subclock Retained operation Retained Function- Retained ing Undefined External NMI interrupts IRQ0 to IRQ7 KIN0 to KIN15 WUE0 to WUE7 Peripheral DTC modules WDT_1 WDT_0 TMR_0, TMR_1 FRT TMR_X, TMR_Y Timer connection IIC_0 IIC_1 LPC SCI_0 SCI_1 SCI_2 Peripheral PWM modules PWMX XBS, Keyboard buffer controller D/A A/D RAM I/O Note: * Function- Function- Function- Function- Function- Halted ing ing ing ing ing Function- Medium- Functioning speed ing operation Function- Function- Functioning ing ing Function- Function- Functioning ing ing Function- Function- Functioning ing ing Functioning/Halted (retained) Functioning Functioning Functioning/Halted (retained) Function- Function- Function- Functioning/Halted ing ing ing (retained) Halted Halted Halted Halted Halted (retained) (retained) (retained) (retained) (reset) Subclock operation Halted (retained) Halted (retained) Subclock operation Subclock operation Subclock operation Subclock operation Subclock operation Subclock operation Halted (retained) Halted (retained) Halted (retained) Halted (reset) Halted (reset) Halted (reset) Halted Halted Halted Halted Halted (retained) (retained) (retained) (retained) (reset) Function- Function- Function- Function- Halted ing/Halted (reset) ing ing ing (reset) Function- Function- Function- Function- Halted ing/Halted (reset) ing ing ing (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Functioning Functioning Functioning Functioning Functioning (DTC) Functioning Function- Retained ing Function- Retained ing Function- Retained Retained ing Function- Function- Retained ing ing Retained High impedance "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). Rev. 3.00 Mar 21, 2006 page 648 of 788 REJ09B0300-0300 Section 25 Power-Down Modes 25.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32). On-chip peripheral modules other than the bus masters always operate on the system clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and the LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit set to 1, the LSON bit cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0, operation shifts to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, medium-speed mode is cancelled and a transition is made to hardware standby mode. Figure 25.2 shows an example of medium-speed mode timing. Rev. 3.00 Mar 21, 2006 page 649 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Medium-speed mode , peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 25.2 Medium-Speed Mode Timing 25.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU's internal registers are retained. Sleep mode is exited by any interrupt, the RES pin, or the STBY pin. When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation stabilization time has passed, driving the RES pin high causes the CPU to start reset exception handling. When the STBY pin level is driven low, sleep mode is cancelled and a transition is made to hardware standby mode. Rev. 3.00 Mar 21, 2006 page 650 of 788 REJ09B0300-0300 Section 25 Power-Down Modes 25.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT_1) is cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, I/O ports, and the states of on-chip peripheral modules other than the SCI, PWM, and PWMX, are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ2, IRQ6, or IRQ7), the RES pin input, or STBY pin input. When an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2, IRQ6, and IRQ7 is generated. Software standby mode cannot be cleared if an interrupt enable bit corresponding to an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt is cleared to 0 or if the interrupt has been masked on the CPU side. When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation stabilizes, the CPU begins reset exception handling. When the STBY pin is driven low, software standby mode is cancelled and a transition is made to hardware standby mode. Figure 25.3 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge of the NMI pin. Rev. 3.00 Mar 21, 2006 page 651 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Oscillator NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 25.3 Application Example in Software Standby Mode 25.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD1 and MD0) while this LSI is in hardware standby mode. Hardware standby mode is cleared by the STBY pin input or the RES pin input. When the STBY pin is driven high while the RES pin is low, clock oscillation is started. Ensure that the RES pin is held low until system clock oscillation stabilizes. When the RES pin is subsequently driven high after the clock oscillation stabilization time has passed, reset exception handling starts. Rev. 3.00 Mar 21, 2006 page 652 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Figure 25.4 shows an example of hardware standby mode timing. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 25.4 Hardware Standby Mode Timing 25.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and onchip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Watch mode is exited by an interrupt (WOVI1, NMI, IRQ0 to IRQ2, IRQ6, or IRQ7), RES pin input, or STBY pin input. When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR cleared to 0 or to subactive mode when the LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in SBYCR has elapsed. In the case of an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt, watch mode is not exited if the corresponding enable bit has been cleared to 0. In the case of interrupts from the onchip peripheral modules, watch mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt, or the interrupt is masked by the CPU. Rev. 3.00 Mar 21, 2006 page 653 of 788 REJ09B0300-0300 Section 25 Power-Down Modes When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. 25.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Subsleep mode is exited by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to IRQ7), the RES pin input, or the STBY pin input. When an interrupt occurs, subsleep mode is exited and interrupt exception handling starts. In the case of an IRQ0 to IRQ7 interrupt, subsleep mode is not exited if the corresponding enable bit has been cleared to 0. In the case of interrupts from the on-chip peripheral modules, subsleep mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt, or the interrupt is masked by the CPU. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. Rev. 3.00 Mar 21, 2006 page 654 of 788 REJ09B0300-0300 Section 25 Power-Down Modes 25.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at a low speed based on the subclock and sequentially executes programs. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must be cleared to 0. Subactive mode is exited by the SLEEP instruction, RES pin input, or STBY pin input. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, the CPU exits subactive mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 10, and the PSS bit in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode. For details of direct transitions, see section 25.11, Direct Transitions. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until the clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. Rev. 3.00 Mar 21, 2006 page 655 of 788 REJ09B0300-0300 Section 25 Power-Down Modes 25.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, D/A converter, A/D converter, PWM, and PWMX are retained. After the reset state is cancelled, all modules other than DTC are in module stop mode. While an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. 25.11 Direct Transitions The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a direct transition is made from high-speed mode to subactive mode, there is no interruption of program execution. A direct transition is enabled by setting the DTON bit in LPWRCR to 1 and then executing the SLEEP instruction. After a transition, direct transition exception handling starts. The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 11, and the PSS bit in TSCR (WDT_1) set to 1. To make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in SBYCR has elapsed, execute the SLEEP instruction in subactive mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 01, and the PSS bit in TSCR (WDT_1) set to 1. Rev. 3.00 Mar 21, 2006 page 656 of 788 REJ09B0300-0300 Section 25 Power-Down Modes 25.12 Usage Notes 25.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 25.12.2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stabilization. 25.12.3 DTC Module Stop Mode If the DTC module stop mode specification and DTC bus request occur simultaneously, the bus is released to the DTC and the MSTP bit cannot be set to 1. After completing the DTC bus cycle, set the MSTP bit to 1 again. Rev. 3.00 Mar 21, 2006 page 657 of 788 REJ09B0300-0300 Section 25 Power-Down Modes Rev. 3.00 Mar 21, 2006 page 658 of 788 REJ09B0300-0300 Section 26 List of Registers Section 26 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order) * Registers are listed from the lower allocation addresses. * The MSB-side address is indicated for 16-bit addresses. * Registers are classified by functional modules. * The access size is indicated. 2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (address order) above. * Reserved bits are indicated by in the bit name column. * The bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * 16-bit registers are indicated from the bit on the MSB side. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (address order) above. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. 4. Register Select Conditions * Register states are described in the same order as the Register Addresses (address order) above. * For details on the register select conditions, refer to section 3.2.2, System Control Register (SYSCR), 3.2.3, Serial Timer Control Register (STCR), 26.1.3, Module Stop Control Registers H and L (MSTPCRH, MSTPCRL), and the register descriptions for each module. Rev. 3.00 Mar 21, 2006 page 659 of 788 REJ09B0300-0300 Section 26 List of Registers 26.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Number of Access States 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Register Name Port G open drain control register Port E open drain control register Port F open drain control register Port C open drain control register Port D open drain control register Bidirectional data register 0MW Bidirectional data register 0SW Bidirectional data register 1 Bidirectional data register 2 Bidirectional data register 3 Bidirectional data register 4 Bidirectional data register 5 Bidirectional data register 6 Bidirectional data register 7 Bidirectional data register 8 Bidirectional data register 9 Bidirectional data register 10 Bidirectional data register 11 Bidirectional data register 12 Bidirectional data register 13 Bidirectional data register 14 Bidirectional data register 15 Input data register 3 Output data register 3 Status register 3 Abbreviation PGNOCR*1 PENOCR*1 PFNOCR* 1 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE16 H'FE18 H'FE19 H'FE1C H'FE1D H'FE20 H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 H'FE32 Module PORT PORT PORT PORT PORT LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PCNOCR* PDNOCR* TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 1 1 Rev. 3.00 Mar 21, 2006 page 660 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Register Name LPC channel address register H LPC channel address register L SERIRQ control register 0 SERIRQ control register 1 Input data register 1 Output data register 1 Status register 1 Input data register 2 Output data register 2 Status register 2 Host interface select register Host interface control register 0 Host interface control register 1 Host interface control register 2 Host interface control register 3 Wakeup event interrupt mask register B Port G output data register Port G input data register Port G data direction register Port E output data register Port F output data register Port E input data register Port E data direction register Port F input data register Abbreviation LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB*2 PGODR*1 PGPIN*1 PGDDR*1 PEODR*1 PFODR*1 PEPIN*1 PEDDR*1 PFPIN*1 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3C H'FE3D H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FE46 H'FE47 (read) H'FE47 (write) H'FE48 H'FE49 H'FE4A (read) H'FE4A (write) H'FE4B (read) Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC INT PORT PORT PORT PORT PORT PORT PORT PORT Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Mar 21, 2006 page 661 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 Register Name Port F data direction register Port C output data register Port D output data register Port C input data register Port C data direction register Port D input data register Port D data direction register Host interface control register 2 Input data register_3 Output data register_3 Status register_3 Input data register_4 Output data register_4 Status register_4 I C bus extended control register_0 I C bus extended control register_1 Keyboard control register H_0 2 2 Abbreviation PFDDR*1 PCODR*1 PDODR* PCPIN* 1 1 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE4B (write) H'FE4C H'FE4D H'FE4E (read) H'FE4E (write) H'FE4F (read) H'FE4F (write) H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FED4 H'FED5 H'FED8 Module PORT PORT PORT PORT PORT PORT PORT XBS XBS XBS XBS XBS XBS XBS IIC_0 IIC_1 Keyboard buffer controller_0 Keyboard buffer controller_0 Keyboard buffer controller_0 Keyboard buffer controller_1 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PCDDR*1 PDPIN*1 PDDDR*1 HICR2 IDR_3 ODR_3 STR_3 IDR_4 ODR_4 STR_4 ICXR_0 ICXR_1 KBCRH_0 Keyboard control register L_0 KBCRL_0 8 H'FED9 8 2 Keyboard data buffer register_0 KBBR_0 8 H'FEDA 8 2 Keyboard control register H_1 KBCRH_1 8 H'FEDC 8 2 Rev. 3.00 Mar 21, 2006 page 662 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 2 Register Name Keyboard control register L_1 Abbreviation KBCRL_1 Number of Bits Address 8 H'FEDD Module Keyboard buffer controller_1 Keyboard buffer controller_1 Keyboard buffer controller_2 Keyboard buffer controller_2 Keyboard buffer controller_2 IrDA/ Extended A/D IIC_0 INT INT INT INT INT INT DTC DTC DTC DTC DTC DTC INT Data Bus Width 8 Keyboard data buffer register_1 KBBR_1 8 H'FEDE 8 2 Keyboard control register H_2 KBCRH_2 8 H'FEE0 8 2 Keyboard control register L_2 KBCRL_2 8 H'FEE1 8 2 Keyboard data buffer register_2 KBBR_2 8 H'FEE2 8 2 Keyboard comparator control register KBCOMP 8 H'FEE4 8 2 DDC switch register Interrupt control register A Interrupt control register B Interrupt control register C IRQ status register IRQ sense control register H IRQ sense control register L DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC vector register Address break control register DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 3.00 Mar 21, 2006 page 663 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Break address register A Break address register B Break address register C Flash memory control register 1 Flash memory control register 2 Peripheral clock select register Erase block register 1 System control register 2 Erase block register 2 Standby control register Low power control register Module stop control register H Module stop control register L Serial mode register_1 I C bus control register_1 Bit rate register_1 I C bus status register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 I C bus data register_1 Second slave address register_1 I C bus mode register_1 Slave address register_1 Timer interrupt enable register Timer control/status register Free running counter H 2 2 2 2 Abbreviation BARA BARB BARC FLMCR1 FLMCR2 PCSR EBR1 SYSCR2 EBR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEF5 H'FEF6 H'FEF7 H'FF80 H'FF81 H'FF82 H'FF82 H'FF83 H'FF83 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 H'FF88 H'FF89 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF8E H'FF8E H'FF8F H'FF8F H'FF90 H'FF91 H'FF92 Module INT INT INT FLASH FLASH PWM FLASH SYSTEM FLASH SYSTEM SYSTEM SYSTEM SYSTEM SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 IIC_1 IIC_1 IIC_1 IIC_1 FRT FRT FRT Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Mar 21, 2006 page 664 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Free running counter L Output control register AH Output control register BH Output control register AL Output control register BL Timer control register Timer output compare control register Input capture register AH Output control register ARH Input capture register AL Output control register ARL Input capture register BH Output control register AFH Input capture register BL Output control register AFL Input capture register CH Output compare register DMH Input capture register CL Output compare register DML Input capture register DH Input capture register DL Serial mode register_2 PWM (D/A) control register PWM (D/A) data register AH PWM (D/A) data register AL Bit rate register_2 Serial control register_2 Transmit data register_2 Abbreviation FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL SMR_2 DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF93 H'FF94 H'FF94 H'FF95 H'FF95 H'FF96 H'FF97 H'FF98 H'FF98 H'FF99 H'FF99 H'FF9A H'FF9A H'FF9B H'FF9B H'FF9C H'FF9C H'FF9D H'FF9D H'FF9E H'FF9F H'FFA0 H'FFA0 H'FFA0 H'FFA1 H'FFA1 H'FFA2 H'FFA3 Module FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT SCI_2 PWMX PWMX PWMX SCI_2 SCI_2 SCI_2 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Mar 21, 2006 page 665 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Serial status register_2 Receive data register_2 Smart card mode register_2 PWM (D/A) counter H PWM (D/A) data register BH PWM (D/A) counter L PWM (D/A) data register BL Timer control/status register_0 Timer counter_0 Timer counter_0 Port A output data register Port A input data register Port A data direction register Port 1 pull-up MOS control register Port 2 pull-up MOS control register Port 3 pull-up MOS control register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Port 3 data direction register Port 4 data direction register Port 3 data register Port 4 data register Port 5 data direction register Port 6 data direction register Port 5 data register Abbreviation SSR_2 RDR_2 SCMR_2 DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFA4 H'FFA5 H'FFA6 H'FFA6 H'FFA6 H'FFA7 H'FFA7 H'FFA8 H'FFA8 (write) H'FFA9 (read) H'FFAA H'FFAB H'FFAB H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA Module SCI_2 SCI_2 SCI_2 PWMX PWMX PWMX PWMX WDT WDT_0 WDT_0 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Mar 21, 2006 page 666 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port 6 data register Port B output data register Port B input data register Port 8 data direction register Port 7 input data register Port B data direction register Port 8 data register Port 9 data direction register Port 9 data register Interrupt enable register Serial timer control register System control register Mode control register Bus control register Wait state control register Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 PWM output enable register B Abbreviation P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFBB H'FFBC H'FFBD (read) H'FFBD (write) H'FFBE (read) H'FFBE (write) H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 Module PORT PORT PORT PORT PORT PORT PORT PORT PORT INT SYSTEM SYSTEM SYSTEM BSC BSC TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 PWM Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 Rev. 3.00 Mar 21, 2006 page 667 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name PWM output enable register A PWM data polarity register B PWM data polarity register A PWM register select PWM data registers 0 to 15 Serial mode register_0 I C bus control register_0 Bit rate register_0 I C bus status register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 I C bus data register_0 Second slave address register_0 I C bus mode register_0 Slave address register_0 A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register 2 2 2 2 Abbreviation PWOERA PWDPRB PWDPRA PWSL PWDR0 to PWDR15 SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD8 H'FFD9 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFDE H'FFDE H'FFDF H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 Module PWM PWM PWM PWM PWM SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 IIC_0 IIC_0 IIC_0 IIC_0 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 A/D converter 8 Rev. 3.00 Mar 21, 2006 page 668 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Timer control/status register_1 Timer counter_1 Timer counter_1 Host interface control register Timer control register_X Timer control register_Y Keyboard matrix interrupt register 6 Timer control/status register_X Timer control/status register_Y Pull-up MOS control register Input capture register R Time constant register A_Y Keyboard matrix interrupt register A Input capture register F Time constant register B_Y Input data register_1 Timer counter_X Timer counter_Y Output data register_1 Timer constant register C Timer input select register Status register_1 Timer constant register A_X Timer constant register B_X D/A data register 0 D/A data register 1 D/A control register Input data register_2 Abbreviation TCSR_1 TCNT_1 TCNT_1 HICR TCR_X TCR_Y KMIMR TCSR_X TCSR_Y KMPCR TICRR TCORA_Y KMIMRA TICRF TCORB_Y IDR_1 TCNT_X TCNT_Y ODR_1 TCORC TISR STR_1 TCORA_X TCORB_X DADR0 DADR1 DACR IDR_2 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFEA H'FFEA (write) H'FFEB (read) H'FFF0 H'FFF0 H'FFF0 H'FFF1 H'FFF1 H'FFF1 H'FFF2 H'FFF2 H'FFF2 H'FFF3 H'FFF3 H'FFF3 H'FFF4 H'FFF4 H'FFF4 H'FFF5 H'FFF5 H'FFF5 H'FFF6 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFC Module WDT_1 WDT_1 WDT_1 XBS TMR_X TMR_Y INT TMR_X TMR_Y PORT TMR_X TMR_Y INT TMR_X TMR_Y XBS TMR_X TMR_Y XBS TMR_X TMR_Y XBS TMR_X TMR_X Data Bus Width 8 8 8 8 16 16 8 16 16 8 16 16 8 16 16 8 16 16 8 16 16 8 16 16 D/A converter 8 D/A converter 8 D/A converter 8 XBS 8 Rev. 3.00 Mar 21, 2006 page 669 of 788 REJ09B0300-0300 Section 26 List of Registers Number of Access States 2 2 2 2 2 2 Register Name Timer connection register I Output data register_2 Timer connection register O Status register_2 Timer connection register S Edge sense register Abbreviation TCONRI ODR_2 TCONRO STR_2 TCONRS SEDGR Number of Bits Address 8 8 8 8 8 8 H'FFFC H'FFFD H'FFFD H'FFFE H'FFFE H'FFFF Module Timer connection XBS Timer connection XBS Timer connection Timer connection Data Bus Width 8 8 8 8 8 8 Notes: 1. Can be used on the H8S/2160B and H8S/2161B. 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page 670 of 788 REJ09B0300-0300 Section 26 List of Registers 26.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. 16-bit registers are shown as 2 lines. Register Abbreviation PGNOCR*1 PENOCR* 1 Bit 7 PG7NOCR PE7NOCR PF7NOCR PC7NOCR PD7NOCR Bit 6 PG6NOCR PE6NOCR PF6NOCR PC6NOCR PD6NOCR Bit 5 PG5NOCR PE5NOCR PF5NOCR PC5NOCR PD5NOCR Bit 4 PG4NOCR PE4NOCR PF4NOCR PC4NOCR PD4NOCR Bit 3 PG3NOCR PE3NOCR PF3NOCR PC3NOCR PD3NOCR Bit 2 PG2NOCR PE2NOCR PF2NOCR PC2NOCR PD2NOCR Bit 1 PG1NOCR PE1NOCR PF1NOCR PC1NOCR PD1NOCR Bit 0 PG0NOCR PE0NOCR PF0NOCR PC0NOCR PD0NOCR Module PORT 1 PFNOCR* PCNOCR* PDNOCR* TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 2 STR3* 1 1 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 IBF3B DBU37 Bit 15 Bit 7 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 OBF3B DBU36 Bit 14 Bit 6 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 MWMF DBU35 Bit 13 Bit 5 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 SWMF DBU34 Bit 12 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 C/D3 C/D3 Bit 11 Bit 3 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 DBU32 DBU32 Bit 10 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 IBF3A IBF3A Bit 9 Bit 1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 OBF3A OBF3A Bit 8 TWRE LPC STR3* 3 LADR3H LADR3L Rev. 3.00 Mar 21, 2006 page 671 of 788 REJ09B0300-0300 Section 26 List of Registers Register Abbreviation SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB* PGODR*1 PGPIN*1 PGDDR*1 PEODR*1 PFODR*1 PEPIN*1 PEDDR*1 PFPIN*1 PFDDR*1 PCODR* 1 5 Bit 7 Q/C IRQ11E3 Bit 7 Bit 7 DBU17 Bit 7 Bit 7 DBU27 SELSTR3 LPC3E LPCBSY GA20 LFRAME WUEMR7 PG7ODR PG7PIN PG7DDR PE7ODR PF7ODR PE7PIN PE7DDR PF7PIN PF7DDR PC7ODR PD7ODR PC7PIN Bit 6 SELREQ IRQ10E3 Bit 6 Bit 6 DBU16 Bit 6 Bit 6 DBU26 SELIRQ11 Bit 5 IEDIR IRQ9E3 Bit 5 Bit 5 DBU15 Bit 5 Bit 5 DBU25 SELIRQ10 Bit 4 SMIE3B IRQ6E3 Bit 4 Bit 4 DBU14 Bit 4 Bit 4 DBU24 SELIRQ9 FGA20E LRSTB ABRT LRESET WUEMR4 PG4ODR PG4PIN PG4DDR PE4ODR PF4ODR PE4PIN PE4DDR PF4PIN PF4DDR PC4ODR PD4ODR PC4PIN PC4DDR PD4PIN PD4DDR -- IDR4 ODR4 DBU Bit 3 SMIE3A IRQ11E2 Bit 3 Bit 3 C/D1 Bit 3 Bit 3 C/D2 SELIRQ6 SDWNE SDWNB IBFIE3 LPCPD WUEMR3 PG3ODR PG3PIN PG3DDR PE3ODR PF3ODR PE3PIN PE3DDR PF3PIN PF3DDR PC3ODR PD3ODR PC3PIN PC3DDR PD3PIN PD3DDR -- IDR3 ODR3 C/D Bit 2 SMIE2 IRQ10E2 Bit 2 Bit 2 DBU12 Bit 2 Bit 2 DBU22 SELSMI PMEE PMEB IBFIE2 PME WUEMR2 PG2ODR PG2PIN PG2DDR PE2ODR PF2ODR PE2PIN PE2DDR PF2PIN PF2DDR PC2ODR PD2ODR PC2PIN PC2DDR PD2PIN PD2DDR IBFIE4 IDR2 ODR2 DBU Bit 1 IRQ12E1 IRQ9E2 Bit 1 Bit 1 IBF1 Bit 1 Bit 1 IBF2 SELIRQ12 Bit 0 IRQ1E1 IRQ6E2 Bit 0 Bit 0 OBF1 Bit 0 Bit 0 OBF2 SELIRQ1 LSCIE LSCIB ERRIE LSCI WUEMR0 PG0ODR PG0PIN PG0DDR PE0ODR PF0ODR PE0PIN PE0DDR PF0PIN PF0DDR PC0ODR PD0ODR PC0PIN PC0DDR PD0PIN PD0DDR -- IDR0 ODR0 OBF Module LPC LPC2E CLKREQ LRST CLKRUN WUEMR6 PG6ODR PG6PIN PG6DDR PE6ODR PF6ODR PE6PIN PE6DDR PF6PIN PF6DDR PC6ODR PD6ODR PC6PIN PC6DDR PD6PIN PD6DDR -- IDR6 ODR6 DBU LPC1E IRQBSY SDWN SERIRQ WUEMR5 PG5ODR PG5PIN PG5DDR PE5ODR PF5ODR PE5PIN PE5DDR PF5PIN PF5DDR PC5ODR PD5ODR PC5PIN PC5DDR PD5PIN PD5DDR -- IDR5 ODR5 DBU LSMIE LSMIB IBFIE1 LSMI WUEMR1 PG1ODR PG1PIN PG1DDR PE1ODR PF1ODR PE1PIN PE1DDR PF1PIN PF1DDR PC1ODR PD1ODR PC1PIN PC1DDR PD1PIN PD1DDR IBFIE3 IDR1 ODR1 IBF INT PORT PDODR*1 PCPIN*1 PCDDR* PDPIN*1 PDDDR*1 HICR2 IDR_3 ODR_3 STR_3 1 PC7DDR PD7PIN PD7DDR -- IDR7 ODR7 DBU XBS Rev. 3.00 Mar 21, 2006 page 672 of 788 REJ09B0300-0300 Section 26 List of Registers Register Abbreviation IDR_4 ODR_4 STR_4 ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCRH_1 KBCRL_1 KBBR_1 KBCRH_2 KBCRL_2 KBBR_2 KBCOMP Bit 7 IDR7 ODR7 DBU STOPIM STOPIM KBIOE KBE KB7 KBIOE KBE KB7 KBIOE KBE KB7 IrE Bit 6 IDR6 ODR6 DBU HNDS HNDS KCLKI KCLKO KB6 KCLKI KCLKO KB6 KCLKI KCLKO KB6 IrCKS2 Bit 5 IDR5 ODR5 DBU ICDRF ICDRF KDI KDO KB5 KDI KDO KB5 KDI KDO KB5 IrCKS1 Bit 4 IDR4 ODR4 DBU ICDRE ICDRE KBFSEL -- KB4 KBFSEL -- KB4 KBFSEL -- KB4 IrCKS0 Bit 3 IDR3 ODR3 C/D ALIE ALIE KBIE RXCR3 KB3 KBIE RXCR3 KB3 KBIE RXCR3 KB3 KBADE Bit 2 IDR2 ODR2 DBU ALSL ALSL KBF RXCR2 KB2 KBF RXCR2 KB2 KBF RXCR2 KB2 KBCH2 Bit 1 IDR1 ODR1 IBF FNC1 FNC1 PER RXCR1 KB1 PER RXCR1 KB1 PER RXCR1 KB1 KBCH1 Bit 0 IDR0 ODR0 OBF FNC0 FNC0 KBS RXCR0 KB0 KBS RXCR0 KB0 KBS RXCR0 KB0 KBCH0 Module XBS IIC_0 IIC_1 Keyboard buffer controller_ 0 Keyboard buffer controller_ 1 Keyboard buffer controller_ 2 IrDA/ expanded A/D IIC_0 INT DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB SWE ICRA7 ICRB7 ICRC7 IRQ7F IRQ7SCB IRQ3SCB DTCEA7 DTCEB7 DTCEC7 DTCED7 DTCEE7 SWDTE CMF A23 A15 SW ICRA6 ICRB6 ICRC6 IRQ6F IRQ7SCA IRQ3SCA DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTVEC6 -- A22 A14 IE ICRA5 ICRB5 ICRC5 IRQ5F IRQ6SCB IRQ2SCB DTCEA5 DTCEB5 DTCEC5 DTCED5 DTCEE5 DTVEC5 -- A21 A13 IF ICRA4 ICRB4 ICRC4 IRQ4F IRQ6SCA IRQ2SCA DTCEA4 DTCEB4 DTCEC4 DTCED4 DTCEE4 DTVEC4 -- A20 A12 CLR3 ICRA3 ICRB3 ICRC3 IRQ3F IRQ5SCB IRQ1SCB DTCEA3 DTCEB3 DTCEC3 DTCED3 DTCEE3 DTVEC3 -- A19 A11 CLR2 ICRA2 ICRB2 ICRC2 IRQ2F IRQ5SCA IRQ1SCA DTCEA2 DTCEB2 DTCEC2 DTCED2 DTCEE2 DTVEC2 -- A18 A10 CLR1 ICRA1 ICRB1 ICRC1 IRQ1F IRQ4SCB IRQ0SCB DTCEA1 DTCEB1 DTCEC1 DTCED1 DTCEE1 DTVEC1 -- A17 A9 CLR0 ICRA0 ICRB0 ICRC0 IRQ0F IRQ4SCA IRQ0SCA DTCEA0 DTCEB0 DTCEC0 DTCED0 DTCEE0 DTVEC0 BIE A16 A8 DTC INT Rev. 3.00 Mar 21, 2006 page 673 of 788 REJ09B0300-0300 Section 26 List of Registers Register Abbreviation BARC FLMCR1 FLMCR2 PCSR 4 EBR1* Bit 7 A7 FWE FLER -- -- KWUL1 EB7 SSBY DTON MSTP15 MSTP7 C/A ICE Bit 7 ESTP TIE Bit 7 TDRE Bit 7 -- ICDR7 SVAX6 MLS SVA6 ICIAE ICFA Bit 15 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 IEDGA Bit 6 A6 SWE -- -- -- KWUL0 EB6 STS2 LSON MSTP14 MSTP6 CHR IEIC Bit 6 STOP RIE Bit 6 RDRF Bit 6 -- ICDR6 SVAX5 WAIT SVA5 ICIBE ICFB Bit 14 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 IEDGB Bit 5 A5 -- -- -- -- P6PUE EB5 STS1 NESEL MSTP13 MSTP5 PE MST Bit 5 IRTR TE Bit 5 ORER Bit 5 -- ICDR5 SVAX4 CKS2 SVA4 ICICE ICFC Bit 13 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 IEDGC Bit 4 A4 -- -- -- -- -- EB4 STS0 EXCLE MSTP12 MSTP4 O/E TRS Bit 4 AASX RE Bit 4 FER Bit 4 -- ICDR4 SVAX3 CKS1 SVA3 ICIDE ICFD Bit 12 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 IEDGD Bit 3 A3 EV -- -- EB11 SDE EB3 -- -- MSTP11 MSTP3 STOP ACKE Bit 3 AL MPIE Bit 3 PER Bit 3 SDIR ICDR3 SVAX2 CKS0 SVA2 OCIAE OCFA Bit 11 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 BUFEA Bit 2 A2 PV -- PWCKB EB10 CS4E EB2 SCK2 -- MSTP10 MSTP2 MP BBSY Bit 2 AAS TEIE Bit 2 TEND Bit 2 SINV ICDR2 SVAX1 BC2 SVA1 OCIBE OCFB Bit 10 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 BUFEB Bit 1 A1 E ESU PWCKA EB9 CS3E EB1 SCK1 -- MSTP9 MSTP1 CKS1 IRIC Bit 1 ADZ CKE1 Bit 1 MPB Bit 1 -- ICDR1 SVAX0 BC1 SVA0 OVIE OVF Bit 9 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 CKS1 Bit 0 -- P PSU -- EB8 HI12E EB0 SCK0 -- MSTP8 MSTP0 CKS0 SCP Bit 0 ACKB CKE0 Bit 0 MPBT Bit 0 SMIF ICDR0 FSX BC0 FS -- CCLRA Bit 8 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 CKS0 Module INT FLASH PWM FLASH SYSTEM FLASH SYSTEM SYSCR2 EBR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 IIC_1 FRT Rev. 3.00 Mar 21, 2006 page 674 of 788 REJ09B0300-0300 Section 26 List of Registers Register Abbreviation TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL SMR_2 DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 PAODR PAPIN Bit 7 ICRDMS Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 7 C/A TEST DA13 DA5 Bit 7 TIE Bit 7 TDRE Bit 7 -- UC7 DA13 UC8 DA5 OVF Bit 7 PA7ODR PA7PIN Bit 6 OCRAMS Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 6 CHR PWME DA12 DA4 Bit 6 RIE Bit 6 RDRF Bit 6 -- UC6 DA12 UC9 DA4 WT/IT Bit 6 PA6ODR PA6PIN Bit 5 ICRS Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 5 PE -- DA11 DA3 Bit 5 TE Bit 5 ORER Bit 5 -- UC5 DA11 UC10 DA3 TME Bit 5 PA5ODR PA5PIN Bit 4 OCRS Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 4 O/E -- DA10 DA2 Bit 4 RE Bit 4 FER Bit 4 -- UC4 DA10 UC11 DA2 -- Bit 4 PA4ODR PA4PIN Bit 3 OEA Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 3 STOP OEB DA9 DA1 Bit 3 MPIE Bit 3 PER Bit 3 SDIR UC3 DA9 UC12 DA1 RST/NMI Bit 3 PA3ODR PA3PIN Bit 2 OEB Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 2 MP OEA DA8 DA0 Bit 2 TEIE Bit 2 TEND Bit 2 SINV UC2 DA8 UC13 DA0 CKS2 Bit 2 PA2ODR PA2PIN Bit 1 OLVLA Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 1 CKS1 OS DA7 CFS Bit 1 CKE1 Bit 1 MPB Bit 1 -- UC1 DA7 -- CFS CKS1 Bit 1 PA1ODR PA1PIN Bit 0 OLVLB Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 0 CKS0 CKS DA6 -- Bit 0 CKE0 Bit 0 MPBT Bit 0 SMIF UC0 DA6 REGS REGS CKS0 Bit 0 PA0ODR PA0PIN Module FRT SCI_2 PWMX SCI_2 PWMX WDT_0 PORT Rev. 3.00 Mar 21, 2006 page 675 of 788 REJ09B0300-0300 Section 26 List of Registers Register Abbreviation PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 Bit 7 PA7DDR P17PCR P27PCR P37PCR P17DDR P27DDR P17DR P27DR P37DDR P47DDR P37DR P47DR -- P67DDR -- P67DR PB7ODR PB7PIN -- P77PIN PB7DDR -- P97DDR P97DR IRQ7E IICS CS2E EXPE -- -- CMIEB CMIEB CMFB Bit 6 PA6DDR P16PCR P26PCR P36PCR P16DDR P26DDR P16DR P26DR P36DDR P46DDR P36DR P46DR -- P66DDR -- P66DR PB6ODR PB6PIN P86DDR P76PIN PB6DDR P86DR P96DDR P96DR IRQ6E IICX1 IOSE -- ICIS0 -- CMIEA CMIEA CMFA Bit 5 PA5DDR P15PCR P25PCR P35PCR P15DDR P25DDR P15DR P25DR P35DDR P45DDR P35DR P45DR -- P65DDR -- P65DR PB5ODR PB5PIN P85DDR P75PIN PB5DDR P85DR P95DDR P95DR IRQ5E IICX0 INTM1 -- BRSTRM ABW OVIE OVIE OVF Bit 4 PA4DDR P14PCR P24PCR P34PCR P14DDR P24DDR P14DR P24DR P34DDR P44DDR P34DR P44DR -- P64DDR -- P64DR PB4ODR PB4PIN P84DDR P74PIN PB4DDR P84DR P94DDR P94DR IRQ4E IICE INTM0 -- BRSTS1 AST CCLR1 CCLR1 ADTE Bit 3 PA3DDR P13PCR P23PCR P33PCR P13DDR P23DDR P13DR P23DR P33DDR P43DDR P33DR P43DR -- P63DDR -- P63DR PB3ODR PB3PIN P83DDR P73PIN PB3DDR P83DR P93DDR P93DR IRQ3E FLSHE XRST -- BRSTS0 WMS1 CCLR0 CCLR0 OS3 Bit 2 PA2DDR P12PCR P22PCR P32PCR P12DDR P22DDR P12DR P22DR P32DDR P42DDR P32DR P42DR P52DDR P62DDR P52DR P62DR PB2ODR PB2PIN P82DDR P72PIN PB2DDR P82DR P92DDR P92DR IRQ2E -- NMIEG -- -- WMS0 CKS2 CKS2 OS2 Bit 1 PA1DDR P11PCR P21PCR P31PCR P11DDR P21DDR P11DR P21DR P31DDR P41DDR P31DR P41DR P51DDR P61DDR P51DR P61DR PB1ODR PB1PIN P81DDR P71PIN PB1DDR P81DR P91DDR P91DR IRQ1E ICKS1 HIE MDS1 IOS1 WC1 CKS1 CKS1 OS1 Bit 0 PA0DDR P10PCR P20PCR P30PCR P10DDR P20DDR P10DR P20DR P30DDR P40DDR P30DR P40DR P50DDR P60DDR P50DR P60DR PB0ODR PB0PIN P80DDR P70PIN PB0DDR P80DR P90DDR P90DR IRQ0E ICKS0 RAME MDS0 IOS0 WC0 CKS0 CKS0 OS0 Module PORT INT SYSTEM BSC TMR_0, TMR_1 Rev. 3.00 Mar 21, 2006 page 676 of 788 REJ09B0300-0300 Section 26 List of Registers Register Abbreviation TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR0-15 SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH Bit 7 CMFB Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 OE15 OE7 OS15 OS7 PWCKE Bit 7 C/A ICE Bit 7 ESTP TIE Bit 7 TDRE Bit 7 -- ICDR7 SVAX6 MLS SVA6 AD9 AD1 AD9 AD1 AD9 AD1 AD9 Bit 6 CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 OE14 OE6 OS14 OS6 PWCKS Bit 6 CHR IEIC Bit 6 STOP RIE Bit 6 RDRF Bit 6 -- ICDR6 SVAX5 WAIT SVA5 AD8 AD0 AD8 AD0 AD8 AD0 AD8 Bit 5 OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 OE13 OE5 OS13 OS5 -- Bit 5 PE MST Bit 5 IRTR TE Bit 5 ORER Bit 5 -- ICDR5 SVAX4 CKS2 SVA4 AD7 -- AD7 -- AD7 -- AD7 Bit 4 -- Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 OE12 OE4 OS12 OS4 -- Bit 4 O/E TRS Bit 4 AASX RE Bit 4 FER Bit 4 -- ICDR4 SVAX3 CKS1 SVA3 AD6 -- AD6 -- AD6 -- AD6 Bit 3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 OE11 OE3 OS11 OS3 RS3 Bit 3 STOP ACKE Bit 3 AL MPIE Bit 3 PER Bit 3 SDIR ICDR3 SVAX2 CKS0 SVA2 AD5 -- AD5 -- AD5 -- AD5 Bit 2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 OE10 OE2 OS10 OS2 RS2 Bit 2 MP BBSY Bit 2 AAS TEIE Bit 2 TEND Bit 2 SINV ICDR2 SVAX1 BC2 SVA1 AD4 -- AD4 -- AD4 -- AD4 Bit 1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 OE9 OE1 OS9 OS1 RS1 Bit 1 CKS1 IRIC Bit 1 ADZ CKE1 Bit 1 MPB Bit 1 -- ICDR1 SVAX0 BC1 SVA0 AD3 -- AD3 -- AD3 -- AD3 Bit 0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 OE8 OE0 OS8 OS0 RS0 Bit 0 CKS0 SCP Bit 0 ACKB CKE0 Bit 0 MPBT Bit 0 SMIF ICDR0 FSX BC0 FS AD2 -- AD2 -- AD2 -- AD2 Module TMR_0, TMR_1 PWM SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 IIC_0 A/D converter Rev. 3.00 Mar 21, 2006 page 677 of 788 REJ09B0300-0300 Section 26 List of Registers Register Abbreviation ADDRDL ADCSR ADCR TCSR_1 TCNT_1 HICR TCR_X TCR_Y KMIMR TCSR_X TCSR_Y KMPCR TICRR TCORA_Y KMIMRA TICRF TCORB_Y IDR_1 TCNT_X TCNT_Y ODR_1 TCORC TISR STR_1 TCORA_X TCORB_X DADR_0 DADR_1 DACR IDR_2 TCONRI Bit 7 AD1 ADF TRGS1 OVF Bit 7 -- CMIEB CMIEB KMIMR7 CMFB CMFB KMIMR7 Bit 7 Bit 7 KMIMR15 Bit 7 Bit 7 IDR7 Bit 7 Bit 7 ODR7 Bit 7 -- DBU17 Bit 7 Bit 7 Bit 7 Bit 7 DAOE1 IDR7 SIMOD1 Bit 6 AD0 ADIE TRGS0 WT/IT Bit 6 -- CMIEA CMIEA KMIMR6 CMFA CMFA KMIMR6 Bit 6 Bit 6 KMIMR14 Bit 6 Bit 6 IDR6 Bit 6 Bit 6 ODR6 Bit 6 -- DBU16 Bit 6 Bit 6 Bit 6 Bit 6 DAOE0 IDR6 SIMOD0 Bit 5 -- ADST -- TME Bit 5 -- OVIE OVIE KMIMR5 OVF OVF KMIMR5 Bit 5 Bit 5 KMIMR13 Bit 5 Bit 5 IDR5 Bit 5 Bit 5 ODR5 Bit 5 -- DBU15 Bit 5 Bit 5 Bit 5 Bit 5 DAE IDR5 SCONE Bit 4 -- SCAN -- PSS Bit 4 -- CCLR1 CCLR1 KMIMR4 ICF ICIE KMIMR4 Bit 4 Bit 4 KMIMR12 Bit 4 Bit 4 IDR4 Bit 4 Bit 4 ODR4 Bit 4 -- DBU14 Bit 4 Bit 4 Bit 4 Bit 4 -- IDR4 ICST Bit 3 -- CKS -- RST/NMI Bit 3 -- CCLR0 CCLR0 KMIMR3 OS3 OS3 KMIMR3 Bit 3 Bit 3 KMIMR11 Bit 3 Bit 3 IDR3 Bit 3 Bit 3 ODR3 Bit 3 -- C/D1 Bit 3 Bit 3 Bit 3 Bit 3 -- IDR3 HFINV Bit 2 -- CH2 -- CKS2 Bit 2 IBFIE2 CKS2 CKS2 KMIMR2 OS2 OS2 KMIMR2 Bit 2 Bit 2 KMIMR10 Bit 2 Bit 2 IDR2 Bit 2 Bit 2 ODR2 Bit 2 -- DBU12 Bit 2 Bit 2 Bit 2 Bit 2 -- IDR2 VFINV Bit 1 -- CH1 -- CKS1 Bit 1 IBFIE1 CKS1 CKS1 KMIMR1 OS1 OS1 KMIMR1 Bit 1 Bit 1 KMIMR9 Bit 1 Bit 1 IDR1 Bit 1 Bit 1 ODR1 Bit 1 -- IBF1 Bit 1 Bit 1 Bit 1 Bit 1 -- IDR1 HIINV Bit 0 -- CH0 -- CKS0 Bit 0 FGA20E CKS0 CKS0 KMIMR0 OS0 OS0 KMIMR0 Bit 0 Bit 0 KMIMR8 Bit 0 Bit 0 IDR0 Bit 0 Bit 0 ODR0 Bit 0 IS OBF1 Bit 0 Bit 0 Bit 0 Bit 0 -- IDR0 VIINV Module A/D converter WDT_1 XBS TMR_X TMR_Y INT TMR_X TMR_Y PORT TMR_X TMR_Y INT TMR_X TMR_Y XBS TMR_X TMR_Y XBS TMR_X TMR_Y XBS TMR_X D/A converter XBS Timer connection XBS ODR_2 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Rev. 3.00 Mar 21, 2006 page 678 of 788 REJ09B0300-0300 Section 26 List of Registers Register Abbreviation TCONRO Bit 7 HOE Bit 6 VOE Bit 5 CLOE Bit 4 CBOE Bit 3 HOINV Bit 2 VOINV Bit 1 CLOINV Bit 0 CBOINV Module Timer connection XBS Timer connection STR_2 TCONRS SEDGR DBU27 TMRX/Y VEDG DBU26 ISGENE HEDG DBU25 HOMOD1 CEDG DBU24 HOMOD0 HFEDG C/D2 VOMOD1 VFEDG DBU22 VOMOD0 PREQF IBF2 CLMOD1 IHI OBF2 CLMOD0 IVI Notes: 1. 2. 3. 4. Can be used on the H8S/2160B and H8S/2161B. When TWRE = 1 or SELSTR3 = 0 in LADR3L When TWRE = 0 and SELSTR3 = 1 in LADR3L All bits are reserved in the 64-kbyte flash memory version. The EB11 and EB10 bits are reserved in the 128-kbyte flash memory version. 5. Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page 679 of 788 REJ09B0300-0300 Section 26 List of Registers 26.3 Register Abbreviation Register States in Each Operating Mode HighSpeed/ MediumSpeed Reset Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SubActive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SubSleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby Module -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized PORT Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized -- -- LPC PGNOCR*1 Initialized -- PENOCR* Initialized -- 1 1 PFNOCR* Initialized -- PCNOCR* Initialized -- 1 PDNOCR* Initialized -- 1 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- -- -- Rev. 3.00 Mar 21, 2006 page 680 of 788 REJ09B0300-0300 Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 Reset Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SubActive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SubSleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby Module -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized LPC -- -- Initialized Initialized Initialized Initialized Initialized -- Initialized INT Initialized PORT -- Initialized Initialized Initialized -- Initialized -- Initialized Initialized Initialized -- Initialized -- Initialized Initialized XBS -- -- Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- WUEMRB*2 Initialized -- PGODR*1 PGPIN*1 PGDDR* 1 Initialized -- -- -- Initialized -- Initialized -- Initialized -- -- -- 1 PEODR* PFODR*1 PEPIN*1 PEDDR*1 PFPIN*1 PFDDR*1 PCODR*1 PDODR*1 PCPIN*1 PCDDR*1 PDPIN*1 PDDDR*1 HICR2 IDR_3 ODR_3 STR_3 IDR_4 ODR_4 STR_4 Initialized -- -- -- Initialized -- Initialized -- Initialized -- -- -- Initialized -- -- -- Initialized -- Initialized -- -- -- -- -- Initialized -- -- -- -- -- Initialized -- Rev. 3.00 Mar 21, 2006 page 681 of 788 REJ09B0300-0300 Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCRH_1 KBCRL_1 KBBR_1 KBCRH_2 KBCRL_2 KBBR_2 KBCOMP Reset Watch -- -- Sleep -- -- SubActive -- -- SubSleep -- -- Module Stop -- -- Software Hardware Standby Standby Module -- -- Initialized IIC_0 Initialized IIC_1 Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized Initialized Initialized Initialized Initialized Keyboard buffer Initialized Initialized Initialized Initialized Initialized controller_ Initialized Initialized Initialized Initialized Initialized 0 Initialized Initialized Initialized Initialized Initialized Keyboard buffer Initialized Initialized Initialized Initialized Initialized controller_ Initialized Initialized Initialized Initialized Initialized 1 Initialized Initialized Initialized Initialized Initialized Keyboard buffer Initialized Initialized Initialized Initialized Initialized controller_ Initialized Initialized Initialized Initialized Initialized 2 -- -- -- -- Initialized IrDA/ A/D converter Initialized IIC_0 Initialized INT Initialized Initialized Initialized Initialized Initialized Initialized DTC Initialized Initialized Initialized Initialized Initialized Initialized INT Initialized Initialized Initialized DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC FLMCR1 FLMCR2 Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized -- Initialized -- Initialized Initialized -- Initialized Initialized -- Initialized Initialized FLASH Initialized Initialized Rev. 3.00 Mar 21, 2006 page 682 of 788 REJ09B0300-0300 Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation PCSR EBR1 SYSCR2 EBR2 SBYCR LPWRCR Reset Watch -- Sleep -- SubActive -- SubSleep -- Module Stop -- Software Hardware Standby Standby Module -- Initialized PWM Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized Initialized -- -- -- -- Initialized Initialized FLASH -- Initialized SYSTEM Initialized -- -- -- -- -- -- -- -- -- Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized FLASH -- -- -- -- Initialized SYSTEM Initialized Initialized Initialized MSTPCRH Initialized -- MSTPCRL Initialized -- SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH OCRARH Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized -- -- -- Initialized Initialized Initialized Initialized Initialized SCI_1 -- -- -- -- Initialized IIC_1 Initialized -- -- -- Initialized Initialized Initialized Initialized Initialized SCI_1 -- -- -- -- Initialized IIC_1 Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized SCI_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized FRT Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IIC_1 Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Rev. 3.00 Mar 21, 2006 page 683 of 788 REJ09B0300-0300 Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL SMR_2 DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR Reset Watch -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- SubActive -- -- -- -- -- -- -- -- -- -- -- -- SubSleep -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby Module -- -- -- -- -- -- -- -- -- -- -- -- Initialized FRT Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized Initialized Initialized Initialized Initialized SCI_2 Initialized Initialized Initialized Initialized Initialized PWMX Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- Initialized Initialized -- Initialized -- Initialized -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized PWMX Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized WDT_0 Initialized Initialized PORT -- Initialized Initialized Initialized Initialized -- Initialized -- Initialized -- Rev. 3.00 Mar 21, 2006 page 684 of 788 REJ09B0300-0300 Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 Reset Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SubActive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SubSleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby Module -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized PORT Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- Initialized -- Initialized Initialized Initialized Initialized Initialized INT Initialized SYSTEM Initialized Initialized Initialized BSC Initialized Initialized TMR_0, TMR_1 Initialized Initialized Initialized Initialized Initialized Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized -- -- -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Rev. 3.00 Mar 21, 2006 page 685 of 788 REJ09B0300-0300 Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR0 to PWDR15 SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR Reset Watch -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- SubActive -- -- -- -- -- -- -- -- SubSleep -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- Software Hardware Standby Standby Module -- -- -- -- -- -- -- -- Initialized TMR_0, TMR_1 Initialized Initialized Initialized Initialized PWM Initialized Initialized Initialized Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized -- Initialized -- Initialized -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_0 -- -- -- -- Initialized IIC_0 Initialized -- -- -- Initialized Initialized Initialized Initialized Initialized SCI_0 -- -- -- -- Initialized IIC_0 Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized SCI_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized IIC_0 Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized Initialized Initialized Initialized Initialized A/D converter Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 3.00 Mar 21, 2006 page 686 of 788 REJ09B0300-0300 Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation ADCR TCSR_1 TCNT_1 HICR TCR_X TCR_Y KMIMR TCSR_X TCSR_Y KMPCR TICRR TCORA_Y KMIMRA TICRF TCORB_Y IDR_1 TCNT_X TCNT_Y ODR_1 TCORC TISR STR_1 TCORA_X TCORB_X DADR0 DADR1 DACR IDR_2 TCONRI ODR_2 Reset Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Module Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized A/D converter -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized WDT_1 Initialized Initialized XBS Initialized TMR_X Initialized TMR_Y Initialized INT Initialized TMR_X Initialized TMR_Y Initialized PORT Initialized TMR_X Initialized TMR_Y Initialized INT Initialized TMR_X Initialized TMR_Y -- XBS Initialized -- Initialized -- -- -- Initialized TMR_X Initialized TMR_Y -- XBS Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized TMR_X Initialized TMR_Y Initialized XBS Initialized TMR_X Initialized Initialized D/A converter Initialized Initialized -- XBS Initialized -- -- -- Initialized Timer connection -- XBS Rev. 3.00 Mar 21, 2006 page 687 of 788 REJ09B0300-0300 Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation TCONRO STR_2 TCONRS SEDGR Reset Watch -- -- -- -- Sleep -- -- -- -- SubActive -- -- -- -- SubSleep -- -- -- -- Module Stop -- -- -- -- Software Hardware Standby Standby Module -- -- -- -- Initialized Timer connection Initialized XBS Initialized Timer connection Initialized -- Initialized -- Initialized -- Initialized -- Initialized Notes: 1. Can be used on the H8S/2160B and H8S/2161B. 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.00 Mar 21, 2006 page 688 of 788 REJ09B0300-0300 Section 26 List of Registers 26.4 Register Select Conditions Register Name PGNOCR PENOCR PFNOCR PCNOCR PDNOCR TWR0MW TWR0SW MSTP = 0, (HI12E = 0)* MSTP = 0, (HI12E = 0)* LPC H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition -- H8S/2160B, H8S/2161B Register Select Condition No condition Module Name PORT Lower Address H'FE16 H'FE18 H'FE19 H'FE1C H'FE1D H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 Rev. 3.00 Mar 21, 2006 page 689 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FE30 H'FE31 H'FE32 H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3C H'FE3D H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FE46 H'FE47 Register Name IDR3 ODR3 STR3 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB PGODR PGPIN (read) PGDDR (write) H'FE48 H'FE49 H'FE4A PEODR PFODR PEPIN (read) PEDDR (write) H'FE4B PFPIN (read) PFDDR (write) H'FE4C H'FE4D PCODR PDODR No condition -- No condition No condition INT PORT H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition MSTP = 0, (HI12E = 0)* H8S/2160B, H8S/2161B Register Select Condition MSTP = 0, (HI12E = 0)* Module Name LPC Rev. 3.00 Mar 21, 2006 page 690 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FE4E Register Name PCPIN (read) PCDDR (write) H'FE4F PDPIN (read) PDDDR (write) H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FED4 H'FED5 H'FED8 H'FED9 H'FEDA H'FEDC H'FEDD H'FEDE H'FEE0 H'FEE1 H'FEE2 H'FEE4 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED HICR2 IDR_3 ODR_3 STR_3 IDR_4 ODR_4 STR_4 ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCRH_1 KBCRL_1 KBBR_1 KBCRH_2 KBCRL_2 KBBR_2 KBCOMP DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL No condition MSTP4 = 0 No condition No condition MSTP4 = 0 No condition IrDA/ expanded A/D IIC_0 INT MSTP2 = 0 MSTP2 = 0 No condition No condition IIC_0 IIC_1 Keyboard buffer controller MSTP2 = 0 MSTP2 = 0 XBS H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition -- H8S/2160B, H8S/2161B Register Select Condition No condition Module Name PORT Rev. 3.00 Mar 21, 2006 page 691 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FF80 H'FF81 H'FF82 Register Name DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC FLMCR1 FLMCR2 PCSR EBR1 H'FF83 SYSCR2 EBR2 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 H'FF89 BRR_1 ICSR_1 MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR MSTP6 = 0,IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR SCI_1 IIC_1 SCI_1 IIC_1 FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR PWM FLASH SYSTEM FLASH SYSTEM FLSHE = 1 in STCR FLSHE = 1 in STCR FLASH No condition No condition INT H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition No condition H8S/2160B, H8S/2161B Register Select Condition No condition Module Name DTC Rev. 3.00 Mar 21, 2006 page 692 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E Register Name SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 H'FF8F ICMR_1 SAR_1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 TIER TCSR FRCH FRCL OCRAH OCRBH H'FF95 OCRAL OCRBL H'FF96 H'FF97 H'FF98 TCR TOCR ICRAH OCRARH ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR MSTP13 = 0 OCRS = 0 in TOCR OCRS = 1 in TOCR OCRS = 0 in TOCR OCRS = 1 in TOCR MSTP13 = 0 OCRS = 0 in TOCR OCRS = 1 in TOCR OCRS = 0 in TOCR OCRS = 1 in TOCR FRT MSTP13 = 0 MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR ICE = 1 in ICCR1 ICE = 0 in ICCR1 ICE = 1 in ICCR1 ICE = 0 in ICCR1 MSTP13 = 0 MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR ICE = 1 in ICCR1 ICE = 0 in ICCR1 ICE = 1 in ICCR1 ICE = 0 in ICCR1 FRT IIC_1 H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition MSTP6 = 0 H8S/2160B, H8S/2161B Register Select Condition MSTP6 = 0 Module Name SCI_1 Rev. 3.00 Mar 21, 2006 page 693 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FF99 Register Name ICRAL OCRARL H'FF9A ICRBH OCRAFH H'FF9B ICRBL OCRAFL H'FF9C ICRCH OCRDMH H'FF9D ICRCL OCRDML H'FF9E H'FF9F H'FFA0 ICRDH ICRDL SMR_2 DADRAH MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, REGS = 0 in IICE = 1 in DACNT/ STCR DADRB REGS = 1 in DACNT/ DADRB MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, REGS = 0 in IICE = 1 in DACNT/ STCR DADRB MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, REGS = 0 in IICE = 1 in DACNT/ STCR DADRB REGS = 1 in DACNT/ DADRB MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, REGS = 0 in IICE = 1 in DACNT/ STCR DADRB SCI_2 PWMX SCI_2 PWMX H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition MSTP13 = 0 ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR H8S/2160B, H8S/2161B Register Select Condition MSTP13 = 0 ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR Module Name FRT DACR H'FFA1 BRR_2 DADRAL Rev. 3.00 Mar 21, 2006 page 694 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 Register Name SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DADRBH MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, REGS = 0 in IICE = 1 in DACNT/ STCR DADRB REGS = 1 in DACNT/ DADRB REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB No condition No condition MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, REGS = 0 in IICE = 1 in DACNT/ STCR DADRB REGS = 1 in DACNT/ DADRB REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB WDT_0 SCI_2 PWMX H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition MSTP5 = 0 H8S/2160B, H8S/2161B Register Select Condition MSTP5 = 0 Module Name SCI_2 DACNTH H'FFA7 DADRBL DACNTL H'FFA8 TCSR_0 TCNT_0 (write) H'FFA9 H'FFAA H'FFAB TCNT_0 (read) PAODR PAPIN (read) PADDR (write) No condition No condition PORT H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR Rev. 3.00 Mar 21, 2006 page 695 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD Register Name P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR P8DDR (write) PBPIN (read) H'FFBE P7PIN (read) PBDDR (write) H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 MSTP12 = 0 MSTP12 = 0 TMR_0, TMR_1 No condition No condition BSC No condition No condition No condition No condition INT SYSTEM H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition No condition H8S/2160B, H8S/2161B Register Select Condition No condition Module Name PORT Rev. 3.00 Mar 21, 2006 page 696 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 Register Name PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR0 to PWDR15 SMR_0 ICCR_0 H'FFD9 BRR_0 ICSR_0 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 H'FFDF ICMR_0 SAR_0 MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR ICE = 1 in ICCR0 ICE = 0 in ICCR0 ICE = 1 in ICCR0 ICE = 0 in ICCR0 MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR ICE = 1 in ICCR0 ICE = 0 in ICCR0 ICE = 1 in ICCR0 ICE = 0 in ICCR0 IIC_0 MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR MSTP7 = 0 MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR MSTP7 = 0 SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 MSTP11 = 0 MSTP11 = 0 PWM H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition No condition H8S/2160B, H8S/2161B Register Select Condition No condition Module Name PWM MSTP4 = 0, IICE = 1 in STCR MSTP4 = 0, IICE = 1 in STCR Rev. 3.00 Mar 21, 2006 page 697 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA Register Name ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 (write) H'FFEB H'FFF0 TCNT_1 (read) HICR TCR_X TCR_Y H'FFF1 KMIMR TCSR_X TCSR_Y MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS XBS TMR_X TMR_Y INT TMR_X TMR_Y No condition No condition WDT_1 H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition MSTP9 = 0 H8S/2160B, H8S/2161B Register Select Condition MSTP9 = 0 Module Name A/D MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS Rev. 3.00 Mar 21, 2006 page 698 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FFF2 Register Name KMPCR TICRR TCORA_Y H'FFF3 KMIMRA TICRF TCORB_Y H'FFF4 IDR_1 TCNT_X TCNT_Y H'FFF5 ODR_1 TCORC TISR H'FFF6 STR_1 TCORA_X H'FFF7 TCORB_X H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS H8S/2160B, H8S/2161B Register Select Condition MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS Module Name PORT TMR_X TMR_Y INT TMR_X TMR_Y XBS TMR_X TMR_Y XBS TMR_X TMR_Y XBS TMR_X MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMRX/Y = 1 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS Rev. 3.00 Mar 21, 2006 page 699 of 788 REJ09B0300-0300 Section 26 List of Registers Lower Address H'FFF8 H'FFF9 H'FFFA H'FFFC Register Name DADR0 DADR1 DACR IDR_2 TCONRI H'FFFD ODR_2 TCONRO H'FFFE STR_2 TCONRS H'FFFF SEDGR MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR XBS Timer connection XBS Timer connection XBS Timer connection H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition MSTP10 = 0 H8S/2160B, H8S/2161B Register Select Condition MSTP10 = 0 Module Name D/A Note: * Although setting the XBS corresponding bits does not affected to the LPC operation, the HI12E bit in SYSCR2 must not be set to 1 to use the LPC according to the limitation depending on the program development tool (emulator) configuration. Rev. 3.00 Mar 21, 2006 page 700 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Section 27 Electrical Characteristics 27.1 Electrical Characteristics of H8S/2140B, H8S/2141B, H8S/2160B, and H8S/2161B Absolute Maximum Ratings 27.1.1 Table 27.1 lists the absolute maximum ratings. Table 27.1 Absolute Maximum Ratings Item Power supply voltage I/O buffer power supply voltage Input voltage (except ports 6, 7, and A, P97, P86, P52, and P42) (Ports C to G are added in the H8S/2160B and H8S/2161B.) Input voltage (CIN input not selected for port 6) Input voltage (CIN input not selected for port A) Input voltage (CIN input selected for port 6) Input voltage (CIN input selected for port A) Input voltage (P97, P86, P52, P42) Input voltage (port 7) Reference supply voltage Analog power supply voltage Analog input voltage Operating temperature Operating temperature (flash memory programming/erasing) Symbol VCC, VCL VCCB Vin Value -0.3 to +4.3 -0.3 to +7.0 -0.3 to VCC + 0.3 Unit V V V Vin Vin Vin Vin Vin Vin AVref AVCC VAN Topr Topr -0.3 to VCC + 0.3 -0.3 to VCCB + 0.3 -0.3 V to lower of voltages VCC + 0.3 and AVCC + 0.3 -0.3 V to lower of voltages VCCB + 0.3 and AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +4.3 -0.3 to AVCC + 0.3 -20 to +75 -20 to +75 V V V V V V V V V C C Storage temperature Tstg -55 to +125 C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Ensure so that the impressed voltage does not exceed 4.3 V for pins for which the maximum rating is determined by the voltage on the VCC, AVCC, and VCL pins, or 7.0 V for pins for which the maximum rating is determined by VCCB. The VCC and VCL pins must be connected to the Vcc power supply. Rev. 3.00 Mar 21, 2006 page 701 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.1.2 DC Characteristics Table 27.2 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 27.3 and 27.4, respectively. Table 27.2 DC Characteristics (1) 9 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 1 AVref* = 2.7 V to AVCC, VSS = AVSS* = 0 V, Ta = -20 to +75C Item 8 Symbol - Min VCC x 0.2 VCCB x 0.2 -- Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VCC x 0.7 VCCB x 0.7 -- -- VCC x 0.7 -- -- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 VCC + 0.3 VCCB + 0.3 Unit V Test Conditions Schmitt (1)* VT 26 P67 to P60* * , trigger input 7 KIN15 to KIN8* , voltage + *3, VT IRQ2 to IRQ0 IRQ5 to IRQ3 VT - VT Schmitt P67 to P60 trigger input (KWUL = 00) voltage (in level 6 switching)* P67 to P60 (KWUL = 01) VT VT VT VT VT VT VT VT - + + - + + - + + - + + - - - - + - VCC x 0.05 VCCB x 0.05 VCC x 0.2 -- VCC x 0.05 VCC x 0.3 -- VCC x 0.05 VCC x 0.4 -- VCC x 0.03 VCC x 0.45 -- 0.05 VCC x 0.9 VCC x 0.7 VCCB x 0.7 V VT - VT VT - VT P67 to P60 (KWUL = 10) VT - VT P67 to P60 (KWUL = 11) VT - VT Input high voltage RES, STBY, (2) NMI, MD1, MD0 EXTAL 7 PA7 to PA0* VIH V Rev. 3.00 Mar 21, 2006 page 702 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Conditions Item Input high voltage Port 7 P97, P86, P52, P42 Input pins except (1) and (2) above (Ports C to G are added in the H8S/2160B and H8S/2161B.) Input low voltage RES, STBY, MD1, MD0 PA7 to PA0 (3) (2) Symbol VIH Min VCC x 0.7 VCC x 0.7 VCC x 0.7 Typ -- -- -- Max Unit AVCC + 0.3 V 5.5 VCC + 0.3 VIL -0.3 -0.3 -- -- VCC x 0.1 VCCB x 0.2 0.8 V VCCB = 2.7 V to 4.0 V VCCB = 4.0 V to 5.5 V VCC = 2.7 V to 3.6 V NMI, EXTAL, input pins except (1) and (3) above (Ports C to G are added in the H8S/2160B and H8S/2161B.) Output high All output pins voltage (except P97, P86, P52, and 458 P42)* * * (Ports C to F are added in the H8S/2160B and H8S/2161B.) P97, P86, P52, and 4 P42* (Port G is added in the H8S/2160B and H8S/2161B.) VOH -0.3 -- VCC x 0.2 VCC - 0.5 -- VCCB - 0.5 VCC - 1.0 -- VCCB - 1.0 -- -- V V IOH = -200 A IOH = -1 mA, (VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 4.5 V) IOH = -200 A 0.5 -- -- V Rev. 3.00 Mar 21, 2006 page 703 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Conditions IOL = 1.6 mA Item Output low voltage All output pins 5 (except RESO)* (Ports C to G are added in the H8S/2160B and H8S/2161B.) Ports 1 to 3 RESO Symbol VOL Min -- Typ -- Max 0.4 Unit V -- -- -- -- 1.0 0.4 V V IOL = 5 mA IOL = 1.6 mA Notes: 1. Do not leave the AVcc, AVref, and AVss pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. 2. P67 to P60 include peripheral module inputs multiplexed on those pins. 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4. P52/SCK0/SCL0, P97/SDA0, P86/SCK1/SCL1, P42/SCK2/SDA1, and port G are NMOS push-pull outputs. When the SCL0, SDA0, SCL1, or SDA1 (ICE = 1) pin is used as an output, it is NMOS open-drain output. Therefore, an external pull-up resistor must be connected in order to output high level. P52/SCK0, P97, P86/SCK1, P42/SCK2 (ICE = 0), and port G high levels are driven by NMOS. An external pull-up resistor is necessary to provide high-level output from SCK0, SCK1, and SCK2. 5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. The upper limit of the port A applied voltage is VCCB + 0.3 V when CIN input is not selected, and the lower of VCCB + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 8. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. 9. For flash memory programming/erasure, the applicable range is VCC = 3.0 V to 3.6 V. Rev. 3.00 Mar 21, 2006 page 704 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.2 DC Characteristics (2) 5 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 1 AVref* = 2.7 V to AVCC, VSS = AVSS* = 0 V, Ta = -20 to +75C Item Input leakage current RES STBY, NMI, MD1, MD0 Port 7 Three-state leakage current (off state) Input pull-up MOS current 4 Ports 1 to 6, 8, 9, A* , and B (Ports C to G are added in the H8S/2160B and H8S/2161B.) Symbol Iin Min -- -- -- Typ -- -- -- -- Max 10.0 1.0 1.0 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V ITSI -- A Vin = 0.5 to VCC - 0.5 V, Vin = 0.5 to VCCB - 0.5 V Vin = 0 V, VCC = 2.7 V to 3.6 V VCCB = 2.7 V to 5.5 V Ports 1 to 3 Ports 6 (P6PUE = 0) and B (Ports C to F are added in the H8S/2160B and H8S/2161B.) Ports A* 4 -IP 5 30 -- -- 150 300 A 30 3 Cin -- -- -- -- -- -- -- -- -- -- 600 100 80 50 20 15 pF pF pF pF Vin = 0 V, f = 1 MHz, Ta = 25C Port 6 (P6PUE = 1) Input RES capacitance NMI P52, P97, P42, P86, PA7 to PA2 Input pins except (4) above (Ports C to G are added in the H8S/2160B and H8S/2161B.) (4) Rev. 3.00 Mar 21, 2006 page 705 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Conditions f = 10 MHz f = 10 MHz Ta 50C 50C < Ta mA A mA AVCC = 2.0 V to 3.6 V Item Normal operation Current 2 dissipation* Sleep mode 3 Standby mode* Symbol ICC Min -- -- -- -- Typ 30 20 1 -- 1.2 0.01 0.5 2.0 0.01 -- -- -- Max 40 32 5.0 20.0 2.0 5.0 1.0 5.0 5.0 3.6 3.6 -- Unit mA mA A Analog power supply current Reference power supply current During A/D, D/A conversion Idle AlCC -- -- -- -- -- During A/D conversion Alref During A/D, D/A conversion Idle A V AVref = 2.0 V to AVCC Operating Idle/not used Analog power supply voltage* 1 AVCC VRAM 2.7 2.0 RAM standby voltage 2.0 V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. 2. Current dissipation values are for VIH min = VCC - 0.2 V, VCCB - 0.2 V, and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 3. The values are for VRAM VCC < 2.7 V, VIH min = VCC- 0.2 V, VCCB - 0.2 V, and VIL max = 0.2 V. 4. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. 5. For flash memory programming/erasure, the applicable range is VCC = 3.0 V to 3.6 V. Rev. 3.00 Mar 21, 2006 page 706 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.2 DC Characteristics (3) When LPC Function Is Used Conditions: VCC = 3.0 V to 3.6 V, VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 AVref* = 2.7 V to AVCC, VSS = AVSS* = 0 V, Ta = -20 to +75C Item Input high voltage Input low voltage Output high voltage Output low voltage Note: * P37 to P30, P83 to P80, PB1, PB0 P37 to P30, P83 to P80, PB1, PB0 P37, P33 to P30, P82 to P80, PB1, PB0 P37, P33 to P30, P82 to P80, PB1, PB0 Symbol VIH Min VCC x 0.5 Max -- Unit V Test Conditions VIL -- VCC x 0.3 V VOH VCC x 0.9 -- V IOH = -0.5 mA VOL -- VCC x 0.1 V IOL = 1.5 mA Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. Rev. 3.00 Mar 21, 2006 page 707 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.3 Permissible Output Currents Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C Item Permissible output low current (per pin) SCL1, SCL0, SDA1, SDA0, PS2AC to PS2CC, PS2AD to PS2CD, PA7 to PA4 (bus drive function selected) Ports 1 to 3 RESO Other output pins Permissible output low current (total) Total of ports 1 to 3 Total of all output pins, including the above All output pins Total of all output pins -IOH -IOH IOL Symbol IOL Min -- Typ -- Max 10 Unit mA -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 1 1 40 60 2 30 mA mA mA Permissible output high current (per pin) Permissible output high current (total) Notes: 1. To protect chip reliability, do not exceed the output current values in table 27.3. 2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as show in figures 27.1 and 27.2. This LSI 2 k Port Darlington pair Figure 27.1 Darlington Pair Drive Circuit (Example) Rev. 3.00 Mar 21, 2006 page 708 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics This LSI 600 Ports 1 to 3 LED Figure 27.2 LED Drive Circuit (Example) Table 27.4 Bus Drive Characteristics Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, Ta = -20 to +75C Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol VT VT - + + - Min VCC x 0.3 -- VCC x 0.05 VCC x 0.7 -0.5 -- -- Typ -- -- -- -- -- -- -- -- -- Max -- VCC x 0.7 -- 5.5 VCC x 0.3 0.5 0.4 20 1.0 250 Unit V Test Conditions VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V VT - VT Input high voltage Input low voltage Output low voltage VIH VIL VOL Cin V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V IOL = 8 mA IOL = 3 mA Vin = 0 V, f = 1 MHz, Ta = 25C Vin = 0.5 to VCC - 0.5 V VCC = 2.7 V to 3.6 V V Input capacitance -- -- pF A ns Three-state leakage | ITSI | current (off state) SCL, SDA output fall time tOf 20 + 0.1Cb -- Rev. 3.00 Mar 21, 2006 page 709 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive function selected) Item Output low voltage Symbol VOL Min -- -- -- Typ -- -- -- Max 0.8 0.5 0.4 Unit V Test Conditions IOL = 16 mA, VCCB = 4.5 V to 5.5 V IOL = 8 mA IOL = 3 mA 27.1.3 AC Characteristics Figure 27.3 shows the test conditions for the AC characteristics. VCC RL Chip output pin C = 30 pF: All output ports RL = 2.4 k RH = 12 k I/O timing test levels * Low level: 0.8 V * High level: 2.0 V C RH Figure 27.3 Output Load Circuit Rev. 3.00 Mar 21, 2006 page 710 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Clock Timing: Table 27.5 shows the clock timing. The clock timing specified here covers clock () output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details on external clock input (EXTAL pin and EXCL pin) timing, see section 25, Clock Pulse Generator. Table 27.5 Clock Timing Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Oscillation settling time at reset (crystal) Oscillation settling time in software standby (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT Min 100 30 30 -- -- 20 8 500 Max 500 -- -- 20 20 -- -- -- Unit ns ns ns ns ns ms ms s Figure 27.7 Figure 27.8 Figure 27.7 Reference Figure 27.6 Figure 27.6 Rev. 3.00 Mar 21, 2006 page 711 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Control Signal Timing: Table 27.6 shows the control signal timing. The only external interrupts that can operate on the subclock ( = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 27.6 Control Signal Timing Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item RES setup time RES pulse width NMI setup time (NMI) NMI hold time (NMI) NMI pulse width (exiting software standby mode) IRQ setup time (IRQ7 to IRQ0) IRQ hold time(IRQ7 to IRQ0) IRQ pulse width (IRQ7, IRQ6, IRQ2 to IRQ0) (exiting software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min 300 20 250 10 200 250 10 200 Max -- -- -- -- -- -- -- -- Unit ns tcyc ns ns ns ns ns ns Figure 27.10 Test Conditions Figure 27.9 Rev. 3.00 Mar 21, 2006 page 712 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Bus Timing: Table 27.7 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock ( = 32.768 kHz). Table 27.7 Bus Timing (1) (Normal Mode) Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item Address delay time Address setup time Address hold time CS delay time (IOS) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 HWR, LWR delay time 1 HWR, LWR delay time 2 HWR, LWR pulse width 1 HWR, LWR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time Symbol tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH Min -- 0.5 x tcyc - 30 0.5 x tcyc - 20 -- -- -- -- 35 0 -- -- -- -- -- -- -- 1.0 x tcyc - 40 1.5 x tcyc - 40 -- 0 20 60 10 Max 40 -- -- 40 60 60 60 -- -- 1.0 x tcyc - 60 1.5 x tcyc - 50 2.0 x tcyc - 60 2.5 x tcyc - 50 3.0 x tcyc - 60 60 60 -- -- 60 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 27.11 to 27.15 Rev. 3.00 Mar 21, 2006 page 713 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.7 Bus Timing (2) (Advanced Mode) Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item Address delay time Address setup time Address hold time CS delay time (IOS) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 HWR, LWR delay time 1 HWR, LWR delay time 2 HWR, LWR pulse width 1 HWR, LWR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time Symbol tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH Min -- 0.5 x tcyc - 30 0.5 x tcyc - 20 -- -- -- -- 35 0 -- -- -- -- -- -- -- 1.0 x tcyc - 40 1.5 x tcyc - 40 -- 0 20 60 10 Max 60 -- -- 60 60 60 60 -- -- 1.0 x tcyc - 80 1.5 x tcyc - 50 2.0 x tcyc - 80 2.5 x tcyc - 50 3.0 x tcyc - 80 60 60 -- -- 60 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 27.11 to 27.15 Rev. 3.00 Mar 21, 2006 page 714 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Timing of On-Chip Peripheral Modules: Tables 27.8 to 27.11 show the on-chip peripheral module timing. The only on-chip peripheral modules that can operate in subclock operation ( = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0 to 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 27.8 Timing of On-Chip Peripheral Modules (1) Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 32.768 kHz*, 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item I/O ports Output data delay time Input data setup time Input data hold time FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width PWM, PWMX SCI Single edge Both edges tFTCWH tFTCWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tPWOD tScyc tSCKW tSCKr tSCKf 1.5 2.5 -- 50 50 1.5 2.5 -- 4 6 0.4 -- -- -- -- 100 -- -- -- -- 100 -- -- 0.6 1.5 1.5 tScyc tcyc ns tcyc Figure 27.22 Figure 27.23 tcyc ns Figure 27.19 Figure 27.21 Figure 27.20 tcyc Symbol tPWD tPRS tPRH tFTOD tFTIS tFTCS Min -- 50 50 -- 50 50 Max 100 -- -- 100 -- -- Figure 27.18 ns Figure 27.17 Unit ns Test Conditions Figure 27.16 Pulse output delay time Input clock cycle Asynchronous Synchronous Input clock pulse width Input clock rise time Input clock fall time Rev. 3.00 Mar 21, 2006 page 715 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Condition 10 MHz Item SCI Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter WDT Trigger input setup time RESO output delay time RESO output pulse width Symbol tTXD tRXS tRXH tTRGS tRESD tRESOW Min -- 100 100 50 -- 132 Max 100 -- -- -- 200 -- Unit ns ns ns ns ns tcyc Figure 27.25 Figure 27.26 Test Conditions Figure 27.24 Note: * Only peripheral modules that can be used in subclock operation Table 27.8 Timing of On-Chip Peripheral Modules (2) Condition: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item XBS read CS/HA0 setup time cycle CS/HA0 hold time IOR pulse width HDB delay time HDB hold time HIRQ delay time XBS write CS/HA0 setup time cycle CS/HA0 hold time IOW pulse width Symbol tHAR tHRA tHRPW tHRD tHRF tHIRQ tHAW tHWA tHWPW Min 10 10 220 -- 0 -- 10 10 100 50 85 tHWD tHGA 25 -- Max -- -- -- 200 40 200 -- -- -- -- -- -- 180 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 27.27 HDB setup Fast A20 gate not tHDW time used Fast A20 gate used HDB hold time GA20 delay time Rev. 3.00 Mar 21, 2006 page 716 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.9 Keyboard Buffer Controller Timing Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Ratings Item KCLK, KD output fall time KCLK, KD input data hold time KCLK, KD input data setup time KCLK, KD output delay time KCLK, KD capacitive load 2 Symbol tKBF tKBIH tKBIS tKBOD Cb Min Typ Max 250 -- -- 450 400 Test Unit Conditions Notes ns ns ns ns pF Figure 27.28 20 + 0.1 Cb -- 150 150 -- -- -- -- -- -- Table 27.10 I C Bus Timing Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 5 MHz to maximum operating frequency, Ta = -20 to +75C Ratings Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Note: * Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min 12 3 5 -- -- -- 5 3 3 3 0.5 0 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 7.5* 300 1 -- -- -- -- -- -- 400 Unit tcyc tcyc tcyc tcyc ns tcyc tcyc tcyc tcyc tcyc tcyc ns pF 2 Test Conditions Notes Figure 27.29 17.5 tcyc can be set according to the clock selected for use by the I C module. For details, see section 16.6, Usage Notes. Rev. 3.00 Mar 21, 2006 page 717 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.11 LPC Module Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Item LPC Input clock cycle Input clock pulse width (H) Input clock pulse width (L) Transmit signal delay time Symbol tLcyc tLCKH tLCKL tTXD Min 30 11 11 2 -- 7 0 Typ -- -- -- -- -- -- -- Max -- -- -- 11 28 -- -- Unit ns Test Conditions Figure 27.30 Transmit signal floating delay tOFF time Receive signal setup time Receive signal hold time tRXS tRXH Rev. 3.00 Mar 21, 2006 page 718 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.1.4 A/D Conversion Characteristics Tables 27.12 and 27.13 list the A/D conversion characteristics. Table 27.12 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VCCB = 2.7 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 13.4 20 5 7.0 7.5 7.5 0.5 8.0 Unit bits s pF k LSB LSB LSB LSB LSB Rev. 3.00 Mar 21, 2006 page 719 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.13 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VCCB = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 13.4 20 5 11.0 11.5 11.5 0.5 12.0 Unit bits s pF k LSB LSB LSB LSB LSB Rev. 3.00 Mar 21, 2006 page 720 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.1.5 D/A Conversion Characteristics Table 27.14 lists the D/A conversion characteristics. Table 27.14 D/A Conversion Characteristics Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VCCB = 2.7 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition 10 MHz Item Resolution Conversion time Absolute accuracy With 20 pF load capacitance With 2 M load resistance With 4 M load resistance Min 8 -- -- -- Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit bits s LSB Rev. 3.00 Mar 21, 2006 page 721 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.1.6 Flash Memory Characteristics Table 27.15 shows the flash memory characteristics. Table 27.15 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = -20 to +75C Item Programming time*1 *2 *4 Erase time*1 *3 *6 Reprogramming count Data retention time*10 Programming Wait time after SWE-bit setting*1 Wait time after PSU-bit setting*1 Wait time after P-bit setting*1 *4 Symbol Min tP tE NWEC tDRP x y z1 z2 z3 Wait time after P-bit clear*1 Wait time after PSU-bit clear*1 Wait time after PV-bit setting*1 Wait time after dummy write* Wait time after PV-bit clear*1 Wait time after SWE-bit clear*1 Maximum programming count*1 *4 *5 Erase Wait time after SWE-bit setting*1 Wait time after ESU-bit setting*1 Wait time after E-bit setting*1 *6 Wait time after E-bit clear*1 Wait time after ESU-bit clear*1 Wait time after EV-bit setting*1 Wait time after dummy write*1 Wait time after EV-bit clear*1 Wait time after SWE-bit clear* Maximum erase count*1 *6 *7 1 1 Typ 10 100 Max 200 Unit ms/ 128 bytes Test Condition -- -- 1200 ms/block times Years s s s s s s s s s s s 1n6 7 n 1000 Additional write 100*8 10,000*9 -- 10 1 50 28 198 8 5 5 4 2 2 100 -- 1 100 10 10 10 20 2 4 100 -- -- -- -- 30 200 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 32 202 12 -- -- -- -- -- -- N x y z N 1000 times -- -- 100 -- -- -- -- -- -- 120 s s ms s s s s s s times Rev. 3.00 Mar 21, 2006 page 722 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = (wait time after P-bit setting (z1) + (z3)) x 6 + wait time after P-bit setting (z2) x ((N) - 6) 5. The maximun number of writes (N) should be set according to the actual set value of z1, z2 and z3 to allow programming within the maximum programming time (tP (max)). The wait time after P-bit setting (z1, z2, and z3) should be alternated according to the number of writes (n) as follows: 1n6 z1 = 30s, z3 = 10s 7 n 1000 z2 = 200s 6. Maximum erase time (tE (max)) tE (max) = Wait time after E-bit setting (z) x maximum erase count (N) 7. The maximum number of erases (N) should be set according to the actual set value of z to allow erasing within the maximum erase time (tE (max)). 8. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 9. Reference value for 25C (as a guideline, rewriting should normally function up to this value). 10. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. Rev. 3.00 Mar 21, 2006 page 723 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.1.7 Usage Note The method of connecting an external capacitor is shown in figure 27.4. Connect the system power supply to the VCL pin together with the VCC pins. Vcc power supply Bypass capacitor 10 F 0.01 F VCL VSS < Vcc = 2.7 V to 3.6 V > Connect the Vcc power supply to the chip's VCL pin in the same way as the VCC pins. It is recommended that a bypass capacitor be connected to the power supply pins. (Values are reference values.) Figure 27.4 Connection of VCL Capacitor Rev. 3.00 Mar 21, 2006 page 724 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.2 27.2.1 Electrical Characteristics of H8S/2145B and H8S/2148B Absolute Maximum Ratings Table 27.16 lists the absolute maximum ratings. Table 27.16 Absolute Maximum Ratings Item 1 Power supply voltage* Symbol VCC VCCB VCC VCL Vin Vin Vin Vin Vin Vin Vin AVref AVCC AVCC VAN Topr Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCCB + 0.3 -0.3 V to lower of voltages VCC + 0.3 and AVCC + 0.3 -0.3 V to lower of voltages VCCB + 0.3 and AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to +4.3 -0.3 to AVCC + 0.3 Normal specification product: -20 to +75 Wide range temperature specification product: -40 to +85 Unit V V V V V V V V V V V V V V V C I/O buffer power supply voltage (power supply for port A) Power supply voltage 1 (3-V version product)* 2 Power supply voltage (VCL pin)* Input voltage (except ports 6, 7, and A, P97, P86, P52, P42) Input voltage (CIN input not selected for port 6) Input voltage (CIN input not selected for port A) Input voltage (CIN input selected for port 6) Input voltage (CIN input selected for port A) Input voltage (P97, P86, P52, P42) Input voltage (port 7) Reference supply voltage Analog power supply voltage Analog power supply voltage (3-V version product) Analog input voltage Operating temperature Rev. 3.00 Mar 21, 2006 page 725 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Item Operating temperature (flash memory programming/erasing) Symbol Topr Value Normal specification product: -20 to +75 Wide range temperature specification product: -40 to +85 Tstg -55 to +125 C Unit C Storage temperature Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Ensure that for 5-V/4-V version products, the input pin voltage does not exceed 7.0 V, and for 3-V version products, all the input voltage except for port A does not exceed 4.3 V. Notes: 1. Voltage applied to the VCC1 pin. Since both the VCC1 pin and VCL pin are connected to the VCC power supply on low-power voltage (3-V) products, VCL ratings should not be exceeded. 2. Power supply voltage pin used for operation within the chip. Do not apply power supply voltage to the VCL pin on 5-V/4-V products. Be sure to insert an external capacitor between the VCL pin and GND to regulate the internal voltage. Rev. 3.00 Mar 21, 2006 page 726 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.2.2 DC Characteristics Table 27.17 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 27.18 and 27.19, respectively. Table 27.17 DC Characteristics (1) 1 Conditions: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, AVCC* = 5.0 V 10%, 1 1 AVref* = 4.5 V to AVCC, VSS = AVSS* = 0 V, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Item Symbol - Min 1.0 -- 0.4 VCC x 0.3 -- Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VCC x 0.7 VCCB x 0.7 -- -- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 VCC + 0.3 VCCB + 0.3 AVCC + 0.3 5.5 VCC + 0.3 Unit V Test Conditions Schmitt P67 to P60 (KWUL (1) VT 26 + trigger input = 00)* * , VT 78 KIN15 to KIN8* * , voltage 3 IRQ2 to IRQ0* , + - VT - VT IRQ5 to IRQ3 Schmitt P67 to P60 trigger input (KWUL = 01) voltage (in level 6 switching)* P67 to P60 (KWUL = 10) VT VT VT VT VT VT - + + - + + - + + - - - V VT - VT VCC x 0.05 VCC x 0.4 -- VCC x 0.03 VCC x 0.45 -- 0.05 VCC - 0.7 VCC x 0.7 VT - VT P67 to P60 (KWUL = 11) VT - VT Input high voltage RES, STBY, NMI, MD1, MD0 EXTAL PA7 to PA0* Port 7 P97, P86, P52, P42 Input pins except (1) and (2) above 7 (2) VIH V VCCB x 0.7 2.0 VCC x 0.7 2.0 Rev. 3.00 Mar 21, 2006 page 727 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Conditions Item Input low voltage RES, STBY, MD1, MD0 PA7 to PA0 NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage (except P97, P86, 58 P52, and P42)* * P97, P86, P52, and 4 P42* Output low voltage All output pins 5 (except RESO)* Ports 1 to 3 RESO (3) Symbol VIL Min -0.3 -0.3 -0.3 Typ -- -- -- Max 0.5 1.0 0.8 Unit V VOH VCC - 0.5 -- VCCB - 0.5 3.5 2.0 -- -- -- -- -- -- -- -- 0.4 1.0 0.4 V V V V V V IOH = -200 A IOH = -1 mA, IOH = -200 A IOL = 1.6 mA IOL = 10 mA IOL = 2.6 mA VOL -- -- -- Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. 2. P67 to P60 include peripheral module inputs multiplexed on those pins. 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4. P52/SCK0/SCL0, P97/SDA0, P86/SCK1/SCL1, P42/SCK2/SDA1, and port G are NMOS push-pull outputs. When the SCL0, SDA0, SCL1, or SDA1 (ICE = 1) pin is used as an output, it is NMOS open-drain output. Therefore, an external pull-up resistor must be connected in order to output high level. P52/SCK0, P97, P86/SCK1, P42/SCK2 (ICE = 0), and port G high levels are driven by NMOS. When the SCK0, SCK1, or SCK2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. 5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. The upper limit of the port A applied voltage is VCCB + 0.3 V when CIN input is not selected, and the lower of VCCB + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. Rev. 3.00 Mar 21, 2006 page 728 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 8. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC in output mode. Table 27.17 DC Characteristics (2) 1 Conditions: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, AVCC* = 5.0 V 10%, 1 1 AVref* = 4.5 V to AVCC, VSS = AVSS* = 0 V, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Item Input leakage current RES STBY, NMI, MD1, MD0 Port 7 Three-state Ports 1 to 6 4 leakage Ports 8, 9, A* , B current (off state) Input pull-up Ports 1 to 3 MOS current Ports A*4, B, 6 (P6PUE = 0) Port 6 (P6PUE = 1) Input RES capacitance NMI P52, P97, P42, P86, PA7 to PA2 Input pins except (4) above Current Normal operation 2 dissipation* Sleep mode 3 Standby mode* (4) Symbol Iin Min -- -- -- Typ -- -- -- -- Max 10.0 1.0 1.0 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V ITSI -- A Vin = 0.5 to VCC - 0.5 V, Vin = 0.5 to VCCB - 0.5 V Vin = 0 V -IP 30 60 15 -- -- -- -- -- -- -- 55 36 1.0 -- 1.2 0.01 300 600 200 80 50 20 15 70 55 5.0 20.0 2.0 5.0 A A A pF Cin -- -- -- -- Vin = 0 V, f = 1 MHz, Ta = 25C ICC -- -- -- -- mA mA A f = 20 MHz f = 20 MHz Ta 50C 50C < Ta Analog power supply current During A/D, D/A conversion Idle AlCC -- -- mA A AVCC = 2.0 V to 5.5 V Rev. 3.00 Mar 21, 2006 page 729 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Conditions Item Reference power supply current Symbol Min -- -- -- Typ 0.5 2.0 0.01 -- -- -- Max 1.0 5.0 5.0 5.5 5.5 -- Unit mA During A/D conversion Alref During A/D, D/A conversion Idle A V AVref = 2.0 V to AVCC Operating Idle/not used Analog power supply voltage* 1 AVCC VRAM 4.5 2.0 RAM standby voltage 2.0 V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. 2. Current dissipation values are for VIH min = VCC - 0.2 V, VCCB - 0.2 V, and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 3. The values are for VRAM VCC < 4.5 V, VIH min = VCC- 0.2 V, VCCB - 0.2 V, and VIL max = 0.2 V. 4. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. Rev. 3.00 Mar 21, 2006 page 730 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.17 DC Characteristics (3) 1 Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.5 V, 1 1 AVref* = 4.0 V to AVCC, VSS = AVSS* = 0 V, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Item Symbol - Min 1.0 -- 0.4 0.8 -- Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit V Test Conditions VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V VCC = 4.0 V to 5.5 V Schmitt P67 to P60 (KWUL (1) VT 26 trigger input = 00)* * , + VT 78 voltage KIN15 to KIN8* * , 3 IRQ2 to IRQ0* , + - VT - VT IRQ5 to IRQ3 VT VT - + VCC x 0.7 V VCCB x 0.7 -- -- VCC x 0.7 VCCB x 0.7 -- -- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 VCC + 0.3 VCCB + 0.3 AVCC + 0.3 5.5 VCC + 0.3 V V V VT - VT Schmitt P67 to P60 trigger input (KWUL = 01) voltage (in level 6 switching)* P67 to P60 (KWUL = 10) VT VT VT VT VT VT - + + - + + - + + + - 0.3 VCC x 0.3 -- VT - VT - VCC x 0.05 VCC x 0.4 -- VT - VT P67 to P60 (KWUL = 11) - VCC x 0.03 VCC x 0.45 -- VT - VT Input high voltage RES, STBY, NMI, MD1, MD0 EXTAL PA7 to PA0* Port 7 P97, P86, P52, P42 Input pins except (1) and (2) above 7 - 0.05 VCC - 0.7 VCC x 0.7 VCCB x 0.7 2.0 VCC x 0.7 2.0 (2) VIH Rev. 3.00 Mar 21, 2006 page 731 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Unit Conditions V VCCB = 4.5 V to 5.5 V VCCB = 4.0 V to 4.5 V Item Input low voltage RES, STBY, MD1, MD0 (3) Symbol VIL Min -0.3 -0.3 -0.3 -0.3 Typ -- -- -- -- Max 0.5 1.0 0.8 0.8 PA7 to PA0 NMI, EXTAL, input pins except (1) and (3) above Output high All output pins VOH voltage (except P97, P86, P52, 458 and P42)* * * -- VCC - 0.5 VCCB - 0.5 3.5 -- -- -- V V IOH = -200 A IOH = -1 mA, VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V IOH = -1 mA, VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V IOH = -200 A IOL = 1.6 mA IOL = 10 mA IOL = 2.6 mA 3.0 -- -- V P97, P86, P52, and 4 P42* Output low voltage All output pins 5 (except RESO)* Ports 1 to 3 RESO VOL 1.5 -- -- -- -- -- -- -- -- 0.4 1.0 0.4 V V V V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. 2. P67 to P60 include peripheral module inputs multiplexed on those pins. 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4. P52/SCK0/SCL0, P97/SDA0, P86/SCK1/SCL1, P42/SCK2/SDA1, and port G are NMOS push-pull outputs. When the SCL0, SDA0, SCL1, or SDA1 (ICE = 1) pin is used as an output, it is NMOS open-drain output. Therefore, an external pull-up resistor must be connected in order to output high level. P52/SCK0, P97, P86/SCK1, P42/SCK2 (ICE = 0), and port G high levels are driven by NMOS. Rev. 3.00 Mar 21, 2006 page 732 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics When the SCK0, SCK1, or SCK2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. The upper limit of the port A applied voltage is VCCB + 0.3 V when CIN input is not selected, and the lower of VCCB + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. 5. 6. 7. 8. Rev. 3.00 Mar 21, 2006 page 733 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.17 DC Characteristics (4) 1 Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.5 V, 1 1 AVref* = 4.0 V to AVCC, VSS = AVSS* = 0 V, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Item Input leakage current RES STBY, NMI, MD1, MD0 Port 7 Three-state Ports 1 to 6, 8, 9, 4 leakage A* , B current (off state) Input pull-up Ports 1 to 3 MOS current Ports A*4, B, 6 (P6PUE = 0) Port 6 (P6PUE = 1) Ports 1 to 3 4 Ports A* , B, 6 (P6PUE = 0) Port 6 (P6PUE = 1) Input RES capacitance NMI P52, P97, P42, P86, PA7 to PA2 Input pins except (4) above Current Normal operation 2 dissipation* Sleep mode 3 Standby mode* (4) Symbol Iin Min -- -- -- Typ -- -- -- -- Max 10.0 1.0 1.0 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V ITSI -- A Vin = 0.5 to VCC - 0.5 V, Vin = 0.5 to VCCB - 0.5 V Vin = 0 V, VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V Vin = 0 V, VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V Vin = 0 V, f = 1 MHz, Ta = 25C -IP 30 60 15 20 40 10 -- -- -- -- -- -- -- -- -- -- 45 30 1.0 -- 300 600 200 200 500 150 80 50 20 15 58 46 5.0 20.0 A A Cin -- -- -- -- pF ICC -- -- -- -- mA mA A f = 16 MHz f = 16 MHz Ta 50C 50C < Ta Rev. 3.00 Mar 21, 2006 page 734 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Conditions Item Analog power supply current Reference power supply current During A/D, D/A conversion Idle Symbol AlCC Min -- -- -- -- -- Typ 1.2 0.01 0.5 2.0 0.01 -- -- -- Max 2.0 5.0 1.0 5.0 5.0 5.5 5.5 -- Unit mA A mA AVCC = 2.0 V to 5.5 V During A/D conversion Alref During A/D, D/A conversion Idle A V AVref = 2.0 V to AVCC Operating Idle/not used 1 Analog power supply voltage* AVCC VRAM 4.0 2.0 RAM standby voltage 2.0 V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. 2. Current dissipation values are for VIH min = VCC - 0.2 V, VCCB - 0.2 V, and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 3. Current dissipation values are for VIH min = VCC - 0.2 V, VCCB - 0.2 V, and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 4. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. Rev. 3.00 Mar 21, 2006 page 735 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.17 DC Characteristics (5) 9 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 AVref = 2.7 V to 3.6 V, VSS = AVSS* = 0 V, Ta = -20 to +75C Item Symbol - Min VCC x 0.2 VCCB x 0.2 -- VCC x 0.05 VCCB x 0.05 VCC x 0.3 -- Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VCC x 0.7 VCCB x 0.7 -- -- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 VCC + 0.3 VCCB + 0.3 AVCC + 0.3 5.5 VCC + 0.3 Unit V Test Conditions Schmitt P67 to P60 (KWUL (1) VT 26 trigger input = 00)* * , 78 + KIN15 to KIN8* * , voltage VT *3, IRQ2 to IRQ0 IRQ5 to IRQ3 + - VT - VT Schmitt P67 to P60 trigger input (KWUL = 01) voltage (in level 6 switching)* P67 to P60 (KWUL = 10) VT VT VT VT VT VT - + + - + + - + + - - - V VT - VT VCC x 0.05 VCC x 0.4 -- VCC x 0.03 VCC x 0.45 -- 0.05 VCC x 0.9 VCC x 0.7 VCCB x 0.7 VCC x 0.7 VCC x 0.7 VCC x 0.7 VT - VT P67 to P60 (KWUL = 11) VT - VT Input high voltage RES, STBY, NMI, MD1, MD0 EXTAL 7 PA7 to PA0* (2) VIH V Port 7 P97, P86, P52, P42 Input pins except (1) and (2) above Rev. 3.00 Mar 21, 2006 page 736 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Unit Conditions V VCCB = 2.7 V to 4.0 V VCCB = 4.0 V to 5.5 V VCC = 2.7 V to 3.6 V V V IOH = -200 A IOH = -1 mA, VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 4.0 V IOH = -200 A IOL = 1.6 mA IOL = 5 mA IOL = 1.6 mA Item Input low voltage RES, STBY, MD1, MD0 PA7 to PA0 (3) Symbol VIL Min -0.3 -0.3 Typ -- -- Max VCC x 0.1 VCCB x 0.2 0.8 NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage (except P97, P86, 458 P52, and P42)* * * VOH -0.3 -- VCC x 0.2 VCC - 0.5 -- VCCB - 0.5 VCC - 1.0 -- VCCB - 1.0 -- -- P97, P86, P52, and 4 P42* Output low voltage All output pins 5 (except RESO)* Ports 1 to 3 RESO VOL 0.5 -- -- -- -- -- -- -- -- 0.4 1.0 0.4 V V V V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. 2. P67 to P60 include peripheral module inputs multiplexed on those pins. 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4. P52/SCK0/SCL0, P97/SDA0, P86/SCK1/SCL1, P42/SCK2/SDA1, and port G are NMOS push-pull outputs. When the SCL0, SDA0, SCL1, or SDA1 (ICE = 1) pin is used as an output, it is NMOS open-drain output. Therefore, an external pull-up resistor must be connected in order to output high level. P52/SCK0, P97, P86/SCK1, P42/SCK2 (ICE = 0), and port G high levels are driven by NMOS. When the SCK0, SCK1, or SCK 2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. Rev. 3.00 Mar 21, 2006 page 737 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. The upper limit of the port A applied voltage is VCCB + 0.3 V when CIN input is not selected, and the lower of VCCB + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 8. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. 9. For flash memory programming/erasure, the applicable range is VCC = 3.0 V to 3.6 V. Rev. 3.00 Mar 21, 2006 page 738 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.17 DC Characteristics (6) 5 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 1 AVref * = 2.7 V to 3.6 V, VSS = AVSS* = 0 V, Ta = -20 to +75C Item Input leakage current RES STBY, NMI, MD1, MD0 Port 7 Three-state Ports 1 to 6 4 leakage Ports 8, 9, A* , B current (off state) Input pull-up Ports 1 to 3 MOS current Ports A*4, B, 6 (P6PUE = 0) Port 6 (P6PUE = 1) Input RES capacitance NMI P52, P97, P42, P86, PA7 to PA2 Input pins except (4) above Current Normal operation 2 dissipation* Sleep mode 3 Standby mode* (4) Symbol Iin Min -- -- -- Typ -- -- -- -- Max 10.0 1.0 1.0 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V ITSI -- A Vin = 0.5 to VCC - 0.5 V, Vin = 0.5 to VCCB - 0.5 V Vin = 0 V, VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 3.6 V Vin = 0 V, f = 1 MHz, Ta = 25C -IP 5 30 3 -- -- -- -- -- -- -- 30 20 1.0 -- 1.2 0.01 150 300 100 80 50 20 15 40 32 5.0 20.0 2.0 5.0 A Cin -- -- -- -- pF ICC -- -- -- -- mA mA A f = 10 MHz f = 10 MHz Ta 50C 50C < Ta Analog power supply current During A/D, D/A conversion Idle AlCC -- -- mA A AVCC = 2.0 V to 3.6 V Rev. 3.00 Mar 21, 2006 page 739 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Test Conditions Item Reference power supply current Symbol Min -- -- -- Typ 0.5 2.0 0.01 -- -- -- Max 1.0 5.0 5.0 3.6 3.6 -- Unit mA During A/D conversion Alref During A/D, D/A conversion Idle A V AVref = 2.0 V to AVCC Operating Idle/not used Analog power supply voltage* 1 AVCC VRAM 2.7 2.0 RAM standby voltage 2.0 V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. 2. Current dissipation values are for VIH min = VCC - 0.2 V, VCCB - 0.2 V, and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 3. The values are for VRAM VCC < 2.7 V, VIH min = VCC- 0.2 V, VCCB - 0.2 V, and VIL max = 0.2 V. 4. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. 5. For flash memory programming/erasure, the applicable range is VCC = 3.0 V to 3.6 V. Rev. 3.00 Mar 21, 2006 page 740 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.17 DC Characteristics (7) (3-V Version of H8S/2145BV) When LPC Function Is Used Conditions: VCC = 3.0 V to 3.6 V, VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 AVref* = 2.7 V to AVCC, VSS = AVSS* = 0 V, Ta = -20 to +75C Item Input high voltage Input low voltage Output high voltage Output low voltage Note: * P37 to P30, P83 to P80, PB1, PB0 P37 to P30, P83 to P80, PB1, PB0 P37, P33 to P30, P82 to P80, PB1, PB0 P37, P33 to P30, P82 to P80, PB1, PB0 Symbol VIH Min VCC x 0.5 Max -- Unit V Test Conditions VIL -- VCC x 0.3 V VOH VCC x 0.9 -- V IOH = -0.5 mA VOL -- VCC x 0.1 V IOL = 1.5 mA Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref AVCC. Rev. 3.00 Mar 21, 2006 page 741 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.18 Permissible Output Currents Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Item Permissible output low current (per pin) SCL1, SCL0, SDA1, SDA0, PS2AC to PS2CC, PS2AD to PS2CD, PA7 to PA4 (bus drive function selected) Ports 1 to 3 RESO Other output pins Permissible output low current (total) Total of ports 1 to 3 Total of all output pins, including the above All output pins Total of all output pins -IOH -IOH IOL Symbol IOL Min -- Typ -- Max 20 Unit mA -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 3 2 80 120 2 40 mA mA mA Permissible output high current (per pin) Permissible output high current (total) Rev. 3.00 Mar 21, 2006 page 742 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C Item Permissible output low current (per pin) SCL1, SCL0, SDA1, SDA0, PS2AC to PS2CC, PS2AD to PS2CD, PA7 to PA4 (bus drive function selected) Ports 1 to 3 RESO Other output pins Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Total of ports 1 to 3 Total of all output pins, including the above All output pins Total of all output pins -IOH -IOH IOL Symbol IOL Min -- Typ -- Max 10 Unit mA -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 1 1 40 60 2 30 mA mA mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 27.18. 2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as show in figures 27.1 and 27.2. Rev. 3.00 Mar 21, 2006 page 743 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.19 Bus Drive Characteristics Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3-V version product), VSS = 0 V Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol VT VT - + + - Min VCC x 0.3 -- VCC x 0.05 VCC x 0.7 -0.5 -- -- -- Typ -- -- -- -- -- -- -- -- -- -- Max -- VCC x 0.7 -- 5.5 VCC x 0.3 0.8 0.5 0.4 20 1.0 250 Unit V Test Conditions VT - VT Input high voltage Input low voltage Output low voltage VIH VIL VOL V V IOL = 16 mA, VCC = 4.5 V to 5.5 V IOL = 8 mA IOL = 3 mA Input capacitance Cin -- -- pF A ns Vin = 0 V, f = 1 MHz, Ta = 25C Vin = 0.5 to VCC - 0.5 V Three-state leakage | ITSI | current (off state) SCL, SDA output fall time tOf 20 + 0.1 Cb -- Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3-V version product), VCCB = 2.7 V to 5.5 V, VSS = 0 V Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive function selected) Item Output low voltage Symbol VOL Min -- -- -- Typ -- -- -- Max 0.8 0.5 0.4 Unit V Test Conditions IOL = 16 mA, VCCB = 4.5 V to 5.5 V IOL = 8 mA IOL = 3 mA Rev. 3.00 Mar 21, 2006 page 744 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.2.3 AC Characteristics The following shows the clock timing, control signal timing, bus timing, and on-chip peripheral function timing. For the AC characteristics test conditions, see figure 27.3. Clock Timing: Table 27.20 shows the clock timing. The clock timing specified here covers clock () output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 25, Clock Pulse Generator. Table 27.20 Clock Timing Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 10 MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Oscillation settling time at reset (crystal) Oscillation settling time in software standby (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 Min 100 30 30 -- -- 20 8 Max 500 -- -- 20 20 -- -- Condition B 16 MHz Min 62.5 20 20 -- -- 10 8 Max 500 -- -- 10 10 -- -- Condition C 20 MHz Min 50 17 17 -- -- 10 8 Max 500 -- -- 8 8 -- -- Test Unit Conditions ns ns ns ns ns ms ms Figure 27.7 Figure 27.8 Figure 27.6 Figure 27.6 tDEXT 500 -- 500 -- 500 -- s Rev. 3.00 Mar 21, 2006 page 745 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Control Signal Timing: Table 27.21 shows the control signal timing. The only external interrupts that can operate on the subclock ( = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 27.21 Control Signal Timing Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 10 MHz Item RES setup time RES pulse width NMI setup time (NMI) NMI hold time (NMI) NMI pulse width (NMI) (exiting software standby mode) IRQ setup time (IRQ7 to IRQ0) IRQ hold time (IRQ7 to IRQ0) Symbol tRESS tRESW tNMIS tNMIH tNMIW Min 300 20 250 10 200 Max -- -- -- -- -- Condition B 16 MHz Min 200 20 150 10 200 Max -- -- -- -- -- Condition C 20 MHz Min 200 20 150 10 200 Max -- -- -- -- -- Test Unit Conditions ns tcyc ns ns ns Figure 27.10 Figure 27.9 tIRQS tIRQH 250 10 200 -- -- -- 150 10 200 -- -- -- 150 10 200 -- -- -- ns ns ns IRQ pulse width tIRQW (IRQ7, IRQ6, IRQ2 to IRQ0) (exiting software standby mode) Rev. 3.00 Mar 21, 2006 page 746 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Bus Timing: Table 27.22 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock ( = 32.768 kHz). Table 27.22 Bus Timing (1) (Normal Mode) Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 10 MHz Item Address delay time Address setup time Address hold time CS delay time (IOS) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Symbol tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 Min -- Max 40 Min -- Condition B 16 MHz Max 30 Min -- Condition C 20 MHz Max 20 Test Unit Conditions ns ns ns ns ns ns ns ns ns Figures 27.11 to 27.15 -- 0.5 x tcyc - 30 -- 0.5 x tcyc - 20 -- -- -- -- 35 0 -- -- 40 60 60 60 -- -- 1.0 x tcyc - 60 1.5 x tcyc - 50 0.5 x -- tcyc - 20 0.5 x -- tcyc - 15 -- -- -- -- 20 0 -- -- 30 45 45 45 -- -- 1.0 x tcyc - 40 1.5 x tcyc - 35 0.5 x -- tcyc - 15 0.5 x -- tcyc - 10 -- -- -- -- 15 0 -- -- 20 30 30 30 -- -- 1.0 x ns tcyc - 30 1.5 x ns tcyc - 25 Rev. 3.00 Mar 21, 2006 page 747 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Condition A 10 MHz Item Read data access time 3 Read data access time 4 Read data access time 5 HWR, LWR delay time 1 HWR, LWR delay time 2 HWR, LWR pulse width 1 HWR, LWR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time Symbol tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH Min -- -- -- -- -- Max 2.0 x tcyc - 60 2.5 x tcyc - 50 3.0 x tcyc - 60 60 60 Min -- -- -- -- -- Condition B 16 MHz Max 2.0 x tcyc - 40 2.5 x tcyc - 35 3.0 x tcyc - 40 45 45 Min -- -- -- -- -- Condition C 20 MHz Max Test Unit Conditions Figures 27.11 to 27.15 2.0 x ns tcyc - 30 2.5 x ns tcyc - 25 3.0 x ns tcyc - 30 30 30 ns ns ns ns ns ns ns ns ns 1.0 x -- tcyc - 40 1.5 x -- tcyc - 40 -- 0 20 60 10 60 -- -- -- -- 1.0 x -- tcyc - 30 1.5 x -- tcyc - 30 -- 0 15 45 5 45 -- -- -- -- 1.0 x -- tcyc - 20 1.5 x -- tcyc - 20 -- 0 10 30 5 30 -- -- -- -- Rev. 3.00 Mar 21, 2006 page 748 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.22 Bus Timing (2) (Advanced Mode) Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 10 MHz Item Address delay time Address setup time Address hold time CS delay time (IOS) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Symbol tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 Min -- Max 60 Min -- Condition B 16 MHz Max 45 Min -- Condition C 20 MHz Max 30 Test Unit Conditions ns ns ns ns ns ns ns ns ns Figures 27.11 to 27.15 -- 0.5 x tcyc - 50 -- 0.5 x tcyc - 20 -- -- -- -- 35 0 -- -- -- 60 60 60 60 -- -- 1.0 x tcyc - 80 1.5 x tcyc - 50 2.0 x tcyc - 80 0.5 x -- tcyc - 35 0.5 x -- tcyc - 15 -- -- -- -- 20 0 -- -- -- 45 45 45 45 -- -- 1.0 x tcyc - 55 2.5 x tcyc - 35 3.0 x tcyc - 55 0.5 x -- tcyc - 25 0.5 x -- tcyc - 10 -- -- -- -- 15 0 -- -- -- 30 30 30 30 -- -- 1.0 x ns tcyc - 40 2.5 x ns tcyc - 25 3.0 x ns tcyc - 40 Rev. 3.00 Mar 21, 2006 page 749 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Condition A 10 MHz Item Read data access time 4 Read data access time 5 HWR, LWR delay time 1 HWR, LWR delay time 2 HWR, LWR pulse width 1 HWR, LWR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time Symbol tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH Min -- -- -- -- Max 2.5 x tcyc - 50 3.0 x tcyc - 80 60 60 Min -- -- -- -- Condition B 16 MHz Max 2.5 x tcyc - 35 3.0 x tcyc - 55 45 45 Min -- -- -- -- Condition C 20 MHz Max Test Unit Conditions Figures 27.11 to 27.15 2.5 x ns tcyc - 25 3.0 x ns tcyc - 40 30 30 ns ns ns ns ns ns ns ns ns -- 1.0 x tcyc - 40 1.5 x -- tcyc - 40 -- 0 20 60 10 60 -- -- -- -- 1.0 x -- tcyc - 30 1.5 x -- tcyc - 30 -- 0 15 45 5 45 -- -- -- -- 1.0 x -- tcyc - 20 1.5 x -- tcyc - 20 -- 0 10 30 5 30 -- -- -- -- Rev. 3.00 Mar 21, 2006 page 750 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Timing of On-Chip Peripheral Modules: Tables 27.23 to 27.26 show the on-chip peripheral module timing. The only on-chip peripheral modules that can operate in subclock operation ( = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 27.23 Timing of On-Chip Peripheral Modules (1) Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 32.768 kHz*, 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 32.768 kHz*, 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 32.768 kHz*, 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 10 MHz Item I/O ports Output data delay time Input data setup time Input data hold time FRT Timer output delay time Timer input setup time Timer clock input setup time Symbol Min tPWD tPRS tPRH tFTOD tFTIS tFTCS -- 50 50 -- 50 50 1.5 2.5 -- 50 50 Max 100 -- -- 100 -- -- -- -- 100 -- -- Condition B 16 MHz Min -- 30 30 -- 30 30 1.5 2.5 -- 30 30 Max 50 -- -- 50 -- -- -- -- 50 -- -- Condition C 20 MHz Min -- 30 30 -- 30 30 1.5 2.5 -- 30 30 Max 50 -- -- 50 -- -- -- -- 50 -- -- ns Figure 27.19 Figure 27.21 Figure 27.20 tcyc Figure 27.18 ns Figure 27.17 Test Unit Conditions ns Figure 27.16 Timer clock Single edge tFTCWH pulse width Both edges tFTCWL TMR Timer output delay time Timer reset input setup time Timer clock input setup time tTMOD tTMRS tTMCS Rev. 3.00 Mar 21, 2006 page 751 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Condition A 10 MHz Item TMR Timer clock pulse width Single edge Both edges Symbol Min tTMCWH tTMCWL 1.5 2.5 Max -- -- Condition B 16 MHz Min 1.5 2.5 Max -- -- Condition C 20 MHz Min 1.5 2.5 Max -- -- Test Unit Conditions tcyc Figure 27.20 PWM, PWMX SCI Pulse output delay time Input clock cycle Asynchronous Synchronous tPWOD tScyc -- 4 6 100 -- -- 0.6 1.5 1.5 100 -- -- -- 200 -- -- 4 6 0.4 -- -- -- 50 50 30 -- 132 50 -- -- 0.6 1.5 1.5 50 -- -- -- 120 -- -- 4 6 0.4 -- -- -- 50 50 30 -- 132 50 -- -- 0.6 1.5 1.5 50 -- -- -- 100 -- ns tcyc Figure 27.22 Figure 27.23 Input clock pulse width Input clock rise time Input clock fall time tSCKW tSCKr tSCKf 0.4 -- -- -- 100 100 50 -- 132 tScyc tcyc Transmit data delay time tTXD (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) A/D Trigger input setup time converter WDT RESO output delay time tRXS tRXH tTRGS tRESD ns Figure 27.24 ns ns tcyc Figure 27.25 Figure 27.26 RESO output pulse width tRESOW Note: * Only peripheral modules that can be used in subclock operation Rev. 3.00 Mar 21, 2006 page 752 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.23 Timing of On-Chip Peripheral Modules (2) Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 10 MHz Item HIF read cycle CS/HA0 setup time CS/HA0 hold time IOR pulse width HDB delay time HDB hold time HIRQ delay time HIF write cycle CS/HA0 setup time CS/HA0 hold time IOW pulse width HDB setup time Fast A20 gate not used Fast A20 gate used HDB hold time GA20 delay time tHWD tHGA Symbol tHAR tHRA tHRPW tHRD tHRF tHIRQ tHAW tHWA tHWPW tHDW Min 10 10 220 -- 0 -- 10 10 100 50 Max -- -- -- 200 40 200 -- -- -- -- Condition B 16 MHz Min 10 10 120 -- 0 -- 10 10 60 30 Max -- -- -- 100 25 120 -- -- -- -- Condition C 20 MHz Min 10 10 120 -- 0 -- 10 10 60 30 Test Max Unit Conditions ns Figure 27.27 -- -- -- 100 25 120 -- -- -- -- 85 25 -- -- -- 180 55 15 -- -- -- 90 45 15 -- -- -- 90 Rev. 3.00 Mar 21, 2006 page 753 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.24 Keyboard Buffer Controller Timing Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3-V product), VCCB = 2.7 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Ratings Item KCLK, KD output fall time KCLK, KD input data hold time KCLK, KD input data setup time KCLK, KD output delay time KCLK, KD capacitive load 2 Symbol tKBF tKBIH tKBIS tKBOD Cb Min Typ Max 250 -- -- 450 400 Test Unit Conditions Notes ns ns ns ns pF Figure 27.28 20 + 0.1 Cb -- 150 150 -- -- -- -- -- -- Table 27.25 I C Bus Timing Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3-V product), VSS = 0 V, = 5 MHz to maximum operating frequency, Ratings Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Note: * Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min 12 3 5 -- -- -- 5 3 3 3 0.5 0 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 7.5* 300 1 -- -- -- -- -- -- 400 Unit tcyc tcyc tcyc tcyc ns tcyc tcyc tcyc tcyc tcyc tcyc ns pF 2 Test Conditions Notes Figure 27.29 17.5tcyc can be set according to the clock selected for use by the I C module. For details, see section 16.6, Usage Notes. Rev. 3.00 Mar 21, 2006 page 754 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.26 LPC Module Timing (For H8S/2145B Only) Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Item LPC Input clock cycle Input clock pulse width (H) Input clock pulse width (L) Transmit signal delay time Symbol tLcyc tLCKH tLCKL tTXD Min 30 11 11 2 -- 7 0 Typ -- -- -- -- -- -- -- Max -- -- -- 11 28 -- -- Unit ns Test Conditions Figure 27.30 Transmit signal floating delay tOFF time Receive signal setup time Receive signal hold time tRXS tRXH Rev. 3.00 Mar 21, 2006 page 755 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.2.4 A/D Conversion Characteristics Tables 27.27 and 27.28 list the A/D conversion characteristics. Table 27.27 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition C: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition C 10 MHz Item Resolution 3 Conversion time* Condition B 16 MHz Condition A 20 MHz Min 10 -- -- -- Typ 10 -- -- -- Max 10 13.4 20 5 Min 10 -- -- -- Typ 10 -- -- -- Max 10 8.4 20 10* 5* 2 1 Min 10 -- -- -- Typ 10 -- -- -- Max 10 6.7 20 10* 5* 2 1 Unit bits s pF k Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy -- -- -- -- -- -- -- -- -- -- 7.0 7.5 7.5 0.5 8.0 -- -- -- -- -- -- -- -- -- -- 3.0 3.5 3.5 0.5 4.0 -- -- -- -- -- -- -- -- -- -- 3.0 3.5 3.5 0.5 4.0 LSB LSB LSB LSB LSB Notes: 1. When conversion time 11.17 s (CKS = 0, or 12 MHz at CKS = 1) 2. When conversion time < 11.17 s ( > 12 MHz at CKS = 1) 3. At the maximum operating frequency in single mode. Rev. 3.00 Mar 21, 2006 page 756 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Table 27.28 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) 4 4 4 Condition C: VCC = 3.0 V to 3.6 V* , AVCC = 3.0 V to 3.6 V* , AVref = 3.0 V to AVCC* , 4 VCCB = 3.0 V to 5.5 V* , VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition C 10 MHz Item Resolution Conversion time* Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Notes: 1. 2. 3. 4. 3 Condition B 16 MHz Condition A 20 MHz Min 10 -- -- -- Typ 10 -- -- -- Max 10 13.4 20 5 Min 10 -- -- -- Typ 10 -- -- -- Max 10 8.4 20 10* 2 5* 1 Min 10 -- -- -- Typ 10 -- -- -- Max 10 6.7 20 10* 2 5* 1 Unit bits s pF k -- -- -- -- -- -- -- -- -- -- 11.0 11.5 11.5 0.5 12.0 -- -- -- -- -- -- -- -- -- -- 5.0 5.5 5.5 0.5 6.0 -- -- -- -- -- -- -- -- -- -- 5.0 5.5 5.5 0.5 6.0 LSB LSB LSB LSB LSB When conversion time 11.17 s (CKS = 0, or 12 MHz at CKS = 1) When conversion time < 11.17 s ( > 12 MHz at CKS = 1) At the maximum operating frequency in single mode. When using CIN, ensure that VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V. Rev. 3.00 Mar 21, 2006 page 757 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.2.5 D/A Conversion Characteristics Table 27.29 lists the D/A conversion characteristics. Table 27.29 D/A Conversion Characteristics Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) Condition C: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition C 10 MHz Item Resolution Conversion With 20 pF load time capacitance Absolute accuracy With 2 M load resistance With 4 M load resistance Min 8 -- -- -- Typ 8 -- Max 8 10 Min 8 -- -- -- Condition B 16 MHz Typ 8 -- Max 8 10 Min 8 -- -- -- Condition A 20 MHz Typ 8 -- Max 8 10 Unit bits s LSB 2.0 3.0 -- 2.0 1.0 1.5 -- 1.0 1.0 1.5 -- 1.0 Rev. 3.00 Mar 21, 2006 page 758 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.2.6 Flash Memory Characteristics Table 27.30 shows the flash memory characteristics. Table 27.30 Flash Memory Characteristics (Operation Range at Programming/Erasing) 5-V version conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C (normal specification product), Ta = -40 to +85C (wide range temperature specification product) 3-V version conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = -20 to +75C Item Programming time*1 *2 *4 Erase time*1 *3 *6 Reprogramming count Symbol tP tE NWEC Min -- -- -- 1 50 28 198 8 5 5 4 2 2 100 -- 1 100 10 10 10 20 2 4 100 -- Typ 10 100 -- -- -- 30 200 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 200 1200 100 -- -- 32 202 12 -- -- -- -- -- -- 1000 -- -- 100 -- -- -- -- -- -- 120 Unit ms/ 128 bytes ms/block times s s s s s s s s s s s times s s ms s s s s s s times 1n6 7 n 1000 Additional write Test Condition Programming Wait time after SWE-bit setting*1 x Wait time after PSU-bit setting*1 y Wait time after P-bit setting*1 *4 z1 z2 z3 Wait time after P-bit clear*1 Wait time after PSU-bit clear*1 Wait time after PV-bit setting*1 Wait time after dummy write*1 Wait time after PV-bit clear*1 Wait time after SWE-bit clear*1 Maximum programming count*1 *4 *5 Erase N Wait time after SWE-bit setting*1 x Wait time after ESU-bit setting*1 y Wait time after E-bit setting*1 *6 z Wait time after E-bit clear*1 Wait time after ESU-bit clear*1 Wait time after EV-bit setting*1 Wait time after dummy write*1 Wait time after EV-bit clear*1 Wait time after SWE-bit clear*1 Maximum erase count*1 *6 *7 N Rev. 3.00 Mar 21, 2006 page 759 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = (wait time after P-bit setting (z1) + (z3)) x 6 + wait time after P-bit setting (z2) x ((N) - 6) 5. The maximun number of writes (N) should be set according to the actual set value of z1, z2 and z3 to allow programming within the maximum programming time (tP (max)). The wait time after P-bit setting (z1, z2, and z3) should be alternated according to the number of writes (n) as follows: 1n6 z1 = 30 s, z3 = 10 s 7 n 1000 z2 = 200 s 6. Maximum erase time (tE (max)) tE (max) = Wait time after E-bit setting (z) x maximum erase count (N) 7. The maximum number of erases (N) should be set according to the actual set value of z to allow erasing within the maximum erase time (tE (max)). 27.2.7 Usage Notes 1. Internal step-down products The H8S/2148 B-masked product (HD64F2148B) includes an internal step-down circuit to step down the microprocessor internal power supply voltage to the appropriate level. One or two (in parallel) internal voltage regulating capacitors (0.47 F) should be inserted between the internal step-down pin (VCL pin) and VSS pin. The method of connecting the external capacitor(s) is shown in figure 27.5. For the 5-V and 4-V version products whose power supply (VCC) voltage exceeds 3.6 V, do not connect the VCC power supply to the VCL pin of the internal step-down product. (Connect the VCC power supply to the VCC1 pin, as usual.) For the 3-V version product whose power supply (VCC) voltage is 3.6 V or less, connect the system power supply to the VCL pin together with the VCC1 pins. When switching from the F-ZTAT version product without the internal step-down function to the F-ZTAT B-masked product with the internal step-down function, note that the VCL pin is allocated to the same location as the VCC2 pin of the product without the internal step-down function. Therefore, the difference in the circuits between before and after the switchover should be considered when designing the PC board patterns. Rev. 3.00 Mar 21, 2006 page 760 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Vcc power supply External capacitor for power supply regulation VCL Bypass capacitor Product with internal step-down function 10 F 0.01 F VCL 0.47 F (one, or two in parallel) Product without internal step-down function VSS VSS The VCC power supply should not be connected to the VCL pin of the product with the internal step-down function. (Connect the VCC power supply to other VCC1 pins as usual.) Be sure to connect power supply regulating capacitor(s) to the VCL pin. One or two (parallel) 0.47-F multilayer capacitors should be used near the VCL pin. For 3-V products used with the voltage of 3.6 V or less, connect the Vcc power supply in the same way as the products without the internal step-down function. < Product with internal step-down function > HD64F2145B HD64F2148B The VCC2 pin of the product without the internal step-down function is allocated at the same location as the VCL pin of the product with the internal step-down function. It is recommended that a bypass capacitor be connected to the power supply pins. (The values are reference values.) < Product without internal step-down function > HD64F2145BV HD64F2148BV Figure 27.5 Connection of VCL Capacitor Rev. 3.00 Mar 21, 2006 page 761 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.3 27.3.1 Timing Chart Clock Timing The clock timings are shown below. tcyc tCH tCL tCr tCf Figure 27.6 System Clock Timing EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 Figure 27.7 Oscillation Settling Timing Rev. 3.00 Mar 21, 2006 page 762 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics NMI IRQi tOSC2 Note: i = 0 to 2, 6, 7 Figure 27.8 Oscillation Setting Timing (Exiting Software Standby Mode) Rev. 3.00 Mar 21, 2006 page 763 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.3.2 Control Signal Timing The control signal timings are shown below. tRESS RES tRESW tRESS Figure 27.9 Reset Input Timing tNMIS NMI tNMIW tNMIH IRQi tIRQW tIRQS IRQi Edge input tIRQS IRQi Level input tIRQH Note: i = 7 to 0 Figure 27.10 Interrupt Input Timing Rev. 3.00 Mar 21, 2006 page 764 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.3.3 Bus Timing The bus timings are shown below. T1 tAD A23 to A0, IOS* tCSD AS* tAS tAH tASD tASD T2 tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D15 to D0 (read) tRDS tRDH tWRD2 HWR, LWR (write) tAS tWDD D15 to D0 (write) tWSW1 tWRD2 tAH tWDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.11 Basic Bus Timing (Two-State Access) Rev. 3.00 Mar 21, 2006 page 765 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics T1 T2 T3 tAD A23 to A0, IOS* tCSD AS* tAS tASD tASD tAH tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.12 Basic Bus Timing (Three-State Access) Rev. 3.00 Mar 21, 2006 page 766 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics T1 T2 TW T3 A23 to A0, IOS* AS* RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.13 Basic Bus Timing (Three-State Access with One Wait State) Rev. 3.00 Mar 21, 2006 page 767 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics T1 T2 or T3 T1 T2 tAD A23 to A0, IOS* tAS AS* tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH tASD tASD tAH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.14 Burst ROM Access Timing (Two-State Access) Rev. 3.00 Mar 21, 2006 page 768 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics T1 T2 or T3 T1 tAD A23 to A0, IOS* AS* tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.15 Burst ROM Access Timing (One-State Access) Rev. 3.00 Mar 21, 2006 page 769 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 27.3.4 On-Chip Peripheral Module Timing The on-chip peripheral module timings are shown below. T1 T2 Ports 1 to 9, A, and B (Ports C to G are added in H8S/2160B and H8S/2161B) (read) Ports 1 to 6, 8, 9, A, and B (Ports C to F are added in H8S/2160B and H8S/2161B) (write) tPRS tPRH tPWD Figure 27.16 I/O Port Input/Output Timing tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 27.17 FRT Input/Output Timing Rev. 3.00 Mar 21, 2006 page 770 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics tFTCS FTCI tFTCWL tFTCWH Figure 27.18 FRT Clock Input Timing tTMOD TMO0, TMO1 TMOX Figure 27.19 8-Bit Timer Output Timing tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH tTMCS Figure 27.20 8-Bit Timer Clock Input Timing tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 27.21 8-Bit Timer Reset Input Timing Rev. 3.00 Mar 21, 2006 page 771 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics tPWOD PW15 to PW0, PWX1, PWX0 Figure 27.22 PWM, PWMX Output Timing tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf Figure 27.23 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS RxD0 to RxD2 (receive data) tRXH Figure 27.24 SCI Input/Output Timing (Synchronous Mode) tTRGS ADTRG Figure 27.25 A/D Converter External Trigger Input Timing Rev. 3.00 Mar 21, 2006 page 772 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics tRESD RESO tRESOW tRESD Figure 27.26 WDT Output Timing (RESO RESO) RESO Host interface (XBS) read timing CS/HA0 tHAR IOR tHRD HDB7 to HDB0 Valid data tHRF tHRPW tHRA tHIRQ HIRQi* Notes: i = 1, 11, 12, 3, 4 * The rising edge timing is the same as the port 4 and port B output timing. See figure 28.16. Host interface (XBS) write timing CS/HA0 tHAW IOW tHDW HDB7 to HDB0 tHWD tHWPW tHWA tHGA GA20 Figure 27.27 Host Interface (XBS) Timing Rev. 3.00 Mar 21, 2006 page 773 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics 1. Reception tKBIS KCLK/ KD 2. Transmission (a) T1 tKBOD KCLK/ KD T2 tKBIH Transmission (b) KCLK/ KD tKBF Legend: KCLK: PS2AC to PS2CC KD: PS2AD to PS2CD Note: shown here is the clock scaled by 1/N when the operating mode is active medium-speed mode. Figure 27.28 Keyboard Buffer Controller Timing Rev. 3.00 Mar 21, 2006 page 774 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics SDA0, SDA1 tBUF VIH VIL tSTAH tSCLH tSP tSTOS tSTAS SCL0, SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS P* Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 27.29 I C Bus Interface Input/Output Timing tLCKH 2 tLcyc LCLK tLCKL LCLK tTXD LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) tRXS LAD3 to LAD0, SERIRQ, CLKRUN LFRAME (Receive signal) tOFF LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) tRXH Figure 27.30 Host Interface (LPC) Timing Rev. 3.00 Mar 21, 2006 page 775 of 788 REJ09B0300-0300 Section 27 Electrical Characteristics Testing voltage: 0.4Vcc 50pF Figure 27.31 Tester Measurement Condition Rev. 3.00 Mar 21, 2006 page 776 of 788 REJ09B0300-0300 Appendix A I/O Port States in Each Processing State Appendix A I/O Port States in Each Processing State Table A.1 Port Name Pin Name Port 1 A7 to A0 I/O Port States in Each Processing State MCU Operating Mode Reset 1 2, 3 (EXPE = 1) L T Hardware Software Standby Standby Mode Mode T kept* Watch Mode kept* Sleep Mode kept* Subsleep Mode kept* Subactive Mode A7 to A0 Address output/ input port I/O port L T T kept* kept* kept* kept* A15 to A8 Address output/ input port I/O port T T T T T T D15 to D8 Program Execution State A7 to A0 Address output/ input port I/O port A15 to A8 Address output/ input port I/O port D15 to D8 2, 3 (EXPE = 0) Port 2 A15 to A8 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 3 D15 to D8 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 4 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 5 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 6 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 7 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 8 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 97 WAIT 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) kept kept kept kept T T T/kept T/kept T/kept T/kept T T kept kept kept kept T T T T T T T T kept kept kept kept T T kept kept kept kept T T kept kept kept kept kept kept kept kept I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Input port Input port I/O port I/O port WAIT/ I/O port I/O port WAIT/ I/O port I/O port Rev. 3.00 Mar 21, 2006 page 777 of 788 REJ09B0300-0300 Appendix A I/O Port States in Each Processing State Hardware Software Standby Standby Mode Mode T Subsleep Mode EXCL input Program Execution State Clock output/ EXCL input/ input port Port Name Pin Name Port 96 EXCL MCU Operating Mode Reset 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Clock output T Watch Mode Sleep Mode [DDR = 1] clock output [DDR = 0] T Subactive Mode EXCL input [DDR = 1] H EXCL input [DDR = 0] T Ports 95 to 93 1 AS, HWR, RD 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Ports 92, 91 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 90 LWR 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port A A23 to A16 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port B D7 to D0 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Ports C to G (H8S/2160B, H8S/2161B) 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) H T T H H H H AS, HWR, RD I/O port I/O port AS, HWR, RD I/O port I/O port kept T T kept kept kept kept kept kept kept T T H/kept H/kept H/kept H/kept LWR/ I/O port I/O port I/O port A23 to A16/ I/O port I/O port LWR/ I/O port I/O port I/O port A23 to A16/ I/O port I/O port D7 to D0/ I/O port I/O port I/O port kept T T kept* kept kept* kept kept* kept kept* T T T/kept T/kept T/kept T/kept D7 to D0/ I/O port I/O port I/O port kept T T kept kept kept kept kept kept kept Legend: H: High L: Low T: High-impedance state kept: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, input pull-up MOSs remain on). Output ports maintain their previous state. Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port function determined by DDR and DR used. DDR: Data direction register Note: * In the case of address output, the last address accessed is retained. Rev. 3.00 Mar 21, 2006 page 778 of 788 REJ09B0300-0300 Appendix B Product Codes Appendix B Product Codes Product Type H8S/2161B H8S/2160B H8S/2141B H8S/2140B H8S/2145B Flash memory version (3-V version) Flash memory version (3-V version) Flash memory version (3-V version) Flash memory version (3-V version) Flash memory version (3-V version) Flash memory version (5-V version) H8S/2148B Flash memory version (3-V version) Flash memory version (5-V version) Product Code HD64F2161BV HD64F2160BV HD64F2141BV HD64F2140BV HD64F2145BV HD64F2145B HD64F2148BV HD64F2148B Mark Code F2161BVTE10 F2160BVTE10 F2141BVFA10 F2141BVTE10 F2140BVFA10 F2140BVTE10 F2145BVFA10 F2145BVTE10 F2145BFA20 F2145BTE20 F2148BVFA10 F2148BVTE10 F2148BFA20 F2148BTE20 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) Package (Package Code) 144-pin TQFP (TFP-144) Legend: (***): ROM code Note: * Some products above are in the developing or planning stage. Please contact Renesas agency to conform the present state of each product. Rev. 3.00 Mar 21, 2006 page 779 of 788 REJ09B0300-0300 Appendix C Package Dimensions Appendix C Package Dimensions JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g HD *1 D 75 51 76 50 bp b1 c1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. *2 HE E c Terminal cross section ZE Reference Dimension in Millimeters Symbol 100 26 1 ZD 25 F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 2.70 15.7 16.0 16.3 15.7 16.0 16.3 3.05 0.00 0.12 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.08 0.10 1.0 1.0 0.3 0.5 0.7 1.0 Min A A2 Figure C.1 Package Dimensions (FP-100B) Rev. 3.00 Mar 21, 2006 page 780 of 788 REJ09B0300-0300 c Appendix C Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 51 75 76 50 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 c1 *2 HE E c Terminal cross section ZE Reference Dimension in Millimeters Symbol 100 26 A2 1 ZD Index mark 25 A F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.08 0.10 1.00 1.00 0.4 0.5 0.6 1.0 Min Figure C.2 Package Dimensions (TFP-100B) Rev. 3.00 Mar 21, 2006 page 781 of 788 REJ09B0300-0300 c Appendix C Package Dimensions JEITA Package Code P-TQFP144-16x16-0.40 RENESAS Code PTQP0144LC-A Previous Code TFP-144/TFP-144V MASS[Typ.] 0.6g HD *1 D 108 109 73 72 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E b1 *2 c1 c 144 1 ZD Index mark 36 37 Reference Dimension in Millimeters Symbol ZE Terminal cross section F A A2 e *3 y bp x M A1 L L1 Detail F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Min Nom Max 16 16 1.00 17.8 18.0 18.2 17.8 18.0 18.2 1.20 0.05 0.10 0.15 0.13 0.18 0.23 0.16 0.12 0.17 0.22 0.15 0 8 0.4 0.07 0.08 1.0 1.0 0.4 0.5 0.6 1.0 Figure C.3 Package Dimensions (TFP-144) Rev. 3.00 Mar 21, 2006 page 782 of 788 REJ09B0300-0300 c Index Index 14-Bit PWM Timer (PWMX) ................. 243 16-Bit Count Mode ................................. 305 16-Bit Free-Running Timer (FRT) ......... 259 2fH Modification .................................... 334 8-Bit PWM Timer (PWM)...................... 231 8-Bit Timer (TMR) ................................. 287 A/D Converter ........................................ 585 A20 Gate......................................... 521, 565 ABRKCR.................. 93, 663, 673, 682, 692 Absolute Address...................................... 53 Activation by Software ........................... 163 ADCR ..................... 590, 668, 678, 687, 698 ADCSR ................... 589, 668, 678, 686, 698 ADDR ..................... 588, 668, 677, 686, 698 Address Map............................................. 71 Address Space........................................... 32 Addressing Modes .................................... 51 ADI ......................................................... 596 Analog Input Channel............................. 588 Arithmetic Operations Instructions........... 43 Asynchronous Mode............................... 376 BAR .......................... 94, 664, 673, 682, 692 Bcc ............................................................ 48 BCR ........................ 124, 667, 676, 685, 696 Bit Manipulation Instructions ................... 46 bit rate ..................................................... 369 Block Configuration ............................... 608 Block Data Transfer Instructions .............. 50 Block Transfer Mode .............................. 158 Boot Mode .............................................. 618 Branch Instructions................................... 48 Break....................................................... 406 BRR ........................ 369, 668, 677, 686, 697 Buffered Input Capture Input.................. 274 Burst ROM Interface...............................141 Bus Arbitration........................................144 Bus Controller (BSC)..............................121 Cascaded Connection ..............................305 CBLANK Output ....................................343 Chain Transfer ........................................159 Clamp Waveform Generation .................330 Clear Timing ...........................................273 Clock Pulse Generator ............................633 Clocked Synchronous Mode ...................393 CMI .........................................................309 CMIA ......................................................309 CMIAY ...................................................309 CMIB ......................................................309 CMIBY ...................................................309 Compare-Match Count Mode .................306 Condition field ..........................................50 Condition-Code Register (CCR) ...............35 Conversion Time.....................................594 CRA ........................................................150 CRB.........................................................150 Crystal Resonator....................................634 D/A Converter.........................................579 DACNT................... 245, 666, 675, 684, 695 DACR ............ 248, 581, 665, 669, 675, 678, 684, 687, 694, 700 DADR0 ................... 580, 669, 678, 687, 700 DADR1 ................... 580, 669, 678, 687, 700 DAR ........................................................149 Data Transfer Controller (DTC)..............145 Data Transfer Instructions.........................42 DDCSWI.................................................475 DDCSWR ............... 436, 663, 673, 682, 691 Direct Transitions....................................656 DTC Vector Table...................................153 DTCER ................... 150, 663, 673, 682, 692 Rev. 3.00 Mar 21, 2006 page 783 of 788 REJ09B0300-0300 Index DTVECR ................ 151, 663, 673, 682, 692 EBR1 ...................... 614, 664, 674, 683, 692 EBR2 ...................... 614, 664, 674, 683, 692 EEPMOV Instruction................................ 61 Effective Address ..................................... 55 Effective address extension ...................... 50 Erase/Erase-Verify.................................. 626 erasing units............................................ 608 ERI.......................................................... 405 ERRI ....................................................... 575 Error Protection ...................................... 628 Exception Handling .................................. 81 Exception Vector Table ............................ 82 Extended Control Register (EXR) ............ 35 External Trigger...................................... 595 flash memory .......................................... 603 FLMCR1................. 611, 664, 674, 682, 692 FLMCR2................. 613, 664, 674, 682, 692 Formatless............................................... 442 FOV ........................................................ 279 framing error........................................... 383 FRC......................... 262, 664, 674, 683, 693 General Registers...................................... 34 Hardware Protection ............................... 628 Hardware Standby Mode ........................ 652 HICR....................... 514, 669, 678, 687, 698 HICR0..................... 533, 661, 672, 681, 690 HICR1..................... 533, 661, 672, 681, 690 HICR2..................... 540, 661, 672, 681, 690 HICR3..................... 540, 661, 672, 681, 690 HIRQ ...................................................... 526 HISEL..................... 561, 661, 672, 681, 690 Host Interface LPC Interface (LPC) ....... 529 Host Interface X-Bus Interface (XBS).... 509 HSYNCO Output.................................... 341 I C Bus Data Format ............................... 442 2 I C Bus Interface (IIC) ............................ 413 IBF .......................................................... 525 ICCR ....................... 424, 668, 677, 686, 697 ICDR....................... 417, 668, 677, 686, 697 ICI ........................................................... 279 ICIX ........................................................ 309 ICMR ...................... 421, 668, 677, 686, 697 ICR........... 92, 262, 663, 665, 673, 675, 682, 683, 691, 693 ICSR........................ 431, 668, 677, 686, 697 ICXR....................... 438, 662, 673, 682, 691 Idle Cycle................................................ 142 IDR.......................... 517, 661, 672, 680, 690 IER ............................ 96, 667, 676, 685, 696 IHI signal divided waveform .................. 332 IICI.......................................................... 475 Immediate ................................................. 53 Increment Timing.................................... 272 Input Capture Input ................................. 274 Instruction Set ........................................... 40 Interrupt Control Modes.......................... 105 Interrupt Controller ................................... 89 Interrupt Exception Handling.................... 85 Interrupt Exception Handling Vector Table ............................................................ 102 Interrupt Mask Bit..................................... 36 Interval Timer Mode ............................... 354 IrDA Operation ....................................... 402 ISCR.......................... 95, 663, 673, 682, 691 ISR ............................ 96, 663, 673, 682, 691 KBBR...................... 495, 662, 673, 682, 691 KBCOMP................ 591, 663, 673, 682, 691 KBCR...................... 492, 662, 673, 682, 691 Keyboard Buffer Controller .................... 489 KMIMR .................... 97, 669, 678, 687, 698 KMIMRA.................. 97, 669, 678, 687, 699 KMPCR .................. 190, 669, 678, 687, 699 2 Rev. 3.00 Mar 21, 2006 page 784 of 788 REJ09B0300-0300 Index LADR3 ................... 543, 661, 671, 680, 690 Logic Operations Instructions................... 45 LPWRCR................ 644, 664, 674, 683, 692 Mark State............................................... 406 MCU Operating Mode Selection .............. 63 MDCR....................... 64, 667, 676, 685, 696 Medium-Speed Mode ............................. 649 Memory Indirect ....................................... 54 Module Stop Mode ................................. 656 MRA ....................................................... 147 MRB ....................................................... 149 MSTPCR................. 645, 664, 674, 683, 692 Multiprocessor Communication Function ............................................................ 387 NMI interrupt.......................................... 100 Noise Canceler........................................ 472 Normal Mode.................................. 156, 164 OCI ......................................................... 279 OCR ........................ 262, 665, 675, 683, 693 OCRDM.................................................. 263 ODR........................ 517, 545, 661, 680, 690 ODR1...................................................... 672 On-Board Programming Modes.............. 617 Operation field .......................................... 50 Output Compare Output.......................... 273 overrun error ........................................... 383 OVI ......................................................... 309 OVIY ...................................................... 309 P1DDR.................... 172, 666, 676, 685, 695 P1DR ...................... 173, 666, 676, 685, 695 P1PCR .................... 173, 666, 676, 684, 695 P2DDR.................... 175, 666, 676, 685, 695 P2DR ...................... 176, 666, 676, 685, 695 P2PCR .................... 176, 666, 676, 684, 695 P3DDR.................... 179, 666, 676, 685, 695 P3DR ...................... 180, 666, 676, 685, 696 P3PCR..................... 180, 666, 676, 685, 695 P4DDR.................... 182, 666, 676, 685, 695 P4DR....................... 183, 666, 676, 685, 696 P5DDR.................... 186, 666, 676, 685, 696 P5DR....................... 187, 666, 676, 685, 696 P6DDR.................... 189, 666, 676, 685, 696 P6DR....................... 189, 667, 676, 685, 696 P7PIN...................... 194, 667, 676, 685, 696 P8DDR.................... 195, 667, 676, 685, 696 P8DR....................... 196, 667, 676, 685, 696 P9DDR.................... 200, 667, 676, 685, 696 P9DR....................... 201, 667, 676, 685, 696 PADDR ................... 205, 666, 676, 684, 695 PAODR ................... 205, 666, 675, 684, 695 PAPIN ..................... 206, 666, 675, 684, 695 parity error ..............................................383 PBDDR ................... 211, 667, 676, 685, 696 PBODR ................... 212, 667, 676, 685, 696 PBPIN ..................... 212, 667, 676, 685, 696 PCDDR ................... 218, 662, 672, 681, 691 PCNOCR................. 221, 660, 671, 680, 689 PCODR ................... 219, 662, 672, 681, 690 PCPIN ..................... 220, 662, 672, 681, 691 PCSR....................... 238, 664, 674, 683, 692 PDDDR ................... 218, 662, 672, 681, 691 PDNOCR ................ 221, 660, 671, 680, 689 PDODR ................... 219, 662, 672, 681, 690 PDPIN ..................... 220, 662, 672, 681, 691 PEDDR ................... 223, 661, 672, 681, 690 PENOCR................. 226, 660, 671, 680, 689 PEODR ................... 224, 661, 672, 681, 690 PEPIN ..................... 225, 661, 672, 681, 690 PFDDR.................... 223, 662, 672, 681, 690 PFNOCR ................. 226, 660, 671, 680, 689 PFODR.................... 224, 661, 672, 681, 690 PFPIN...................... 225, 661, 672, 681, 690 PGDDR ................... 228, 661, 672, 681, 690 PGNOCR ................ 229, 660, 671, 680, 689 PGODR ................... 228, 661, 672, 681, 690 PGPIN ..................... 229, 661, 672, 681, 690 Rev. 3.00 Mar 21, 2006 page 785 of 788 REJ09B0300-0300 Index Power-Down Modes ............................... 641 Program Counter (PC) .............................. 35 Program/Erase Protection ....................... 628 Program/Program-Verify ........................ 624 Program-Counter Relative ........................ 54 Programmer Mode.................................. 630 Pulse Output ........................................... 271 PWDPR .................. 236, 668, 677, 686, 697 PWDR..................... 236, 668, 677, 686, 697 PWM Decoding ...................................... 329 PWOER .................. 237, 667, 677, 686, 697 PWSL...................... 234, 668, 677, 686, 697 RDR ........................ 362, 668, 677, 686, 697 Register Direct .......................................... 52 Register field............................................. 50 Register Indirect ....................................... 52 Register Indirect with Displacement......... 52 Register Indirect with Post-Increment ...... 52 Register Indirect with Pre-Decrement ...... 53 Register information ............................... 153 Repeat Mode........................................... 157 Reset ......................................................... 83 Reset Exception Handling ........................ 83 RSR......................................................... 362 RXI ......................................................... 405 SAR ........................ 418, 668, 677, 686, 697 SARX...................... 419, 668, 677, 686, 697 SBYCR ................... 642, 664, 674, 683, 692 SCMR ..................... 368, 668, 677, 686, 697 SCR......................... 364, 668, 677, 686, 697 SEDGR ................... 327, 670, 679, 688, 700 Serial Communication Interface (SCI and IrDA) ................................... 359 Serial Formats......................................... 443 Shift Instructions....................................... 45 Shutdown Function................................. 523 Single Mode............................................ 592 SIRQCR.................. 552, 661, 672, 680, 690 Rev. 3.00 Mar 21, 2006 page 786 of 788 REJ09B0300-0300 Sleep Mode ............................................. 650 SMI ......................................................... 576 SMR ........................ 363, 668, 677, 686, 697 software activation .................................. 165 Software Protection................................. 628 Software Standby Mode.......................... 651 SSR ......................... 366, 668, 677, 686, 697 stack pointer (SP)...................................... 34 Stack Status............................................... 86 STCR ........................ 66, 667, 676, 685, 696 STR ......................... 545, 661, 672, 681, 690 Subactive Mode ...................................... 655 Subsleep Mode........................................ 654 SWDTEND ............................................. 160 SYSCR...................... 65, 667, 676, 685, 696 SYSCR2.................. 512, 664, 674, 683, 692 System Control Instructions...................... 49 TCNT ............. 291, 347, 666, 667, 675, 677, 684, 686, 695, 696 TCNT Count Timing............................... 302 TCONRI.................. 320, 670, 678, 687, 700 TCONRO ................ 323, 670, 679, 688, 700 TCONRS................. 325, 670, 679, 688, 700 TCOR...................... 291, 667, 677, 685, 696 TCORC ................... 300, 669, 678, 687, 699 TCR................ 268, 291, 665, 667, 674, 676, 683, 685, 693, 696 TCSR ..... 265, 294, 348, 664, 666, 667, 674, 675, 676, 683, 684, 685, 693, 695, 696 TDR ........................ 362, 668, 677, 686, 697 TEI .......................................................... 405 TICR ....................................................... 300 TICRF ..................... 300, 669, 678, 687, 699 TICRR..................... 300, 669, 678, 687, 699 TIER........................ 264, 664, 674, 683, 693 Timer Connection ................................... 317 TISR........................ 300, 669, 678, 687, 699 TOCR...................... 269, 665, 675, 683, 693 Toggle output.......................................... 313 Index Trap Instruction Exception Handling........ 85 TSR......................................................... 362 TWR ....................... 545, 660, 671, 680, 689 TXI.......................................................... 405 User Program Mode................................ 622 VSYNCO Output.................................... 342 Wait Control............................................139 Watch Mode............................................653 Watchdog Timer (WDT).........................345 Watchdog Timer Mode ...........................352 WOVI......................................................355 WSCR ..................... 125, 667, 676, 685, 696 WUEMRB................. 97, 661, 672, 681, 690 Rev. 3.00 Mar 21, 2006 page 787 of 788 REJ09B0300-0300 Index Rev. 3.00 Mar 21, 2006 page 788 of 788 REJ09B0300-0300 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2140B Group Publication Date: 1st Edition, March 2002 Rev.3.00, March 21, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c)2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8S/2140B Group Hardware Manual |
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